1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
58 extern bool itlb_multihit_kvm_mitigation;
60 int __read_mostly nx_huge_pages = -1;
61 #ifdef CONFIG_PREEMPT_RT
62 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
63 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
65 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
68 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
69 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
71 static const struct kernel_param_ops nx_huge_pages_ops = {
72 .set = set_nx_huge_pages,
73 .get = param_get_bool,
76 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
77 .set = set_nx_huge_pages_recovery_ratio,
78 .get = param_get_uint,
81 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
82 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
83 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
84 &nx_huge_pages_recovery_ratio, 0644);
85 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
87 static bool __read_mostly force_flush_and_sync_on_reuse;
88 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
91 * When setting this variable to true it enables Two-Dimensional-Paging
92 * where the hardware walks 2 page tables:
93 * 1. the guest-virtual to guest-physical
94 * 2. while doing 1. it walks guest-physical to host-physical
95 * If the hardware supports that we don't need to do shadow paging.
97 bool tdp_enabled = false;
99 static int max_huge_page_level __read_mostly;
100 static int tdp_root_level __read_mostly;
101 static int max_tdp_level __read_mostly;
104 AUDIT_PRE_PAGE_FAULT,
105 AUDIT_POST_PAGE_FAULT,
107 AUDIT_POST_PTE_WRITE,
114 module_param(dbg, bool, 0644);
117 #define PTE_PREFETCH_NUM 8
119 #define PT32_LEVEL_BITS 10
121 #define PT32_LEVEL_SHIFT(level) \
122 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
124 #define PT32_LVL_OFFSET_MASK(level) \
125 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT32_LEVEL_BITS))) - 1))
128 #define PT32_INDEX(address, level)\
129 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
132 #define PT32_BASE_ADDR_MASK PAGE_MASK
133 #define PT32_DIR_BASE_ADDR_MASK \
134 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
135 #define PT32_LVL_ADDR_MASK(level) \
136 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
137 * PT32_LEVEL_BITS))) - 1))
139 #include <trace/events/kvm.h>
141 /* make pte_list_desc fit well in cache lines */
142 #define PTE_LIST_EXT 14
145 * Slight optimization of cacheline layout, by putting `more' and `spte_count'
146 * at the start; then accessing it will only use one single cacheline for
147 * either full (entries==PTE_LIST_EXT) case or entries<=6.
149 struct pte_list_desc {
150 struct pte_list_desc *more;
152 * Stores number of entries stored in the pte_list_desc. No need to be
153 * u64 but just for easier alignment. When PTE_LIST_EXT, means full.
156 u64 *sptes[PTE_LIST_EXT];
159 struct kvm_shadow_walk_iterator {
167 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
168 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
170 shadow_walk_okay(&(_walker)); \
171 shadow_walk_next(&(_walker)))
173 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
174 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
175 shadow_walk_okay(&(_walker)); \
176 shadow_walk_next(&(_walker)))
178 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
179 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
180 shadow_walk_okay(&(_walker)) && \
181 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
182 __shadow_walk_next(&(_walker), spte))
184 static struct kmem_cache *pte_list_desc_cache;
185 struct kmem_cache *mmu_page_header_cache;
186 static struct percpu_counter kvm_total_used_mmu_pages;
188 static void mmu_spte_set(u64 *sptep, u64 spte);
189 static union kvm_mmu_page_role
190 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
192 struct kvm_mmu_role_regs {
193 const unsigned long cr0;
194 const unsigned long cr4;
198 #define CREATE_TRACE_POINTS
199 #include "mmutrace.h"
202 * Yes, lot's of underscores. They're a hint that you probably shouldn't be
203 * reading from the role_regs. Once the mmu_role is constructed, it becomes
204 * the single source of truth for the MMU's state.
206 #define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \
207 static inline bool __maybe_unused ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\
209 return !!(regs->reg & flag); \
211 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, pg, X86_CR0_PG);
212 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, wp, X86_CR0_WP);
213 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pse, X86_CR4_PSE);
214 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pae, X86_CR4_PAE);
215 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smep, X86_CR4_SMEP);
216 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smap, X86_CR4_SMAP);
217 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pke, X86_CR4_PKE);
218 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, la57, X86_CR4_LA57);
219 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, nx, EFER_NX);
220 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, lma, EFER_LMA);
223 * The MMU itself (with a valid role) is the single source of truth for the
224 * MMU. Do not use the regs used to build the MMU/role, nor the vCPU. The
225 * regs don't account for dependencies, e.g. clearing CR4 bits if CR0.PG=1,
226 * and the vCPU may be incorrect/irrelevant.
228 #define BUILD_MMU_ROLE_ACCESSOR(base_or_ext, reg, name) \
229 static inline bool __maybe_unused is_##reg##_##name(struct kvm_mmu *mmu) \
231 return !!(mmu->mmu_role. base_or_ext . reg##_##name); \
233 BUILD_MMU_ROLE_ACCESSOR(ext, cr0, pg);
234 BUILD_MMU_ROLE_ACCESSOR(base, cr0, wp);
235 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pse);
236 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pae);
237 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smep);
238 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, smap);
239 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, pke);
240 BUILD_MMU_ROLE_ACCESSOR(ext, cr4, la57);
241 BUILD_MMU_ROLE_ACCESSOR(base, efer, nx);
243 static struct kvm_mmu_role_regs vcpu_to_role_regs(struct kvm_vcpu *vcpu)
245 struct kvm_mmu_role_regs regs = {
246 .cr0 = kvm_read_cr0_bits(vcpu, KVM_MMU_CR0_ROLE_BITS),
247 .cr4 = kvm_read_cr4_bits(vcpu, KVM_MMU_CR4_ROLE_BITS),
248 .efer = vcpu->arch.efer,
254 static int role_regs_to_root_level(struct kvm_mmu_role_regs *regs)
256 if (!____is_cr0_pg(regs))
258 else if (____is_efer_lma(regs))
259 return ____is_cr4_la57(regs) ? PT64_ROOT_5LEVEL :
261 else if (____is_cr4_pae(regs))
262 return PT32E_ROOT_LEVEL;
264 return PT32_ROOT_LEVEL;
267 static inline bool kvm_available_flush_tlb_with_range(void)
269 return kvm_x86_ops.tlb_remote_flush_with_range;
272 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
273 struct kvm_tlb_range *range)
277 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
278 ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range);
281 kvm_flush_remote_tlbs(kvm);
284 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
285 u64 start_gfn, u64 pages)
287 struct kvm_tlb_range range;
289 range.start_gfn = start_gfn;
292 kvm_flush_remote_tlbs_with_range(kvm, &range);
295 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
298 u64 spte = make_mmio_spte(vcpu, gfn, access);
300 trace_mark_mmio_spte(sptep, gfn, spte);
301 mmu_spte_set(sptep, spte);
304 static gfn_t get_mmio_spte_gfn(u64 spte)
306 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
308 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
309 & shadow_nonpresent_or_rsvd_mask;
311 return gpa >> PAGE_SHIFT;
314 static unsigned get_mmio_spte_access(u64 spte)
316 return spte & shadow_mmio_access_mask;
319 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
321 u64 kvm_gen, spte_gen, gen;
323 gen = kvm_vcpu_memslots(vcpu)->generation;
324 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
327 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
328 spte_gen = get_mmio_spte_generation(spte);
330 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
331 return likely(kvm_gen == spte_gen);
334 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
335 struct x86_exception *exception)
340 static int is_cpuid_PSE36(void)
345 static gfn_t pse36_gfn_delta(u32 gpte)
347 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
349 return (gpte & PT32_DIR_PSE36_MASK) << shift;
353 static void __set_spte(u64 *sptep, u64 spte)
355 WRITE_ONCE(*sptep, spte);
358 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
360 WRITE_ONCE(*sptep, spte);
363 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
365 return xchg(sptep, spte);
368 static u64 __get_spte_lockless(u64 *sptep)
370 return READ_ONCE(*sptep);
381 static void count_spte_clear(u64 *sptep, u64 spte)
383 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
385 if (is_shadow_present_pte(spte))
388 /* Ensure the spte is completely set before we increase the count */
390 sp->clear_spte_count++;
393 static void __set_spte(u64 *sptep, u64 spte)
395 union split_spte *ssptep, sspte;
397 ssptep = (union split_spte *)sptep;
398 sspte = (union split_spte)spte;
400 ssptep->spte_high = sspte.spte_high;
403 * If we map the spte from nonpresent to present, We should store
404 * the high bits firstly, then set present bit, so cpu can not
405 * fetch this spte while we are setting the spte.
409 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
412 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
414 union split_spte *ssptep, sspte;
416 ssptep = (union split_spte *)sptep;
417 sspte = (union split_spte)spte;
419 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
422 * If we map the spte from present to nonpresent, we should clear
423 * present bit firstly to avoid vcpu fetch the old high bits.
427 ssptep->spte_high = sspte.spte_high;
428 count_spte_clear(sptep, spte);
431 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
433 union split_spte *ssptep, sspte, orig;
435 ssptep = (union split_spte *)sptep;
436 sspte = (union split_spte)spte;
438 /* xchg acts as a barrier before the setting of the high bits */
439 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
440 orig.spte_high = ssptep->spte_high;
441 ssptep->spte_high = sspte.spte_high;
442 count_spte_clear(sptep, spte);
448 * The idea using the light way get the spte on x86_32 guest is from
449 * gup_get_pte (mm/gup.c).
451 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
452 * coalesces them and we are running out of the MMU lock. Therefore
453 * we need to protect against in-progress updates of the spte.
455 * Reading the spte while an update is in progress may get the old value
456 * for the high part of the spte. The race is fine for a present->non-present
457 * change (because the high part of the spte is ignored for non-present spte),
458 * but for a present->present change we must reread the spte.
460 * All such changes are done in two steps (present->non-present and
461 * non-present->present), hence it is enough to count the number of
462 * present->non-present updates: if it changed while reading the spte,
463 * we might have hit the race. This is done using clear_spte_count.
465 static u64 __get_spte_lockless(u64 *sptep)
467 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
468 union split_spte spte, *orig = (union split_spte *)sptep;
472 count = sp->clear_spte_count;
475 spte.spte_low = orig->spte_low;
478 spte.spte_high = orig->spte_high;
481 if (unlikely(spte.spte_low != orig->spte_low ||
482 count != sp->clear_spte_count))
489 static bool spte_has_volatile_bits(u64 spte)
491 if (!is_shadow_present_pte(spte))
495 * Always atomically update spte if it can be updated
496 * out of mmu-lock, it can ensure dirty bit is not lost,
497 * also, it can help us to get a stable is_writable_pte()
498 * to ensure tlb flush is not missed.
500 if (spte_can_locklessly_be_made_writable(spte) ||
501 is_access_track_spte(spte))
504 if (spte_ad_enabled(spte)) {
505 if ((spte & shadow_accessed_mask) == 0 ||
506 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
513 /* Rules for using mmu_spte_set:
514 * Set the sptep from nonpresent to present.
515 * Note: the sptep being assigned *must* be either not present
516 * or in a state where the hardware will not attempt to update
519 static void mmu_spte_set(u64 *sptep, u64 new_spte)
521 WARN_ON(is_shadow_present_pte(*sptep));
522 __set_spte(sptep, new_spte);
526 * Update the SPTE (excluding the PFN), but do not track changes in its
527 * accessed/dirty status.
529 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
531 u64 old_spte = *sptep;
533 WARN_ON(!is_shadow_present_pte(new_spte));
535 if (!is_shadow_present_pte(old_spte)) {
536 mmu_spte_set(sptep, new_spte);
540 if (!spte_has_volatile_bits(old_spte))
541 __update_clear_spte_fast(sptep, new_spte);
543 old_spte = __update_clear_spte_slow(sptep, new_spte);
545 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
550 /* Rules for using mmu_spte_update:
551 * Update the state bits, it means the mapped pfn is not changed.
553 * Whenever we overwrite a writable spte with a read-only one we
554 * should flush remote TLBs. Otherwise rmap_write_protect
555 * will find a read-only spte, even though the writable spte
556 * might be cached on a CPU's TLB, the return value indicates this
559 * Returns true if the TLB needs to be flushed
561 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
564 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
566 if (!is_shadow_present_pte(old_spte))
570 * For the spte updated out of mmu-lock is safe, since
571 * we always atomically update it, see the comments in
572 * spte_has_volatile_bits().
574 if (spte_can_locklessly_be_made_writable(old_spte) &&
575 !is_writable_pte(new_spte))
579 * Flush TLB when accessed/dirty states are changed in the page tables,
580 * to guarantee consistency between TLB and page tables.
583 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
585 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
588 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
590 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
597 * Rules for using mmu_spte_clear_track_bits:
598 * It sets the sptep from present to nonpresent, and track the
599 * state bits, it is used to clear the last level sptep.
600 * Returns the old PTE.
602 static int mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
605 u64 old_spte = *sptep;
606 int level = sptep_to_sp(sptep)->role.level;
608 if (!spte_has_volatile_bits(old_spte))
609 __update_clear_spte_fast(sptep, 0ull);
611 old_spte = __update_clear_spte_slow(sptep, 0ull);
613 if (!is_shadow_present_pte(old_spte))
616 kvm_update_page_stats(kvm, level, -1);
618 pfn = spte_to_pfn(old_spte);
621 * KVM does not hold the refcount of the page used by
622 * kvm mmu, before reclaiming the page, we should
623 * unmap it from mmu first.
625 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
627 if (is_accessed_spte(old_spte))
628 kvm_set_pfn_accessed(pfn);
630 if (is_dirty_spte(old_spte))
631 kvm_set_pfn_dirty(pfn);
637 * Rules for using mmu_spte_clear_no_track:
638 * Directly clear spte without caring the state bits of sptep,
639 * it is used to set the upper level spte.
641 static void mmu_spte_clear_no_track(u64 *sptep)
643 __update_clear_spte_fast(sptep, 0ull);
646 static u64 mmu_spte_get_lockless(u64 *sptep)
648 return __get_spte_lockless(sptep);
651 /* Restore an acc-track PTE back to a regular PTE */
652 static u64 restore_acc_track_spte(u64 spte)
655 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
656 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
658 WARN_ON_ONCE(spte_ad_enabled(spte));
659 WARN_ON_ONCE(!is_access_track_spte(spte));
661 new_spte &= ~shadow_acc_track_mask;
662 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
663 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
664 new_spte |= saved_bits;
669 /* Returns the Accessed status of the PTE and resets it at the same time. */
670 static bool mmu_spte_age(u64 *sptep)
672 u64 spte = mmu_spte_get_lockless(sptep);
674 if (!is_accessed_spte(spte))
677 if (spte_ad_enabled(spte)) {
678 clear_bit((ffs(shadow_accessed_mask) - 1),
679 (unsigned long *)sptep);
682 * Capture the dirty status of the page, so that it doesn't get
683 * lost when the SPTE is marked for access tracking.
685 if (is_writable_pte(spte))
686 kvm_set_pfn_dirty(spte_to_pfn(spte));
688 spte = mark_spte_for_access_track(spte);
689 mmu_spte_update_no_track(sptep, spte);
695 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
697 if (is_tdp_mmu(vcpu->arch.mmu)) {
698 kvm_tdp_mmu_walk_lockless_begin();
701 * Prevent page table teardown by making any free-er wait during
702 * kvm_flush_remote_tlbs() IPI to all active vcpus.
707 * Make sure a following spte read is not reordered ahead of the write
710 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
714 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
716 if (is_tdp_mmu(vcpu->arch.mmu)) {
717 kvm_tdp_mmu_walk_lockless_end();
720 * Make sure the write to vcpu->mode is not reordered in front of
721 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
722 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
724 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
729 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
733 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
734 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
735 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
738 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
739 PT64_ROOT_MAX_LEVEL);
742 if (maybe_indirect) {
743 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
744 PT64_ROOT_MAX_LEVEL);
748 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
749 PT64_ROOT_MAX_LEVEL);
752 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
754 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
755 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
756 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
757 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
760 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
762 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
765 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
767 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
770 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
772 if (!sp->role.direct)
773 return sp->gfns[index];
775 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
778 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
780 if (!sp->role.direct) {
781 sp->gfns[index] = gfn;
785 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
786 pr_err_ratelimited("gfn mismatch under direct page %llx "
787 "(expected %llx, got %llx)\n",
789 kvm_mmu_page_get_gfn(sp, index), gfn);
793 * Return the pointer to the large page information for a given gfn,
794 * handling slots that are not large page aligned.
796 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
797 const struct kvm_memory_slot *slot, int level)
801 idx = gfn_to_index(gfn, slot->base_gfn, level);
802 return &slot->arch.lpage_info[level - 2][idx];
805 static void update_gfn_disallow_lpage_count(const struct kvm_memory_slot *slot,
806 gfn_t gfn, int count)
808 struct kvm_lpage_info *linfo;
811 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
812 linfo = lpage_info_slot(gfn, slot, i);
813 linfo->disallow_lpage += count;
814 WARN_ON(linfo->disallow_lpage < 0);
818 void kvm_mmu_gfn_disallow_lpage(const struct kvm_memory_slot *slot, gfn_t gfn)
820 update_gfn_disallow_lpage_count(slot, gfn, 1);
823 void kvm_mmu_gfn_allow_lpage(const struct kvm_memory_slot *slot, gfn_t gfn)
825 update_gfn_disallow_lpage_count(slot, gfn, -1);
828 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
830 struct kvm_memslots *slots;
831 struct kvm_memory_slot *slot;
834 kvm->arch.indirect_shadow_pages++;
836 slots = kvm_memslots_for_spte_role(kvm, sp->role);
837 slot = __gfn_to_memslot(slots, gfn);
839 /* the non-leaf shadow pages are keeping readonly. */
840 if (sp->role.level > PG_LEVEL_4K)
841 return kvm_slot_page_track_add_page(kvm, slot, gfn,
842 KVM_PAGE_TRACK_WRITE);
844 kvm_mmu_gfn_disallow_lpage(slot, gfn);
847 void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
849 if (sp->lpage_disallowed)
852 ++kvm->stat.nx_lpage_splits;
853 list_add_tail(&sp->lpage_disallowed_link,
854 &kvm->arch.lpage_disallowed_mmu_pages);
855 sp->lpage_disallowed = true;
858 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
860 struct kvm_memslots *slots;
861 struct kvm_memory_slot *slot;
864 kvm->arch.indirect_shadow_pages--;
866 slots = kvm_memslots_for_spte_role(kvm, sp->role);
867 slot = __gfn_to_memslot(slots, gfn);
868 if (sp->role.level > PG_LEVEL_4K)
869 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
870 KVM_PAGE_TRACK_WRITE);
872 kvm_mmu_gfn_allow_lpage(slot, gfn);
875 void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
877 --kvm->stat.nx_lpage_splits;
878 sp->lpage_disallowed = false;
879 list_del(&sp->lpage_disallowed_link);
882 static struct kvm_memory_slot *
883 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
886 struct kvm_memory_slot *slot;
888 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
889 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
891 if (no_dirty_log && kvm_slot_dirty_track_enabled(slot))
898 * About rmap_head encoding:
900 * If the bit zero of rmap_head->val is clear, then it points to the only spte
901 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
902 * pte_list_desc containing more mappings.
906 * Returns the number of pointers in the rmap chain, not counting the new one.
908 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
909 struct kvm_rmap_head *rmap_head)
911 struct pte_list_desc *desc;
914 if (!rmap_head->val) {
915 rmap_printk("%p %llx 0->1\n", spte, *spte);
916 rmap_head->val = (unsigned long)spte;
917 } else if (!(rmap_head->val & 1)) {
918 rmap_printk("%p %llx 1->many\n", spte, *spte);
919 desc = mmu_alloc_pte_list_desc(vcpu);
920 desc->sptes[0] = (u64 *)rmap_head->val;
921 desc->sptes[1] = spte;
922 desc->spte_count = 2;
923 rmap_head->val = (unsigned long)desc | 1;
926 rmap_printk("%p %llx many->many\n", spte, *spte);
927 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
928 while (desc->spte_count == PTE_LIST_EXT) {
929 count += PTE_LIST_EXT;
931 desc->more = mmu_alloc_pte_list_desc(vcpu);
933 desc->spte_count = 0;
938 count += desc->spte_count;
939 desc->sptes[desc->spte_count++] = spte;
945 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
946 struct pte_list_desc *desc, int i,
947 struct pte_list_desc *prev_desc)
949 int j = desc->spte_count - 1;
951 desc->sptes[i] = desc->sptes[j];
952 desc->sptes[j] = NULL;
954 if (desc->spte_count)
956 if (!prev_desc && !desc->more)
960 prev_desc->more = desc->more;
962 rmap_head->val = (unsigned long)desc->more | 1;
963 mmu_free_pte_list_desc(desc);
966 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
968 struct pte_list_desc *desc;
969 struct pte_list_desc *prev_desc;
972 if (!rmap_head->val) {
973 pr_err("%s: %p 0->BUG\n", __func__, spte);
975 } else if (!(rmap_head->val & 1)) {
976 rmap_printk("%p 1->0\n", spte);
977 if ((u64 *)rmap_head->val != spte) {
978 pr_err("%s: %p 1->BUG\n", __func__, spte);
983 rmap_printk("%p many->many\n", spte);
984 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
987 for (i = 0; i < desc->spte_count; ++i) {
988 if (desc->sptes[i] == spte) {
989 pte_list_desc_remove_entry(rmap_head,
997 pr_err("%s: %p many->many\n", __func__, spte);
1002 static void pte_list_remove(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1005 mmu_spte_clear_track_bits(kvm, sptep);
1006 __pte_list_remove(sptep, rmap_head);
1009 /* Return true if rmap existed, false otherwise */
1010 static bool pte_list_destroy(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1012 struct pte_list_desc *desc, *next;
1015 if (!rmap_head->val)
1018 if (!(rmap_head->val & 1)) {
1019 mmu_spte_clear_track_bits(kvm, (u64 *)rmap_head->val);
1023 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1025 for (; desc; desc = next) {
1026 for (i = 0; i < desc->spte_count; i++)
1027 mmu_spte_clear_track_bits(kvm, desc->sptes[i]);
1029 mmu_free_pte_list_desc(desc);
1032 /* rmap_head is meaningless now, remember to reset it */
1037 unsigned int pte_list_count(struct kvm_rmap_head *rmap_head)
1039 struct pte_list_desc *desc;
1040 unsigned int count = 0;
1042 if (!rmap_head->val)
1044 else if (!(rmap_head->val & 1))
1047 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1050 count += desc->spte_count;
1057 static struct kvm_rmap_head *gfn_to_rmap(gfn_t gfn, int level,
1058 const struct kvm_memory_slot *slot)
1062 idx = gfn_to_index(gfn, slot->base_gfn, level);
1063 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
1066 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1068 struct kvm_mmu_memory_cache *mc;
1070 mc = &vcpu->arch.mmu_pte_list_desc_cache;
1071 return kvm_mmu_memory_cache_nr_free_objects(mc);
1074 static void rmap_remove(struct kvm *kvm, u64 *spte)
1076 struct kvm_memslots *slots;
1077 struct kvm_memory_slot *slot;
1078 struct kvm_mmu_page *sp;
1080 struct kvm_rmap_head *rmap_head;
1082 sp = sptep_to_sp(spte);
1083 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1086 * Unlike rmap_add, rmap_remove does not run in the context of a vCPU
1087 * so we have to determine which memslots to use based on context
1088 * information in sp->role.
1090 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1092 slot = __gfn_to_memslot(slots, gfn);
1093 rmap_head = gfn_to_rmap(gfn, sp->role.level, slot);
1095 __pte_list_remove(spte, rmap_head);
1099 * Used by the following functions to iterate through the sptes linked by a
1100 * rmap. All fields are private and not assumed to be used outside.
1102 struct rmap_iterator {
1103 /* private fields */
1104 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1105 int pos; /* index of the sptep */
1109 * Iteration must be started by this function. This should also be used after
1110 * removing/dropping sptes from the rmap link because in such cases the
1111 * information in the iterator may not be valid.
1113 * Returns sptep if found, NULL otherwise.
1115 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1116 struct rmap_iterator *iter)
1120 if (!rmap_head->val)
1123 if (!(rmap_head->val & 1)) {
1125 sptep = (u64 *)rmap_head->val;
1129 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1131 sptep = iter->desc->sptes[iter->pos];
1133 BUG_ON(!is_shadow_present_pte(*sptep));
1138 * Must be used with a valid iterator: e.g. after rmap_get_first().
1140 * Returns sptep if found, NULL otherwise.
1142 static u64 *rmap_get_next(struct rmap_iterator *iter)
1147 if (iter->pos < PTE_LIST_EXT - 1) {
1149 sptep = iter->desc->sptes[iter->pos];
1154 iter->desc = iter->desc->more;
1158 /* desc->sptes[0] cannot be NULL */
1159 sptep = iter->desc->sptes[iter->pos];
1166 BUG_ON(!is_shadow_present_pte(*sptep));
1170 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1171 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1172 _spte_; _spte_ = rmap_get_next(_iter_))
1174 static void drop_spte(struct kvm *kvm, u64 *sptep)
1176 u64 old_spte = mmu_spte_clear_track_bits(kvm, sptep);
1178 if (is_shadow_present_pte(old_spte))
1179 rmap_remove(kvm, sptep);
1183 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1185 if (is_large_pte(*sptep)) {
1186 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1187 drop_spte(kvm, sptep);
1194 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1196 if (__drop_large_spte(vcpu->kvm, sptep)) {
1197 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1199 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1200 KVM_PAGES_PER_HPAGE(sp->role.level));
1205 * Write-protect on the specified @sptep, @pt_protect indicates whether
1206 * spte write-protection is caused by protecting shadow page table.
1208 * Note: write protection is difference between dirty logging and spte
1210 * - for dirty logging, the spte can be set to writable at anytime if
1211 * its dirty bitmap is properly set.
1212 * - for spte protection, the spte can be writable only after unsync-ing
1215 * Return true if tlb need be flushed.
1217 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1221 if (!is_writable_pte(spte) &&
1222 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1225 rmap_printk("spte %p %llx\n", sptep, *sptep);
1228 spte &= ~shadow_mmu_writable_mask;
1229 spte = spte & ~PT_WRITABLE_MASK;
1231 return mmu_spte_update(sptep, spte);
1234 static bool __rmap_write_protect(struct kvm *kvm,
1235 struct kvm_rmap_head *rmap_head,
1239 struct rmap_iterator iter;
1242 for_each_rmap_spte(rmap_head, &iter, sptep)
1243 flush |= spte_write_protect(sptep, pt_protect);
1248 static bool spte_clear_dirty(u64 *sptep)
1252 rmap_printk("spte %p %llx\n", sptep, *sptep);
1254 MMU_WARN_ON(!spte_ad_enabled(spte));
1255 spte &= ~shadow_dirty_mask;
1256 return mmu_spte_update(sptep, spte);
1259 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1261 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1262 (unsigned long *)sptep);
1263 if (was_writable && !spte_ad_enabled(*sptep))
1264 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1266 return was_writable;
1270 * Gets the GFN ready for another round of dirty logging by clearing the
1271 * - D bit on ad-enabled SPTEs, and
1272 * - W bit on ad-disabled SPTEs.
1273 * Returns true iff any D or W bits were cleared.
1275 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1276 const struct kvm_memory_slot *slot)
1279 struct rmap_iterator iter;
1282 for_each_rmap_spte(rmap_head, &iter, sptep)
1283 if (spte_ad_need_write_protect(*sptep))
1284 flush |= spte_wrprot_for_clear_dirty(sptep);
1286 flush |= spte_clear_dirty(sptep);
1292 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1293 * @kvm: kvm instance
1294 * @slot: slot to protect
1295 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1296 * @mask: indicates which pages we should protect
1298 * Used when we do not need to care about huge page mappings.
1300 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1301 struct kvm_memory_slot *slot,
1302 gfn_t gfn_offset, unsigned long mask)
1304 struct kvm_rmap_head *rmap_head;
1306 if (is_tdp_mmu_enabled(kvm))
1307 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1308 slot->base_gfn + gfn_offset, mask, true);
1310 if (!kvm_memslots_have_rmaps(kvm))
1314 rmap_head = gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1316 __rmap_write_protect(kvm, rmap_head, false);
1318 /* clear the first set bit */
1324 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1325 * protect the page if the D-bit isn't supported.
1326 * @kvm: kvm instance
1327 * @slot: slot to clear D-bit
1328 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1329 * @mask: indicates which pages we should clear D-bit
1331 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1333 static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1334 struct kvm_memory_slot *slot,
1335 gfn_t gfn_offset, unsigned long mask)
1337 struct kvm_rmap_head *rmap_head;
1339 if (is_tdp_mmu_enabled(kvm))
1340 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1341 slot->base_gfn + gfn_offset, mask, false);
1343 if (!kvm_memslots_have_rmaps(kvm))
1347 rmap_head = gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1349 __rmap_clear_dirty(kvm, rmap_head, slot);
1351 /* clear the first set bit */
1357 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1360 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1361 * enable dirty logging for them.
1363 * We need to care about huge page mappings: e.g. during dirty logging we may
1364 * have such mappings.
1366 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1367 struct kvm_memory_slot *slot,
1368 gfn_t gfn_offset, unsigned long mask)
1371 * Huge pages are NOT write protected when we start dirty logging in
1372 * initially-all-set mode; must write protect them here so that they
1373 * are split to 4K on the first write.
1375 * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn
1376 * of memslot has no such restriction, so the range can cross two large
1379 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) {
1380 gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask);
1381 gfn_t end = slot->base_gfn + gfn_offset + __fls(mask);
1383 kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M);
1385 /* Cross two large pages? */
1386 if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) !=
1387 ALIGN(end << PAGE_SHIFT, PMD_SIZE))
1388 kvm_mmu_slot_gfn_write_protect(kvm, slot, end,
1392 /* Now handle 4K PTEs. */
1393 if (kvm_x86_ops.cpu_dirty_log_size)
1394 kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
1396 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1399 int kvm_cpu_dirty_log_size(void)
1401 return kvm_x86_ops.cpu_dirty_log_size;
1404 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1405 struct kvm_memory_slot *slot, u64 gfn,
1408 struct kvm_rmap_head *rmap_head;
1410 bool write_protected = false;
1412 if (kvm_memslots_have_rmaps(kvm)) {
1413 for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1414 rmap_head = gfn_to_rmap(gfn, i, slot);
1415 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1419 if (is_tdp_mmu_enabled(kvm))
1421 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level);
1423 return write_protected;
1426 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1428 struct kvm_memory_slot *slot;
1430 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1431 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K);
1434 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1435 const struct kvm_memory_slot *slot)
1437 return pte_list_destroy(kvm, rmap_head);
1440 static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1441 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1444 return kvm_zap_rmapp(kvm, rmap_head, slot);
1447 static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1448 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1452 struct rmap_iterator iter;
1457 WARN_ON(pte_huge(pte));
1458 new_pfn = pte_pfn(pte);
1461 for_each_rmap_spte(rmap_head, &iter, sptep) {
1462 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1463 sptep, *sptep, gfn, level);
1467 if (pte_write(pte)) {
1468 pte_list_remove(kvm, rmap_head, sptep);
1471 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1474 mmu_spte_clear_track_bits(kvm, sptep);
1475 mmu_spte_set(sptep, new_spte);
1479 if (need_flush && kvm_available_flush_tlb_with_range()) {
1480 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1487 struct slot_rmap_walk_iterator {
1489 const struct kvm_memory_slot *slot;
1495 /* output fields. */
1497 struct kvm_rmap_head *rmap;
1500 /* private field. */
1501 struct kvm_rmap_head *end_rmap;
1505 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1507 iterator->level = level;
1508 iterator->gfn = iterator->start_gfn;
1509 iterator->rmap = gfn_to_rmap(iterator->gfn, level, iterator->slot);
1510 iterator->end_rmap = gfn_to_rmap(iterator->end_gfn, level, iterator->slot);
1514 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1515 const struct kvm_memory_slot *slot, int start_level,
1516 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1518 iterator->slot = slot;
1519 iterator->start_level = start_level;
1520 iterator->end_level = end_level;
1521 iterator->start_gfn = start_gfn;
1522 iterator->end_gfn = end_gfn;
1524 rmap_walk_init_level(iterator, iterator->start_level);
1527 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1529 return !!iterator->rmap;
1532 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1534 if (++iterator->rmap <= iterator->end_rmap) {
1535 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1539 if (++iterator->level > iterator->end_level) {
1540 iterator->rmap = NULL;
1544 rmap_walk_init_level(iterator, iterator->level);
1547 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1548 _start_gfn, _end_gfn, _iter_) \
1549 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1550 _end_level_, _start_gfn, _end_gfn); \
1551 slot_rmap_walk_okay(_iter_); \
1552 slot_rmap_walk_next(_iter_))
1554 typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1555 struct kvm_memory_slot *slot, gfn_t gfn,
1556 int level, pte_t pte);
1558 static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm,
1559 struct kvm_gfn_range *range,
1560 rmap_handler_t handler)
1562 struct slot_rmap_walk_iterator iterator;
1565 for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL,
1566 range->start, range->end - 1, &iterator)
1567 ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn,
1568 iterator.level, range->pte);
1573 bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
1577 if (kvm_memslots_have_rmaps(kvm))
1578 flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp);
1580 if (is_tdp_mmu_enabled(kvm))
1581 flush |= kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush);
1586 bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1590 if (kvm_memslots_have_rmaps(kvm))
1591 flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp);
1593 if (is_tdp_mmu_enabled(kvm))
1594 flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range);
1599 static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1600 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1604 struct rmap_iterator iter;
1607 for_each_rmap_spte(rmap_head, &iter, sptep)
1608 young |= mmu_spte_age(sptep);
1613 static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1614 struct kvm_memory_slot *slot, gfn_t gfn,
1615 int level, pte_t unused)
1618 struct rmap_iterator iter;
1620 for_each_rmap_spte(rmap_head, &iter, sptep)
1621 if (is_accessed_spte(*sptep))
1626 #define RMAP_RECYCLE_THRESHOLD 1000
1628 static void rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1630 struct kvm_memory_slot *slot;
1631 struct kvm_mmu_page *sp;
1632 struct kvm_rmap_head *rmap_head;
1635 sp = sptep_to_sp(spte);
1636 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1637 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1638 rmap_head = gfn_to_rmap(gfn, sp->role.level, slot);
1639 rmap_count = pte_list_add(vcpu, spte, rmap_head);
1641 if (rmap_count > RMAP_RECYCLE_THRESHOLD) {
1642 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0));
1643 kvm_flush_remote_tlbs_with_address(
1644 vcpu->kvm, sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level));
1648 bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1652 if (kvm_memslots_have_rmaps(kvm))
1653 young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp);
1655 if (is_tdp_mmu_enabled(kvm))
1656 young |= kvm_tdp_mmu_age_gfn_range(kvm, range);
1661 bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1665 if (kvm_memslots_have_rmaps(kvm))
1666 young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp);
1668 if (is_tdp_mmu_enabled(kvm))
1669 young |= kvm_tdp_mmu_test_age_gfn(kvm, range);
1675 static int is_empty_shadow_page(u64 *spt)
1680 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1681 if (is_shadow_present_pte(*pos)) {
1682 printk(KERN_ERR "%s: %p %llx\n", __func__,
1691 * This value is the sum of all of the kvm instances's
1692 * kvm->arch.n_used_mmu_pages values. We need a global,
1693 * aggregate version in order to make the slab shrinker
1696 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, long nr)
1698 kvm->arch.n_used_mmu_pages += nr;
1699 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1702 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1704 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1705 hlist_del(&sp->hash_link);
1706 list_del(&sp->link);
1707 free_page((unsigned long)sp->spt);
1708 if (!sp->role.direct)
1709 free_page((unsigned long)sp->gfns);
1710 kmem_cache_free(mmu_page_header_cache, sp);
1713 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1715 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1718 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1719 struct kvm_mmu_page *sp, u64 *parent_pte)
1724 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1727 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1730 __pte_list_remove(parent_pte, &sp->parent_ptes);
1733 static void drop_parent_pte(struct kvm_mmu_page *sp,
1736 mmu_page_remove_parent_pte(sp, parent_pte);
1737 mmu_spte_clear_no_track(parent_pte);
1740 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1742 struct kvm_mmu_page *sp;
1744 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1745 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1747 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1748 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1751 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1752 * depends on valid pages being added to the head of the list. See
1753 * comments in kvm_zap_obsolete_pages().
1755 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1756 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1757 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1761 static void mark_unsync(u64 *spte);
1762 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1765 struct rmap_iterator iter;
1767 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1772 static void mark_unsync(u64 *spte)
1774 struct kvm_mmu_page *sp;
1777 sp = sptep_to_sp(spte);
1778 index = spte - sp->spt;
1779 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1781 if (sp->unsync_children++)
1783 kvm_mmu_mark_parents_unsync(sp);
1786 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1787 struct kvm_mmu_page *sp)
1792 #define KVM_PAGE_ARRAY_NR 16
1794 struct kvm_mmu_pages {
1795 struct mmu_page_and_offset {
1796 struct kvm_mmu_page *sp;
1798 } page[KVM_PAGE_ARRAY_NR];
1802 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1808 for (i=0; i < pvec->nr; i++)
1809 if (pvec->page[i].sp == sp)
1812 pvec->page[pvec->nr].sp = sp;
1813 pvec->page[pvec->nr].idx = idx;
1815 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1818 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1820 --sp->unsync_children;
1821 WARN_ON((int)sp->unsync_children < 0);
1822 __clear_bit(idx, sp->unsync_child_bitmap);
1825 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1826 struct kvm_mmu_pages *pvec)
1828 int i, ret, nr_unsync_leaf = 0;
1830 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1831 struct kvm_mmu_page *child;
1832 u64 ent = sp->spt[i];
1834 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1835 clear_unsync_child_bit(sp, i);
1839 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1841 if (child->unsync_children) {
1842 if (mmu_pages_add(pvec, child, i))
1845 ret = __mmu_unsync_walk(child, pvec);
1847 clear_unsync_child_bit(sp, i);
1849 } else if (ret > 0) {
1850 nr_unsync_leaf += ret;
1853 } else if (child->unsync) {
1855 if (mmu_pages_add(pvec, child, i))
1858 clear_unsync_child_bit(sp, i);
1861 return nr_unsync_leaf;
1864 #define INVALID_INDEX (-1)
1866 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1867 struct kvm_mmu_pages *pvec)
1870 if (!sp->unsync_children)
1873 mmu_pages_add(pvec, sp, INVALID_INDEX);
1874 return __mmu_unsync_walk(sp, pvec);
1877 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1879 WARN_ON(!sp->unsync);
1880 trace_kvm_mmu_sync_page(sp);
1882 --kvm->stat.mmu_unsync;
1885 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1886 struct list_head *invalid_list);
1887 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1888 struct list_head *invalid_list);
1890 #define for_each_valid_sp(_kvm, _sp, _list) \
1891 hlist_for_each_entry(_sp, _list, hash_link) \
1892 if (is_obsolete_sp((_kvm), (_sp))) { \
1895 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1896 for_each_valid_sp(_kvm, _sp, \
1897 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1898 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1900 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1901 struct list_head *invalid_list)
1903 int ret = vcpu->arch.mmu->sync_page(vcpu, sp);
1906 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1913 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1914 struct list_head *invalid_list,
1917 if (!remote_flush && list_empty(invalid_list))
1920 if (!list_empty(invalid_list))
1921 kvm_mmu_commit_zap_page(kvm, invalid_list);
1923 kvm_flush_remote_tlbs(kvm);
1927 #ifdef CONFIG_KVM_MMU_AUDIT
1928 #include "mmu_audit.c"
1930 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1931 static void mmu_audit_disable(void) { }
1934 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1936 return sp->role.invalid ||
1937 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1940 struct mmu_page_path {
1941 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1942 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1945 #define for_each_sp(pvec, sp, parents, i) \
1946 for (i = mmu_pages_first(&pvec, &parents); \
1947 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1948 i = mmu_pages_next(&pvec, &parents, i))
1950 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1951 struct mmu_page_path *parents,
1956 for (n = i+1; n < pvec->nr; n++) {
1957 struct kvm_mmu_page *sp = pvec->page[n].sp;
1958 unsigned idx = pvec->page[n].idx;
1959 int level = sp->role.level;
1961 parents->idx[level-1] = idx;
1962 if (level == PG_LEVEL_4K)
1965 parents->parent[level-2] = sp;
1971 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1972 struct mmu_page_path *parents)
1974 struct kvm_mmu_page *sp;
1980 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1982 sp = pvec->page[0].sp;
1983 level = sp->role.level;
1984 WARN_ON(level == PG_LEVEL_4K);
1986 parents->parent[level-2] = sp;
1988 /* Also set up a sentinel. Further entries in pvec are all
1989 * children of sp, so this element is never overwritten.
1991 parents->parent[level-1] = NULL;
1992 return mmu_pages_next(pvec, parents, 0);
1995 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1997 struct kvm_mmu_page *sp;
1998 unsigned int level = 0;
2001 unsigned int idx = parents->idx[level];
2002 sp = parents->parent[level];
2006 WARN_ON(idx == INVALID_INDEX);
2007 clear_unsync_child_bit(sp, idx);
2009 } while (!sp->unsync_children);
2012 static int mmu_sync_children(struct kvm_vcpu *vcpu,
2013 struct kvm_mmu_page *parent, bool can_yield)
2016 struct kvm_mmu_page *sp;
2017 struct mmu_page_path parents;
2018 struct kvm_mmu_pages pages;
2019 LIST_HEAD(invalid_list);
2022 while (mmu_unsync_walk(parent, &pages)) {
2023 bool protected = false;
2025 for_each_sp(pages, sp, parents, i)
2026 protected |= rmap_write_protect(vcpu, sp->gfn);
2029 kvm_mmu_remote_flush_or_zap(vcpu->kvm, &invalid_list, true);
2033 for_each_sp(pages, sp, parents, i) {
2034 kvm_unlink_unsync_page(vcpu->kvm, sp);
2035 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2036 mmu_pages_clear_parents(&parents);
2038 if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) {
2039 kvm_mmu_remote_flush_or_zap(vcpu->kvm, &invalid_list, flush);
2041 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2045 cond_resched_rwlock_write(&vcpu->kvm->mmu_lock);
2050 kvm_mmu_remote_flush_or_zap(vcpu->kvm, &invalid_list, flush);
2054 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2056 atomic_set(&sp->write_flooding_count, 0);
2059 static void clear_sp_write_flooding_count(u64 *spte)
2061 __clear_sp_write_flooding_count(sptep_to_sp(spte));
2064 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2069 unsigned int access)
2071 bool direct_mmu = vcpu->arch.mmu->direct_map;
2072 union kvm_mmu_page_role role;
2073 struct hlist_head *sp_list;
2075 struct kvm_mmu_page *sp;
2077 LIST_HEAD(invalid_list);
2079 role = vcpu->arch.mmu->mmu_role.base;
2081 role.direct = direct;
2083 role.gpte_is_8_bytes = true;
2084 role.access = access;
2085 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2086 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2087 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2088 role.quadrant = quadrant;
2091 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2092 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2093 if (sp->gfn != gfn) {
2098 if (sp->role.word != role.word) {
2100 * If the guest is creating an upper-level page, zap
2101 * unsync pages for the same gfn. While it's possible
2102 * the guest is using recursive page tables, in all
2103 * likelihood the guest has stopped using the unsync
2104 * page and is installing a completely unrelated page.
2105 * Unsync pages must not be left as is, because the new
2106 * upper-level page will be write-protected.
2108 if (level > PG_LEVEL_4K && sp->unsync)
2109 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2115 goto trace_get_page;
2119 * The page is good, but is stale. kvm_sync_page does
2120 * get the latest guest state, but (unlike mmu_unsync_children)
2121 * it doesn't write-protect the page or mark it synchronized!
2122 * This way the validity of the mapping is ensured, but the
2123 * overhead of write protection is not incurred until the
2124 * guest invalidates the TLB mapping. This allows multiple
2125 * SPs for a single gfn to be unsync.
2127 * If the sync fails, the page is zapped. If so, break
2128 * in order to rebuild it.
2130 if (!kvm_sync_page(vcpu, sp, &invalid_list))
2133 WARN_ON(!list_empty(&invalid_list));
2134 kvm_flush_remote_tlbs(vcpu->kvm);
2137 __clear_sp_write_flooding_count(sp);
2140 trace_kvm_mmu_get_page(sp, false);
2144 ++vcpu->kvm->stat.mmu_cache_miss;
2146 sp = kvm_mmu_alloc_page(vcpu, direct);
2150 hlist_add_head(&sp->hash_link, sp_list);
2152 account_shadowed(vcpu->kvm, sp);
2153 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2154 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2156 trace_kvm_mmu_get_page(sp, true);
2158 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2160 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2161 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2165 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2166 struct kvm_vcpu *vcpu, hpa_t root,
2169 iterator->addr = addr;
2170 iterator->shadow_addr = root;
2171 iterator->level = vcpu->arch.mmu->shadow_root_level;
2173 if (iterator->level == PT64_ROOT_4LEVEL &&
2174 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2175 !vcpu->arch.mmu->direct_map)
2178 if (iterator->level == PT32E_ROOT_LEVEL) {
2180 * prev_root is currently only used for 64-bit hosts. So only
2181 * the active root_hpa is valid here.
2183 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2185 iterator->shadow_addr
2186 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2187 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2189 if (!iterator->shadow_addr)
2190 iterator->level = 0;
2194 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2195 struct kvm_vcpu *vcpu, u64 addr)
2197 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2201 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2203 if (iterator->level < PG_LEVEL_4K)
2206 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2207 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2211 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2214 if (!is_shadow_present_pte(spte) || is_last_spte(spte, iterator->level)) {
2215 iterator->level = 0;
2219 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2223 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2225 __shadow_walk_next(iterator, *iterator->sptep);
2228 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2229 struct kvm_mmu_page *sp)
2233 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2235 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2237 mmu_spte_set(sptep, spte);
2239 mmu_page_add_parent_pte(vcpu, sp, sptep);
2241 if (sp->unsync_children || sp->unsync)
2245 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2246 unsigned direct_access)
2248 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2249 struct kvm_mmu_page *child;
2252 * For the direct sp, if the guest pte's dirty bit
2253 * changed form clean to dirty, it will corrupt the
2254 * sp's access: allow writable in the read-only sp,
2255 * so we should update the spte at this point to get
2256 * a new sp with the correct access.
2258 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2259 if (child->role.access == direct_access)
2262 drop_parent_pte(child, sptep);
2263 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2267 /* Returns the number of zapped non-leaf child shadow pages. */
2268 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2269 u64 *spte, struct list_head *invalid_list)
2272 struct kvm_mmu_page *child;
2275 if (is_shadow_present_pte(pte)) {
2276 if (is_last_spte(pte, sp->role.level)) {
2277 drop_spte(kvm, spte);
2279 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2280 drop_parent_pte(child, spte);
2283 * Recursively zap nested TDP SPs, parentless SPs are
2284 * unlikely to be used again in the near future. This
2285 * avoids retaining a large number of stale nested SPs.
2287 if (tdp_enabled && invalid_list &&
2288 child->role.guest_mode && !child->parent_ptes.val)
2289 return kvm_mmu_prepare_zap_page(kvm, child,
2292 } else if (is_mmio_spte(pte)) {
2293 mmu_spte_clear_no_track(spte);
2298 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2299 struct kvm_mmu_page *sp,
2300 struct list_head *invalid_list)
2305 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2306 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2311 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2314 struct rmap_iterator iter;
2316 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2317 drop_parent_pte(sp, sptep);
2320 static int mmu_zap_unsync_children(struct kvm *kvm,
2321 struct kvm_mmu_page *parent,
2322 struct list_head *invalid_list)
2325 struct mmu_page_path parents;
2326 struct kvm_mmu_pages pages;
2328 if (parent->role.level == PG_LEVEL_4K)
2331 while (mmu_unsync_walk(parent, &pages)) {
2332 struct kvm_mmu_page *sp;
2334 for_each_sp(pages, sp, parents, i) {
2335 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2336 mmu_pages_clear_parents(&parents);
2344 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2345 struct kvm_mmu_page *sp,
2346 struct list_head *invalid_list,
2351 trace_kvm_mmu_prepare_zap_page(sp);
2352 ++kvm->stat.mmu_shadow_zapped;
2353 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2354 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2355 kvm_mmu_unlink_parents(kvm, sp);
2357 /* Zapping children means active_mmu_pages has become unstable. */
2358 list_unstable = *nr_zapped;
2360 if (!sp->role.invalid && !sp->role.direct)
2361 unaccount_shadowed(kvm, sp);
2364 kvm_unlink_unsync_page(kvm, sp);
2365 if (!sp->root_count) {
2370 * Already invalid pages (previously active roots) are not on
2371 * the active page list. See list_del() in the "else" case of
2374 if (sp->role.invalid)
2375 list_add(&sp->link, invalid_list);
2377 list_move(&sp->link, invalid_list);
2378 kvm_mod_used_mmu_pages(kvm, -1);
2381 * Remove the active root from the active page list, the root
2382 * will be explicitly freed when the root_count hits zero.
2384 list_del(&sp->link);
2387 * Obsolete pages cannot be used on any vCPUs, see the comment
2388 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2389 * treats invalid shadow pages as being obsolete.
2391 if (!is_obsolete_sp(kvm, sp))
2392 kvm_reload_remote_mmus(kvm);
2395 if (sp->lpage_disallowed)
2396 unaccount_huge_nx_page(kvm, sp);
2398 sp->role.invalid = 1;
2399 return list_unstable;
2402 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2403 struct list_head *invalid_list)
2407 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2411 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2412 struct list_head *invalid_list)
2414 struct kvm_mmu_page *sp, *nsp;
2416 if (list_empty(invalid_list))
2420 * We need to make sure everyone sees our modifications to
2421 * the page tables and see changes to vcpu->mode here. The barrier
2422 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2423 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2425 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2426 * guest mode and/or lockless shadow page table walks.
2428 kvm_flush_remote_tlbs(kvm);
2430 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2431 WARN_ON(!sp->role.invalid || sp->root_count);
2432 kvm_mmu_free_page(sp);
2436 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2437 unsigned long nr_to_zap)
2439 unsigned long total_zapped = 0;
2440 struct kvm_mmu_page *sp, *tmp;
2441 LIST_HEAD(invalid_list);
2445 if (list_empty(&kvm->arch.active_mmu_pages))
2449 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2451 * Don't zap active root pages, the page itself can't be freed
2452 * and zapping it will just force vCPUs to realloc and reload.
2457 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2459 total_zapped += nr_zapped;
2460 if (total_zapped >= nr_to_zap)
2467 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2469 kvm->stat.mmu_recycled += total_zapped;
2470 return total_zapped;
2473 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2475 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2476 return kvm->arch.n_max_mmu_pages -
2477 kvm->arch.n_used_mmu_pages;
2482 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2484 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2486 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2489 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2492 * Note, this check is intentionally soft, it only guarantees that one
2493 * page is available, while the caller may end up allocating as many as
2494 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2495 * exceeding the (arbitrary by default) limit will not harm the host,
2496 * being too aggressive may unnecessarily kill the guest, and getting an
2497 * exact count is far more trouble than it's worth, especially in the
2500 if (!kvm_mmu_available_pages(vcpu->kvm))
2506 * Changing the number of mmu pages allocated to the vm
2507 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2509 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2511 write_lock(&kvm->mmu_lock);
2513 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2514 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2517 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2520 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2522 write_unlock(&kvm->mmu_lock);
2525 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2527 struct kvm_mmu_page *sp;
2528 LIST_HEAD(invalid_list);
2531 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2533 write_lock(&kvm->mmu_lock);
2534 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2535 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2538 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2540 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2541 write_unlock(&kvm->mmu_lock);
2546 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2551 if (vcpu->arch.mmu->direct_map)
2554 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2556 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2561 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2563 trace_kvm_mmu_unsync_page(sp);
2564 ++vcpu->kvm->stat.mmu_unsync;
2567 kvm_mmu_mark_parents_unsync(sp);
2571 * Attempt to unsync any shadow pages that can be reached by the specified gfn,
2572 * KVM is creating a writable mapping for said gfn. Returns 0 if all pages
2573 * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must
2574 * be write-protected.
2576 int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync,
2579 struct kvm_mmu_page *sp;
2580 bool locked = false;
2583 * Force write-protection if the page is being tracked. Note, the page
2584 * track machinery is used to write-protect upper-level shadow pages,
2585 * i.e. this guards the role.level == 4K assertion below!
2587 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2591 * The page is not write-tracked, mark existing shadow pages unsync
2592 * unless KVM is synchronizing an unsync SP (can_unsync = false). In
2593 * that case, KVM must complete emulation of the guest TLB flush before
2594 * allowing shadow pages to become unsync (writable by the guest).
2596 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2607 * TDP MMU page faults require an additional spinlock as they
2608 * run with mmu_lock held for read, not write, and the unsync
2609 * logic is not thread safe. Take the spinklock regardless of
2610 * the MMU type to avoid extra conditionals/parameters, there's
2611 * no meaningful penalty if mmu_lock is held for write.
2615 spin_lock(&vcpu->kvm->arch.mmu_unsync_pages_lock);
2618 * Recheck after taking the spinlock, a different vCPU
2619 * may have since marked the page unsync. A false
2620 * positive on the unprotected check above is not
2621 * possible as clearing sp->unsync _must_ hold mmu_lock
2622 * for write, i.e. unsync cannot transition from 0->1
2623 * while this CPU holds mmu_lock for read (or write).
2625 if (READ_ONCE(sp->unsync))
2629 WARN_ON(sp->role.level != PG_LEVEL_4K);
2630 kvm_unsync_page(vcpu, sp);
2633 spin_unlock(&vcpu->kvm->arch.mmu_unsync_pages_lock);
2636 * We need to ensure that the marking of unsync pages is visible
2637 * before the SPTE is updated to allow writes because
2638 * kvm_mmu_sync_roots() checks the unsync flags without holding
2639 * the MMU lock and so can race with this. If the SPTE was updated
2640 * before the page had been marked as unsync-ed, something like the
2641 * following could happen:
2644 * ---------------------------------------------------------------------
2645 * 1.2 Host updates SPTE
2647 * 2.1 Guest writes a GPTE for GVA X.
2648 * (GPTE being in the guest page table shadowed
2649 * by the SP from CPU 1.)
2650 * This reads SPTE during the page table walk.
2651 * Since SPTE.W is read as 1, there is no
2654 * 2.2 Guest issues TLB flush.
2655 * That causes a VM Exit.
2657 * 2.3 Walking of unsync pages sees sp->unsync is
2658 * false and skips the page.
2660 * 2.4 Guest accesses GVA X.
2661 * Since the mapping in the SP was not updated,
2662 * so the old mapping for GVA X incorrectly
2666 * (sp->unsync = true)
2668 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2669 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2670 * pairs with this write barrier.
2677 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2678 unsigned int pte_access, bool write_fault, int level,
2679 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2682 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
2683 int was_rmapped = 0;
2684 int ret = RET_PF_FIXED;
2689 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2690 *sptep, write_fault, gfn);
2692 if (unlikely(is_noslot_pfn(pfn))) {
2693 mark_mmio_spte(vcpu, sptep, gfn, pte_access);
2694 return RET_PF_EMULATE;
2697 if (is_shadow_present_pte(*sptep)) {
2699 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2700 * the parent of the now unreachable PTE.
2702 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2703 struct kvm_mmu_page *child;
2706 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2707 drop_parent_pte(child, sptep);
2709 } else if (pfn != spte_to_pfn(*sptep)) {
2710 pgprintk("hfn old %llx new %llx\n",
2711 spte_to_pfn(*sptep), pfn);
2712 drop_spte(vcpu->kvm, sptep);
2718 make_spte_ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2719 true, host_writable, sp_ad_disabled(sp), &spte);
2721 if (*sptep == spte) {
2722 ret = RET_PF_SPURIOUS;
2724 trace_kvm_mmu_set_spte(level, gfn, sptep);
2725 flush |= mmu_spte_update(sptep, spte);
2728 if (make_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2730 ret = RET_PF_EMULATE;
2734 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2735 KVM_PAGES_PER_HPAGE(level));
2737 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2740 WARN_ON_ONCE(ret == RET_PF_SPURIOUS);
2741 kvm_update_page_stats(vcpu->kvm, level, 1);
2742 rmap_add(vcpu, sptep, gfn);
2748 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2751 struct kvm_memory_slot *slot;
2753 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2755 return KVM_PFN_ERR_FAULT;
2757 return gfn_to_pfn_memslot_atomic(slot, gfn);
2760 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2761 struct kvm_mmu_page *sp,
2762 u64 *start, u64 *end)
2764 struct page *pages[PTE_PREFETCH_NUM];
2765 struct kvm_memory_slot *slot;
2766 unsigned int access = sp->role.access;
2770 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2771 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2775 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2779 for (i = 0; i < ret; i++, gfn++, start++) {
2780 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2781 page_to_pfn(pages[i]), true, true);
2788 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2789 struct kvm_mmu_page *sp, u64 *sptep)
2791 u64 *spte, *start = NULL;
2794 WARN_ON(!sp->role.direct);
2796 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2799 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2800 if (is_shadow_present_pte(*spte) || spte == sptep) {
2803 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2810 direct_pte_prefetch_many(vcpu, sp, start, spte);
2813 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2815 struct kvm_mmu_page *sp;
2817 sp = sptep_to_sp(sptep);
2820 * Without accessed bits, there's no way to distinguish between
2821 * actually accessed translations and prefetched, so disable pte
2822 * prefetch if accessed bits aren't available.
2824 if (sp_ad_disabled(sp))
2827 if (sp->role.level > PG_LEVEL_4K)
2831 * If addresses are being invalidated, skip prefetching to avoid
2832 * accidentally prefetching those addresses.
2834 if (unlikely(vcpu->kvm->mmu_notifier_count))
2837 __direct_pte_prefetch(vcpu, sp, sptep);
2840 static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
2841 const struct kvm_memory_slot *slot)
2847 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2851 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2852 * is not solely for performance, it's also necessary to avoid the
2853 * "writable" check in __gfn_to_hva_many(), which will always fail on
2854 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2855 * page fault steps have already verified the guest isn't writing a
2856 * read-only memslot.
2858 hva = __gfn_to_hva_memslot(slot, gfn);
2860 pte = lookup_address_in_mm(kvm->mm, hva, &level);
2867 int kvm_mmu_max_mapping_level(struct kvm *kvm,
2868 const struct kvm_memory_slot *slot, gfn_t gfn,
2869 kvm_pfn_t pfn, int max_level)
2871 struct kvm_lpage_info *linfo;
2874 max_level = min(max_level, max_huge_page_level);
2875 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2876 linfo = lpage_info_slot(gfn, slot, max_level);
2877 if (!linfo->disallow_lpage)
2881 if (max_level == PG_LEVEL_4K)
2884 host_level = host_pfn_mapping_level(kvm, gfn, pfn, slot);
2885 return min(host_level, max_level);
2888 void kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
2890 struct kvm_memory_slot *slot = fault->slot;
2893 fault->huge_page_disallowed = fault->exec && fault->nx_huge_page_workaround_enabled;
2895 if (unlikely(fault->max_level == PG_LEVEL_4K))
2898 if (is_error_noslot_pfn(fault->pfn) || kvm_is_reserved_pfn(fault->pfn))
2901 if (kvm_slot_dirty_track_enabled(slot))
2905 * Enforce the iTLB multihit workaround after capturing the requested
2906 * level, which will be used to do precise, accurate accounting.
2908 fault->req_level = kvm_mmu_max_mapping_level(vcpu->kvm, slot,
2909 fault->gfn, fault->pfn,
2911 if (fault->req_level == PG_LEVEL_4K || fault->huge_page_disallowed)
2915 * mmu_notifier_retry() was successful and mmu_lock is held, so
2916 * the pmd can't be split from under us.
2918 fault->goal_level = fault->req_level;
2919 mask = KVM_PAGES_PER_HPAGE(fault->goal_level) - 1;
2920 VM_BUG_ON((fault->gfn & mask) != (fault->pfn & mask));
2921 fault->pfn &= ~mask;
2924 void disallowed_hugepage_adjust(struct kvm_page_fault *fault, u64 spte, int cur_level)
2926 if (cur_level > PG_LEVEL_4K &&
2927 cur_level == fault->goal_level &&
2928 is_shadow_present_pte(spte) &&
2929 !is_large_pte(spte)) {
2931 * A small SPTE exists for this pfn, but FNAME(fetch)
2932 * and __direct_map would like to create a large PTE
2933 * instead: just force them to go down another level,
2934 * patching back for them into pfn the next 9 bits of
2937 u64 page_mask = KVM_PAGES_PER_HPAGE(cur_level) -
2938 KVM_PAGES_PER_HPAGE(cur_level - 1);
2939 fault->pfn |= fault->gfn & page_mask;
2940 fault->goal_level--;
2944 static int __direct_map(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
2946 struct kvm_shadow_walk_iterator it;
2947 struct kvm_mmu_page *sp;
2949 gfn_t base_gfn = fault->gfn;
2951 kvm_mmu_hugepage_adjust(vcpu, fault);
2953 trace_kvm_mmu_spte_requested(fault);
2954 for_each_shadow_entry(vcpu, fault->addr, it) {
2956 * We cannot overwrite existing page tables with an NX
2957 * large page, as the leaf could be executable.
2959 if (fault->nx_huge_page_workaround_enabled)
2960 disallowed_hugepage_adjust(fault, *it.sptep, it.level);
2962 base_gfn = fault->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2963 if (it.level == fault->goal_level)
2966 drop_large_spte(vcpu, it.sptep);
2967 if (is_shadow_present_pte(*it.sptep))
2970 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2971 it.level - 1, true, ACC_ALL);
2973 link_shadow_page(vcpu, it.sptep, sp);
2974 if (fault->is_tdp && fault->huge_page_disallowed &&
2975 fault->req_level >= it.level)
2976 account_huge_nx_page(vcpu->kvm, sp);
2979 if (WARN_ON_ONCE(it.level != fault->goal_level))
2982 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2983 fault->write, fault->goal_level, base_gfn, fault->pfn,
2984 fault->prefault, fault->map_writable);
2985 if (ret == RET_PF_SPURIOUS)
2988 direct_pte_prefetch(vcpu, it.sptep);
2989 ++vcpu->stat.pf_fixed;
2993 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2995 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2998 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
3001 * Do not cache the mmio info caused by writing the readonly gfn
3002 * into the spte otherwise read access on readonly gfn also can
3003 * caused mmio page fault and treat it as mmio access.
3005 if (pfn == KVM_PFN_ERR_RO_FAULT)
3006 return RET_PF_EMULATE;
3008 if (pfn == KVM_PFN_ERR_HWPOISON) {
3009 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3010 return RET_PF_RETRY;
3016 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault,
3017 unsigned int access, int *ret_val)
3019 /* The pfn is invalid, report the error! */
3020 if (unlikely(is_error_pfn(fault->pfn))) {
3021 *ret_val = kvm_handle_bad_page(vcpu, fault->gfn, fault->pfn);
3025 if (unlikely(!fault->slot)) {
3026 gva_t gva = fault->is_tdp ? 0 : fault->addr;
3028 vcpu_cache_mmio_info(vcpu, gva, fault->gfn,
3029 access & shadow_mmio_access_mask);
3031 * If MMIO caching is disabled, emulate immediately without
3032 * touching the shadow page tables as attempting to install an
3033 * MMIO SPTE will just be an expensive nop.
3035 if (unlikely(!shadow_mmio_value)) {
3036 *ret_val = RET_PF_EMULATE;
3044 static bool page_fault_can_be_fast(struct kvm_page_fault *fault)
3047 * Do not fix the mmio spte with invalid generation number which
3048 * need to be updated by slow page fault path.
3053 /* See if the page fault is due to an NX violation */
3054 if (unlikely(fault->exec && fault->present))
3058 * #PF can be fast if:
3059 * 1. The shadow page table entry is not present, which could mean that
3060 * the fault is potentially caused by access tracking (if enabled).
3061 * 2. The shadow page table entry is present and the fault
3062 * is caused by write-protect, that means we just need change the W
3063 * bit of the spte which can be done out of mmu-lock.
3065 * However, if access tracking is disabled we know that a non-present
3066 * page must be a genuine page fault where we have to create a new SPTE.
3067 * So, if access tracking is disabled, we return true only for write
3068 * accesses to a present page.
3071 return shadow_acc_track_mask != 0 || (fault->write && fault->present);
3075 * Returns true if the SPTE was fixed successfully. Otherwise,
3076 * someone else modified the SPTE from its original value.
3079 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault,
3080 u64 *sptep, u64 old_spte, u64 new_spte)
3083 * Theoretically we could also set dirty bit (and flush TLB) here in
3084 * order to eliminate unnecessary PML logging. See comments in
3085 * set_spte. But fast_page_fault is very unlikely to happen with PML
3086 * enabled, so we do not do this. This might result in the same GPA
3087 * to be logged in PML buffer again when the write really happens, and
3088 * eventually to be called by mark_page_dirty twice. But it's also no
3089 * harm. This also avoids the TLB flush needed after setting dirty bit
3090 * so non-PML cases won't be impacted.
3092 * Compare with set_spte where instead shadow_dirty_mask is set.
3094 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3097 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte))
3098 mark_page_dirty_in_slot(vcpu->kvm, fault->slot, fault->gfn);
3103 static bool is_access_allowed(struct kvm_page_fault *fault, u64 spte)
3106 return is_executable_pte(spte);
3109 return is_writable_pte(spte);
3111 /* Fault was on Read access */
3112 return spte & PT_PRESENT_MASK;
3116 * Returns the last level spte pointer of the shadow page walk for the given
3117 * gpa, and sets *spte to the spte value. This spte may be non-preset. If no
3118 * walk could be performed, returns NULL and *spte does not contain valid data.
3121 * - Must be called between walk_shadow_page_lockless_{begin,end}.
3122 * - The returned sptep must not be used after walk_shadow_page_lockless_end.
3124 static u64 *fast_pf_get_last_sptep(struct kvm_vcpu *vcpu, gpa_t gpa, u64 *spte)
3126 struct kvm_shadow_walk_iterator iterator;
3130 for_each_shadow_entry_lockless(vcpu, gpa, iterator, old_spte) {
3131 sptep = iterator.sptep;
3139 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3141 static int fast_page_fault(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
3143 struct kvm_mmu_page *sp;
3144 int ret = RET_PF_INVALID;
3147 uint retry_count = 0;
3149 if (!page_fault_can_be_fast(fault))
3152 walk_shadow_page_lockless_begin(vcpu);
3157 if (is_tdp_mmu(vcpu->arch.mmu))
3158 sptep = kvm_tdp_mmu_fast_pf_get_last_sptep(vcpu, fault->addr, &spte);
3160 sptep = fast_pf_get_last_sptep(vcpu, fault->addr, &spte);
3162 if (!is_shadow_present_pte(spte))
3165 sp = sptep_to_sp(sptep);
3166 if (!is_last_spte(spte, sp->role.level))
3170 * Check whether the memory access that caused the fault would
3171 * still cause it if it were to be performed right now. If not,
3172 * then this is a spurious fault caused by TLB lazily flushed,
3173 * or some other CPU has already fixed the PTE after the
3174 * current CPU took the fault.
3176 * Need not check the access of upper level table entries since
3177 * they are always ACC_ALL.
3179 if (is_access_allowed(fault, spte)) {
3180 ret = RET_PF_SPURIOUS;
3186 if (is_access_track_spte(spte))
3187 new_spte = restore_acc_track_spte(new_spte);
3190 * Currently, to simplify the code, write-protection can
3191 * be removed in the fast path only if the SPTE was
3192 * write-protected for dirty-logging or access tracking.
3195 spte_can_locklessly_be_made_writable(spte)) {
3196 new_spte |= PT_WRITABLE_MASK;
3199 * Do not fix write-permission on the large spte. Since
3200 * we only dirty the first page into the dirty-bitmap in
3201 * fast_pf_fix_direct_spte(), other pages are missed
3202 * if its slot has dirty logging enabled.
3204 * Instead, we let the slow page fault path create a
3205 * normal spte to fix the access.
3207 * See the comments in kvm_arch_commit_memory_region().
3209 if (sp->role.level > PG_LEVEL_4K)
3213 /* Verify that the fault can be handled in the fast path */
3214 if (new_spte == spte ||
3215 !is_access_allowed(fault, new_spte))
3219 * Currently, fast page fault only works for direct mapping
3220 * since the gfn is not stable for indirect shadow page. See
3221 * Documentation/virt/kvm/locking.rst to get more detail.
3223 if (fast_pf_fix_direct_spte(vcpu, fault, sptep, spte, new_spte)) {
3228 if (++retry_count > 4) {
3229 printk_once(KERN_WARNING
3230 "kvm: Fast #PF retrying more than 4 times.\n");
3236 trace_fast_page_fault(vcpu, fault, sptep, spte, ret);
3237 walk_shadow_page_lockless_end(vcpu);
3242 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3243 struct list_head *invalid_list)
3245 struct kvm_mmu_page *sp;
3247 if (!VALID_PAGE(*root_hpa))
3250 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3252 if (is_tdp_mmu_page(sp))
3253 kvm_tdp_mmu_put_root(kvm, sp, false);
3254 else if (!--sp->root_count && sp->role.invalid)
3255 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3257 *root_hpa = INVALID_PAGE;
3260 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3261 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3262 ulong roots_to_free)
3264 struct kvm *kvm = vcpu->kvm;
3266 LIST_HEAD(invalid_list);
3267 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3269 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3271 /* Before acquiring the MMU lock, see if we need to do any real work. */
3272 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3273 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3274 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3275 VALID_PAGE(mmu->prev_roots[i].hpa))
3278 if (i == KVM_MMU_NUM_PREV_ROOTS)
3282 write_lock(&kvm->mmu_lock);
3284 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3285 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3286 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3289 if (free_active_root) {
3290 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3291 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3292 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3293 } else if (mmu->pae_root) {
3294 for (i = 0; i < 4; ++i) {
3295 if (!IS_VALID_PAE_ROOT(mmu->pae_root[i]))
3298 mmu_free_root_page(kvm, &mmu->pae_root[i],
3300 mmu->pae_root[i] = INVALID_PAE_ROOT;
3303 mmu->root_hpa = INVALID_PAGE;
3307 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3308 write_unlock(&kvm->mmu_lock);
3310 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3312 void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3314 unsigned long roots_to_free = 0;
3319 * This should not be called while L2 is active, L2 can't invalidate
3320 * _only_ its own roots, e.g. INVVPID unconditionally exits.
3322 WARN_ON_ONCE(mmu->mmu_role.base.guest_mode);
3324 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3325 root_hpa = mmu->prev_roots[i].hpa;
3326 if (!VALID_PAGE(root_hpa))
3329 if (!to_shadow_page(root_hpa) ||
3330 to_shadow_page(root_hpa)->role.guest_mode)
3331 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
3334 kvm_mmu_free_roots(vcpu, mmu, roots_to_free);
3336 EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots);
3339 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3343 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3344 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3351 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3352 u8 level, bool direct)
3354 struct kvm_mmu_page *sp;
3356 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3359 return __pa(sp->spt);
3362 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3364 struct kvm_mmu *mmu = vcpu->arch.mmu;
3365 u8 shadow_root_level = mmu->shadow_root_level;
3370 write_lock(&vcpu->kvm->mmu_lock);
3371 r = make_mmu_pages_available(vcpu);
3375 if (is_tdp_mmu_enabled(vcpu->kvm)) {
3376 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3377 mmu->root_hpa = root;
3378 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3379 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
3380 mmu->root_hpa = root;
3381 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3382 if (WARN_ON_ONCE(!mmu->pae_root)) {
3387 for (i = 0; i < 4; ++i) {
3388 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3390 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3391 i << 30, PT32_ROOT_LEVEL, true);
3392 mmu->pae_root[i] = root | PT_PRESENT_MASK |
3395 mmu->root_hpa = __pa(mmu->pae_root);
3397 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level);
3402 /* root_pgd is ignored for direct MMUs. */
3405 write_unlock(&vcpu->kvm->mmu_lock);
3409 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3411 struct kvm_mmu *mmu = vcpu->arch.mmu;
3412 u64 pdptrs[4], pm_mask;
3413 gfn_t root_gfn, root_pgd;
3418 root_pgd = mmu->get_guest_pgd(vcpu);
3419 root_gfn = root_pgd >> PAGE_SHIFT;
3421 if (mmu_check_root(vcpu, root_gfn))
3425 * On SVM, reading PDPTRs might access guest memory, which might fault
3426 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3428 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3429 for (i = 0; i < 4; ++i) {
3430 pdptrs[i] = mmu->get_pdptr(vcpu, i);
3431 if (!(pdptrs[i] & PT_PRESENT_MASK))
3434 if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT))
3439 r = alloc_all_memslots_rmaps(vcpu->kvm);
3443 write_lock(&vcpu->kvm->mmu_lock);
3444 r = make_mmu_pages_available(vcpu);
3449 * Do we shadow a long mode page table? If so we need to
3450 * write-protect the guests page table root.
3452 if (mmu->root_level >= PT64_ROOT_4LEVEL) {
3453 root = mmu_alloc_root(vcpu, root_gfn, 0,
3454 mmu->shadow_root_level, false);
3455 mmu->root_hpa = root;
3459 if (WARN_ON_ONCE(!mmu->pae_root)) {
3465 * We shadow a 32 bit page table. This may be a legacy 2-level
3466 * or a PAE 3-level page table. In either case we need to be aware that
3467 * the shadow page table may be a PAE or a long mode page table.
3469 pm_mask = PT_PRESENT_MASK | shadow_me_mask;
3470 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3471 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3473 if (WARN_ON_ONCE(!mmu->pml4_root)) {
3477 mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask;
3479 if (mmu->shadow_root_level == PT64_ROOT_5LEVEL) {
3480 if (WARN_ON_ONCE(!mmu->pml5_root)) {
3484 mmu->pml5_root[0] = __pa(mmu->pml4_root) | pm_mask;
3488 for (i = 0; i < 4; ++i) {
3489 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3491 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3492 if (!(pdptrs[i] & PT_PRESENT_MASK)) {
3493 mmu->pae_root[i] = INVALID_PAE_ROOT;
3496 root_gfn = pdptrs[i] >> PAGE_SHIFT;
3499 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3500 PT32_ROOT_LEVEL, false);
3501 mmu->pae_root[i] = root | pm_mask;
3504 if (mmu->shadow_root_level == PT64_ROOT_5LEVEL)
3505 mmu->root_hpa = __pa(mmu->pml5_root);
3506 else if (mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3507 mmu->root_hpa = __pa(mmu->pml4_root);
3509 mmu->root_hpa = __pa(mmu->pae_root);
3512 mmu->root_pgd = root_pgd;
3514 write_unlock(&vcpu->kvm->mmu_lock);
3519 static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu)
3521 struct kvm_mmu *mmu = vcpu->arch.mmu;
3522 bool need_pml5 = mmu->shadow_root_level > PT64_ROOT_4LEVEL;
3523 u64 *pml5_root = NULL;
3524 u64 *pml4_root = NULL;
3528 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3529 * tables are allocated and initialized at root creation as there is no
3530 * equivalent level in the guest's NPT to shadow. Allocate the tables
3531 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3533 if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL ||
3534 mmu->shadow_root_level < PT64_ROOT_4LEVEL)
3538 * NPT, the only paging mode that uses this horror, uses a fixed number
3539 * of levels for the shadow page tables, e.g. all MMUs are 4-level or
3540 * all MMus are 5-level. Thus, this can safely require that pml5_root
3541 * is allocated if the other roots are valid and pml5 is needed, as any
3542 * prior MMU would also have required pml5.
3544 if (mmu->pae_root && mmu->pml4_root && (!need_pml5 || mmu->pml5_root))
3548 * The special roots should always be allocated in concert. Yell and
3549 * bail if KVM ends up in a state where only one of the roots is valid.
3551 if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root ||
3552 (need_pml5 && mmu->pml5_root)))
3556 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3557 * doesn't need to be decrypted.
3559 pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3563 #ifdef CONFIG_X86_64
3564 pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3569 pml5_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3575 mmu->pae_root = pae_root;
3576 mmu->pml4_root = pml4_root;
3577 mmu->pml5_root = pml5_root;
3581 #ifdef CONFIG_X86_64
3583 free_page((unsigned long)pml4_root);
3585 free_page((unsigned long)pae_root);
3590 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3593 struct kvm_mmu_page *sp;
3595 if (vcpu->arch.mmu->direct_map)
3598 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3601 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3603 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3604 hpa_t root = vcpu->arch.mmu->root_hpa;
3605 sp = to_shadow_page(root);
3608 * Even if another CPU was marking the SP as unsync-ed
3609 * simultaneously, any guest page table changes are not
3610 * guaranteed to be visible anyway until this VCPU issues a TLB
3611 * flush strictly after those changes are made. We only need to
3612 * ensure that the other CPU sets these flags before any actual
3613 * changes to the page tables are made. The comments in
3614 * mmu_try_to_unsync_pages() describe what could go wrong if
3615 * this requirement isn't satisfied.
3617 if (!smp_load_acquire(&sp->unsync) &&
3618 !smp_load_acquire(&sp->unsync_children))
3621 write_lock(&vcpu->kvm->mmu_lock);
3622 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3624 mmu_sync_children(vcpu, sp, true);
3626 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3627 write_unlock(&vcpu->kvm->mmu_lock);
3631 write_lock(&vcpu->kvm->mmu_lock);
3632 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3634 for (i = 0; i < 4; ++i) {
3635 hpa_t root = vcpu->arch.mmu->pae_root[i];
3637 if (IS_VALID_PAE_ROOT(root)) {
3638 root &= PT64_BASE_ADDR_MASK;
3639 sp = to_shadow_page(root);
3640 mmu_sync_children(vcpu, sp, true);
3644 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3645 write_unlock(&vcpu->kvm->mmu_lock);
3648 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3649 u32 access, struct x86_exception *exception)
3652 exception->error_code = 0;
3656 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3658 struct x86_exception *exception)
3661 exception->error_code = 0;
3662 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3665 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3668 * A nested guest cannot use the MMIO cache if it is using nested
3669 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3671 if (mmu_is_nested(vcpu))
3675 return vcpu_match_mmio_gpa(vcpu, addr);
3677 return vcpu_match_mmio_gva(vcpu, addr);
3681 * Return the level of the lowest level SPTE added to sptes.
3682 * That SPTE may be non-present.
3684 * Must be called between walk_shadow_page_lockless_{begin,end}.
3686 static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
3688 struct kvm_shadow_walk_iterator iterator;
3692 for (shadow_walk_init(&iterator, vcpu, addr),
3693 *root_level = iterator.level;
3694 shadow_walk_okay(&iterator);
3695 __shadow_walk_next(&iterator, spte)) {
3696 leaf = iterator.level;
3697 spte = mmu_spte_get_lockless(iterator.sptep);
3705 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3706 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3708 u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
3709 struct rsvd_bits_validate *rsvd_check;
3710 int root, leaf, level;
3711 bool reserved = false;
3713 walk_shadow_page_lockless_begin(vcpu);
3715 if (is_tdp_mmu(vcpu->arch.mmu))
3716 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
3718 leaf = get_walk(vcpu, addr, sptes, &root);
3720 walk_shadow_page_lockless_end(vcpu);
3722 if (unlikely(leaf < 0)) {
3727 *sptep = sptes[leaf];
3730 * Skip reserved bits checks on the terminal leaf if it's not a valid
3731 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3732 * design, always have reserved bits set. The purpose of the checks is
3733 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3735 if (!is_shadow_present_pte(sptes[leaf]))
3738 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3740 for (level = root; level >= leaf; level--)
3741 reserved |= is_rsvd_spte(rsvd_check, sptes[level], level);
3744 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3746 for (level = root; level >= leaf; level--)
3747 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3748 sptes[level], level,
3749 get_rsvd_bits(rsvd_check, sptes[level], level));
3755 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3760 if (mmio_info_in_cache(vcpu, addr, direct))
3761 return RET_PF_EMULATE;
3763 reserved = get_mmio_spte(vcpu, addr, &spte);
3764 if (WARN_ON(reserved))
3767 if (is_mmio_spte(spte)) {
3768 gfn_t gfn = get_mmio_spte_gfn(spte);
3769 unsigned int access = get_mmio_spte_access(spte);
3771 if (!check_mmio_spte(vcpu, spte))
3772 return RET_PF_INVALID;
3777 trace_handle_mmio_page_fault(addr, gfn, access);
3778 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3779 return RET_PF_EMULATE;
3783 * If the page table is zapped by other cpus, let CPU fault again on
3786 return RET_PF_RETRY;
3789 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3790 struct kvm_page_fault *fault)
3792 if (unlikely(fault->rsvd))
3795 if (!fault->present || !fault->write)
3799 * guest is writing the page which is write tracked which can
3800 * not be fixed by page fault handler.
3802 if (kvm_slot_page_track_is_active(fault->slot, fault->gfn, KVM_PAGE_TRACK_WRITE))
3808 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3810 struct kvm_shadow_walk_iterator iterator;
3813 walk_shadow_page_lockless_begin(vcpu);
3814 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3815 clear_sp_write_flooding_count(iterator.sptep);
3816 walk_shadow_page_lockless_end(vcpu);
3819 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3822 struct kvm_arch_async_pf arch;
3824 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3826 arch.direct_map = vcpu->arch.mmu->direct_map;
3827 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3829 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3830 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3833 static bool kvm_faultin_pfn(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault, int *r)
3835 struct kvm_memory_slot *slot = fault->slot;
3839 * Retry the page fault if the gfn hit a memslot that is being deleted
3840 * or moved. This ensures any existing SPTEs for the old memslot will
3841 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3843 if (slot && (slot->flags & KVM_MEMSLOT_INVALID))
3846 if (!kvm_is_visible_memslot(slot)) {
3847 /* Don't expose private memslots to L2. */
3848 if (is_guest_mode(vcpu)) {
3850 fault->pfn = KVM_PFN_NOSLOT;
3851 fault->map_writable = false;
3855 * If the APIC access page exists but is disabled, go directly
3856 * to emulation without caching the MMIO access or creating a
3857 * MMIO SPTE. That way the cache doesn't need to be purged
3858 * when the AVIC is re-enabled.
3860 if (slot && slot->id == APIC_ACCESS_PAGE_PRIVATE_MEMSLOT &&
3861 !kvm_apicv_activated(vcpu->kvm)) {
3862 *r = RET_PF_EMULATE;
3868 fault->pfn = __gfn_to_pfn_memslot(slot, fault->gfn, false, &async,
3869 fault->write, &fault->map_writable,
3872 return false; /* *pfn has correct page already */
3874 if (!fault->prefault && kvm_can_do_async_pf(vcpu)) {
3875 trace_kvm_try_async_get_page(fault->addr, fault->gfn);
3876 if (kvm_find_async_pf_gfn(vcpu, fault->gfn)) {
3877 trace_kvm_async_pf_doublefault(fault->addr, fault->gfn);
3878 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3880 } else if (kvm_arch_setup_async_pf(vcpu, fault->addr, fault->gfn))
3884 fault->pfn = __gfn_to_pfn_memslot(slot, fault->gfn, false, NULL,
3885 fault->write, &fault->map_writable,
3893 static int direct_page_fault(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
3895 bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu);
3897 unsigned long mmu_seq;
3900 fault->gfn = fault->addr >> PAGE_SHIFT;
3901 fault->slot = kvm_vcpu_gfn_to_memslot(vcpu, fault->gfn);
3903 if (page_fault_handle_page_track(vcpu, fault))
3904 return RET_PF_EMULATE;
3906 r = fast_page_fault(vcpu, fault);
3907 if (r != RET_PF_INVALID)
3910 r = mmu_topup_memory_caches(vcpu, false);
3914 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3917 if (kvm_faultin_pfn(vcpu, fault, &r))
3920 if (handle_abnormal_pfn(vcpu, fault, ACC_ALL, &r))
3925 if (is_tdp_mmu_fault)
3926 read_lock(&vcpu->kvm->mmu_lock);
3928 write_lock(&vcpu->kvm->mmu_lock);
3930 if (fault->slot && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, fault->hva))
3932 r = make_mmu_pages_available(vcpu);
3936 if (is_tdp_mmu_fault)
3937 r = kvm_tdp_mmu_map(vcpu, fault);
3939 r = __direct_map(vcpu, fault);
3942 if (is_tdp_mmu_fault)
3943 read_unlock(&vcpu->kvm->mmu_lock);
3945 write_unlock(&vcpu->kvm->mmu_lock);
3946 kvm_release_pfn_clean(fault->pfn);
3950 static int nonpaging_page_fault(struct kvm_vcpu *vcpu,
3951 struct kvm_page_fault *fault)
3953 pgprintk("%s: gva %lx error %x\n", __func__, fault->addr, fault->error_code);
3955 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3956 fault->max_level = PG_LEVEL_2M;
3957 return direct_page_fault(vcpu, fault);
3960 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3961 u64 fault_address, char *insn, int insn_len)
3964 u32 flags = vcpu->arch.apf.host_apf_flags;
3966 #ifndef CONFIG_X86_64
3967 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3968 if (WARN_ON_ONCE(fault_address >> 32))
3972 vcpu->arch.l1tf_flush_l1d = true;
3974 trace_kvm_page_fault(fault_address, error_code);
3976 if (kvm_event_needs_reinjection(vcpu))
3977 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3978 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3980 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3981 vcpu->arch.apf.host_apf_flags = 0;
3982 local_irq_disable();
3983 kvm_async_pf_task_wait_schedule(fault_address);
3986 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3991 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3993 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault)
3995 while (fault->max_level > PG_LEVEL_4K) {
3996 int page_num = KVM_PAGES_PER_HPAGE(fault->max_level);
3997 gfn_t base = (fault->addr >> PAGE_SHIFT) & ~(page_num - 1);
3999 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
4005 return direct_page_fault(vcpu, fault);
4008 static void nonpaging_init_context(struct kvm_mmu *context)
4010 context->page_fault = nonpaging_page_fault;
4011 context->gva_to_gpa = nonpaging_gva_to_gpa;
4012 context->sync_page = nonpaging_sync_page;
4013 context->invlpg = NULL;
4014 context->direct_map = true;
4017 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
4018 union kvm_mmu_page_role role)
4020 return (role.direct || pgd == root->pgd) &&
4021 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
4022 role.word == to_shadow_page(root->hpa)->role.word;
4026 * Find out if a previously cached root matching the new pgd/role is available.
4027 * The current root is also inserted into the cache.
4028 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4030 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4031 * false is returned. This root should now be freed by the caller.
4033 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4034 union kvm_mmu_page_role new_role)
4037 struct kvm_mmu_root_info root;
4038 struct kvm_mmu *mmu = vcpu->arch.mmu;
4040 root.pgd = mmu->root_pgd;
4041 root.hpa = mmu->root_hpa;
4043 if (is_root_usable(&root, new_pgd, new_role))
4046 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4047 swap(root, mmu->prev_roots[i]);
4049 if (is_root_usable(&root, new_pgd, new_role))
4053 mmu->root_hpa = root.hpa;
4054 mmu->root_pgd = root.pgd;
4056 return i < KVM_MMU_NUM_PREV_ROOTS;
4059 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4060 union kvm_mmu_page_role new_role)
4062 struct kvm_mmu *mmu = vcpu->arch.mmu;
4065 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4066 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4067 * later if necessary.
4069 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4070 mmu->root_level >= PT64_ROOT_4LEVEL)
4071 return cached_root_available(vcpu, new_pgd, new_role);
4076 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4077 union kvm_mmu_page_role new_role)
4079 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
4080 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
4085 * It's possible that the cached previous root page is obsolete because
4086 * of a change in the MMU generation number. However, changing the
4087 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
4088 * free the root set here and allocate a new one.
4090 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
4092 if (force_flush_and_sync_on_reuse) {
4093 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4094 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
4098 * The last MMIO access's GVA and GPA are cached in the VCPU. When
4099 * switching to a new CR3, that GVA->GPA mapping may no longer be
4100 * valid. So clear any cached MMIO info even when we don't need to sync
4101 * the shadow page tables.
4103 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4106 * If this is a direct root page, it doesn't have a write flooding
4107 * count. Otherwise, clear the write flooding count.
4109 if (!new_role.direct)
4110 __clear_sp_write_flooding_count(
4111 to_shadow_page(vcpu->arch.mmu->root_hpa));
4114 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd)
4116 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu));
4118 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
4120 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4122 return kvm_read_cr3(vcpu);
4125 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4126 unsigned int access)
4128 if (unlikely(is_mmio_spte(*sptep))) {
4129 if (gfn != get_mmio_spte_gfn(*sptep)) {
4130 mmu_spte_clear_no_track(sptep);
4134 mark_mmio_spte(vcpu, sptep, gfn, access);
4141 #define PTTYPE_EPT 18 /* arbitrary */
4142 #define PTTYPE PTTYPE_EPT
4143 #include "paging_tmpl.h"
4147 #include "paging_tmpl.h"
4151 #include "paging_tmpl.h"
4155 __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check,
4156 u64 pa_bits_rsvd, int level, bool nx, bool gbpages,
4159 u64 gbpages_bit_rsvd = 0;
4160 u64 nonleaf_bit8_rsvd = 0;
4163 rsvd_check->bad_mt_xwr = 0;
4166 gbpages_bit_rsvd = rsvd_bits(7, 7);
4168 if (level == PT32E_ROOT_LEVEL)
4169 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62);
4171 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4173 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4175 high_bits_rsvd |= rsvd_bits(63, 63);
4178 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4179 * leaf entries) on AMD CPUs only.
4182 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4185 case PT32_ROOT_LEVEL:
4186 /* no rsvd bits for 2 level 4K page table entries */
4187 rsvd_check->rsvd_bits_mask[0][1] = 0;
4188 rsvd_check->rsvd_bits_mask[0][0] = 0;
4189 rsvd_check->rsvd_bits_mask[1][0] =
4190 rsvd_check->rsvd_bits_mask[0][0];
4193 rsvd_check->rsvd_bits_mask[1][1] = 0;
4197 if (is_cpuid_PSE36())
4198 /* 36bits PSE 4MB page */
4199 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4201 /* 32 bits PSE 4MB page */
4202 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4204 case PT32E_ROOT_LEVEL:
4205 rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
4208 rsvd_bits(1, 2); /* PDPTE */
4209 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
4210 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
4211 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4212 rsvd_bits(13, 20); /* large page */
4213 rsvd_check->rsvd_bits_mask[1][0] =
4214 rsvd_check->rsvd_bits_mask[0][0];
4216 case PT64_ROOT_5LEVEL:
4217 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
4220 rsvd_check->rsvd_bits_mask[1][4] =
4221 rsvd_check->rsvd_bits_mask[0][4];
4223 case PT64_ROOT_4LEVEL:
4224 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
4227 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
4229 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
4230 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4231 rsvd_check->rsvd_bits_mask[1][3] =
4232 rsvd_check->rsvd_bits_mask[0][3];
4233 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
4236 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4237 rsvd_bits(13, 20); /* large page */
4238 rsvd_check->rsvd_bits_mask[1][0] =
4239 rsvd_check->rsvd_bits_mask[0][0];
4244 static bool guest_can_use_gbpages(struct kvm_vcpu *vcpu)
4247 * If TDP is enabled, let the guest use GBPAGES if they're supported in
4248 * hardware. The hardware page walker doesn't let KVM disable GBPAGES,
4249 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA
4250 * walk for performance and complexity reasons. Not to mention KVM
4251 * _can't_ solve the problem because GVA->GPA walks aren't visible to
4252 * KVM once a TDP translation is installed. Mimic hardware behavior so
4253 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF.
4255 return tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) :
4256 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES);
4259 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4260 struct kvm_mmu *context)
4262 __reset_rsvds_bits_mask(&context->guest_rsvd_check,
4263 vcpu->arch.reserved_gpa_bits,
4264 context->root_level, is_efer_nx(context),
4265 guest_can_use_gbpages(vcpu),
4266 is_cr4_pse(context),
4267 guest_cpuid_is_amd_or_hygon(vcpu));
4271 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4272 u64 pa_bits_rsvd, bool execonly)
4274 u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4277 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
4278 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
4279 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6);
4280 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6);
4281 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4284 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4285 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4286 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29);
4287 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20);
4288 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4290 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4291 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4292 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4293 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4294 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4296 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4297 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4299 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4302 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4303 struct kvm_mmu *context, bool execonly)
4305 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4306 vcpu->arch.reserved_gpa_bits, execonly);
4309 static inline u64 reserved_hpa_bits(void)
4311 return rsvd_bits(shadow_phys_bits, 63);
4315 * the page table on host is the shadow page table for the page
4316 * table in guest or amd nested guest, its mmu features completely
4317 * follow the features in guest.
4319 static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4320 struct kvm_mmu *context)
4323 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4324 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4325 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4326 * The iTLB multi-hit workaround can be toggled at any time, so assume
4327 * NX can be used by any non-nested shadow MMU to avoid having to reset
4328 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4330 bool uses_nx = is_efer_nx(context) || !tdp_enabled;
4332 /* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */
4334 /* KVM doesn't use 2-level page tables for the shadow MMU. */
4335 bool is_pse = false;
4336 struct rsvd_bits_validate *shadow_zero_check;
4339 WARN_ON_ONCE(context->shadow_root_level < PT32E_ROOT_LEVEL);
4341 shadow_zero_check = &context->shadow_zero_check;
4342 __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
4343 context->shadow_root_level, uses_nx,
4344 guest_can_use_gbpages(vcpu), is_pse, is_amd);
4346 if (!shadow_me_mask)
4349 for (i = context->shadow_root_level; --i >= 0;) {
4350 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4351 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4356 static inline bool boot_cpu_is_amd(void)
4358 WARN_ON_ONCE(!tdp_enabled);
4359 return shadow_x_mask == 0;
4363 * the direct page table on host, use as much mmu features as
4364 * possible, however, kvm currently does not do execution-protection.
4367 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4368 struct kvm_mmu *context)
4370 struct rsvd_bits_validate *shadow_zero_check;
4373 shadow_zero_check = &context->shadow_zero_check;
4375 if (boot_cpu_is_amd())
4376 __reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
4377 context->shadow_root_level, false,
4378 boot_cpu_has(X86_FEATURE_GBPAGES),
4381 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4382 reserved_hpa_bits(), false);
4384 if (!shadow_me_mask)
4387 for (i = context->shadow_root_level; --i >= 0;) {
4388 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4389 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4394 * as the comments in reset_shadow_zero_bits_mask() except it
4395 * is the shadow page table for intel nested guest.
4398 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4399 struct kvm_mmu *context, bool execonly)
4401 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4402 reserved_hpa_bits(), execonly);
4405 #define BYTE_MASK(access) \
4406 ((1 & (access) ? 2 : 0) | \
4407 (2 & (access) ? 4 : 0) | \
4408 (3 & (access) ? 8 : 0) | \
4409 (4 & (access) ? 16 : 0) | \
4410 (5 & (access) ? 32 : 0) | \
4411 (6 & (access) ? 64 : 0) | \
4412 (7 & (access) ? 128 : 0))
4415 static void update_permission_bitmask(struct kvm_mmu *mmu, bool ept)
4419 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4420 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4421 const u8 u = BYTE_MASK(ACC_USER_MASK);
4423 bool cr4_smep = is_cr4_smep(mmu);
4424 bool cr4_smap = is_cr4_smap(mmu);
4425 bool cr0_wp = is_cr0_wp(mmu);
4426 bool efer_nx = is_efer_nx(mmu);
4428 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4429 unsigned pfec = byte << 1;
4432 * Each "*f" variable has a 1 bit for each UWX value
4433 * that causes a fault with the given PFEC.
4436 /* Faults from writes to non-writable pages */
4437 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4438 /* Faults from user mode accesses to supervisor pages */
4439 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4440 /* Faults from fetches of non-executable pages*/
4441 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4442 /* Faults from kernel mode fetches of user pages */
4444 /* Faults from kernel mode accesses of user pages */
4448 /* Faults from kernel mode accesses to user pages */
4449 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4451 /* Not really needed: !nx will cause pte.nx to fault */
4455 /* Allow supervisor writes if !cr0.wp */
4457 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4459 /* Disallow supervisor fetches of user code if cr4.smep */
4461 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4464 * SMAP:kernel-mode data accesses from user-mode
4465 * mappings should fault. A fault is considered
4466 * as a SMAP violation if all of the following
4467 * conditions are true:
4468 * - X86_CR4_SMAP is set in CR4
4469 * - A user page is accessed
4470 * - The access is not a fetch
4471 * - Page fault in kernel mode
4472 * - if CPL = 3 or X86_EFLAGS_AC is clear
4474 * Here, we cover the first three conditions.
4475 * The fourth is computed dynamically in permission_fault();
4476 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4477 * *not* subject to SMAP restrictions.
4480 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4483 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4488 * PKU is an additional mechanism by which the paging controls access to
4489 * user-mode addresses based on the value in the PKRU register. Protection
4490 * key violations are reported through a bit in the page fault error code.
4491 * Unlike other bits of the error code, the PK bit is not known at the
4492 * call site of e.g. gva_to_gpa; it must be computed directly in
4493 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4494 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4496 * In particular the following conditions come from the error code, the
4497 * page tables and the machine state:
4498 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4499 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4500 * - PK is always zero if U=0 in the page tables
4501 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4503 * The PKRU bitmask caches the result of these four conditions. The error
4504 * code (minus the P bit) and the page table's U bit form an index into the
4505 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4506 * with the two bits of the PKRU register corresponding to the protection key.
4507 * For the first three conditions above the bits will be 00, thus masking
4508 * away both AD and WD. For all reads or if the last condition holds, WD
4509 * only will be masked away.
4511 static void update_pkru_bitmask(struct kvm_mmu *mmu)
4516 if (!is_cr4_pke(mmu)) {
4521 wp = is_cr0_wp(mmu);
4523 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4524 unsigned pfec, pkey_bits;
4525 bool check_pkey, check_write, ff, uf, wf, pte_user;
4528 ff = pfec & PFERR_FETCH_MASK;
4529 uf = pfec & PFERR_USER_MASK;
4530 wf = pfec & PFERR_WRITE_MASK;
4532 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4533 pte_user = pfec & PFERR_RSVD_MASK;
4536 * Only need to check the access which is not an
4537 * instruction fetch and is to a user page.
4539 check_pkey = (!ff && pte_user);
4541 * write access is controlled by PKRU if it is a
4542 * user access or CR0.WP = 1.
4544 check_write = check_pkey && wf && (uf || wp);
4546 /* PKRU.AD stops both read and write access. */
4547 pkey_bits = !!check_pkey;
4548 /* PKRU.WD stops write access. */
4549 pkey_bits |= (!!check_write) << 1;
4551 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4555 static void reset_guest_paging_metadata(struct kvm_vcpu *vcpu,
4556 struct kvm_mmu *mmu)
4558 if (!is_cr0_pg(mmu))
4561 reset_rsvds_bits_mask(vcpu, mmu);
4562 update_permission_bitmask(mmu, false);
4563 update_pkru_bitmask(mmu);
4566 static void paging64_init_context(struct kvm_mmu *context)
4568 context->page_fault = paging64_page_fault;
4569 context->gva_to_gpa = paging64_gva_to_gpa;
4570 context->sync_page = paging64_sync_page;
4571 context->invlpg = paging64_invlpg;
4572 context->direct_map = false;
4575 static void paging32_init_context(struct kvm_mmu *context)
4577 context->page_fault = paging32_page_fault;
4578 context->gva_to_gpa = paging32_gva_to_gpa;
4579 context->sync_page = paging32_sync_page;
4580 context->invlpg = paging32_invlpg;
4581 context->direct_map = false;
4584 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu,
4585 struct kvm_mmu_role_regs *regs)
4587 union kvm_mmu_extended_role ext = {0};
4589 if (____is_cr0_pg(regs)) {
4591 ext.cr4_pae = ____is_cr4_pae(regs);
4592 ext.cr4_smep = ____is_cr4_smep(regs);
4593 ext.cr4_smap = ____is_cr4_smap(regs);
4594 ext.cr4_pse = ____is_cr4_pse(regs);
4596 /* PKEY and LA57 are active iff long mode is active. */
4597 ext.cr4_pke = ____is_efer_lma(regs) && ____is_cr4_pke(regs);
4598 ext.cr4_la57 = ____is_efer_lma(regs) && ____is_cr4_la57(regs);
4606 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4607 struct kvm_mmu_role_regs *regs,
4610 union kvm_mmu_role role = {0};
4612 role.base.access = ACC_ALL;
4613 if (____is_cr0_pg(regs)) {
4614 role.base.efer_nx = ____is_efer_nx(regs);
4615 role.base.cr0_wp = ____is_cr0_wp(regs);
4617 role.base.smm = is_smm(vcpu);
4618 role.base.guest_mode = is_guest_mode(vcpu);
4623 role.ext = kvm_calc_mmu_role_ext(vcpu, regs);
4628 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4630 /* tdp_root_level is architecture forced level, use it if nonzero */
4632 return tdp_root_level;
4634 /* Use 5-level TDP if and only if it's useful/necessary. */
4635 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4638 return max_tdp_level;
4641 static union kvm_mmu_role
4642 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu,
4643 struct kvm_mmu_role_regs *regs, bool base_only)
4645 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
4647 role.base.ad_disabled = (shadow_accessed_mask == 0);
4648 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4649 role.base.direct = true;
4650 role.base.gpte_is_8_bytes = true;
4655 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4657 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4658 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4659 union kvm_mmu_role new_role =
4660 kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, false);
4662 if (new_role.as_u64 == context->mmu_role.as_u64)
4665 context->mmu_role.as_u64 = new_role.as_u64;
4666 context->page_fault = kvm_tdp_page_fault;
4667 context->sync_page = nonpaging_sync_page;
4668 context->invlpg = NULL;
4669 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4670 context->direct_map = true;
4671 context->get_guest_pgd = get_cr3;
4672 context->get_pdptr = kvm_pdptr_read;
4673 context->inject_page_fault = kvm_inject_page_fault;
4674 context->root_level = role_regs_to_root_level(®s);
4676 if (!is_cr0_pg(context))
4677 context->gva_to_gpa = nonpaging_gva_to_gpa;
4678 else if (is_cr4_pae(context))
4679 context->gva_to_gpa = paging64_gva_to_gpa;
4681 context->gva_to_gpa = paging32_gva_to_gpa;
4683 reset_guest_paging_metadata(vcpu, context);
4684 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4687 static union kvm_mmu_role
4688 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu,
4689 struct kvm_mmu_role_regs *regs, bool base_only)
4691 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs, base_only);
4693 role.base.smep_andnot_wp = role.ext.cr4_smep && !____is_cr0_wp(regs);
4694 role.base.smap_andnot_wp = role.ext.cr4_smap && !____is_cr0_wp(regs);
4695 role.base.gpte_is_8_bytes = ____is_cr0_pg(regs) && ____is_cr4_pae(regs);
4700 static union kvm_mmu_role
4701 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu,
4702 struct kvm_mmu_role_regs *regs, bool base_only)
4704 union kvm_mmu_role role =
4705 kvm_calc_shadow_root_page_role_common(vcpu, regs, base_only);
4707 role.base.direct = !____is_cr0_pg(regs);
4709 if (!____is_efer_lma(regs))
4710 role.base.level = PT32E_ROOT_LEVEL;
4711 else if (____is_cr4_la57(regs))
4712 role.base.level = PT64_ROOT_5LEVEL;
4714 role.base.level = PT64_ROOT_4LEVEL;
4719 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4720 struct kvm_mmu_role_regs *regs,
4721 union kvm_mmu_role new_role)
4723 if (new_role.as_u64 == context->mmu_role.as_u64)
4726 context->mmu_role.as_u64 = new_role.as_u64;
4728 if (!is_cr0_pg(context))
4729 nonpaging_init_context(context);
4730 else if (is_cr4_pae(context))
4731 paging64_init_context(context);
4733 paging32_init_context(context);
4734 context->root_level = role_regs_to_root_level(regs);
4736 reset_guest_paging_metadata(vcpu, context);
4737 context->shadow_root_level = new_role.base.level;
4739 reset_shadow_zero_bits_mask(vcpu, context);
4742 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu,
4743 struct kvm_mmu_role_regs *regs)
4745 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4746 union kvm_mmu_role new_role =
4747 kvm_calc_shadow_mmu_root_page_role(vcpu, regs, false);
4749 shadow_mmu_init_context(vcpu, context, regs, new_role);
4752 static union kvm_mmu_role
4753 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu,
4754 struct kvm_mmu_role_regs *regs)
4756 union kvm_mmu_role role =
4757 kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
4759 role.base.direct = false;
4760 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4765 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
4766 unsigned long cr4, u64 efer, gpa_t nested_cr3)
4768 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4769 struct kvm_mmu_role_regs regs = {
4774 union kvm_mmu_role new_role;
4776 new_role = kvm_calc_shadow_npt_root_page_role(vcpu, ®s);
4778 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base);
4780 shadow_mmu_init_context(vcpu, context, ®s, new_role);
4782 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4784 static union kvm_mmu_role
4785 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4786 bool execonly, u8 level)
4788 union kvm_mmu_role role = {0};
4790 /* SMM flag is inherited from root_mmu */
4791 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4793 role.base.level = level;
4794 role.base.gpte_is_8_bytes = true;
4795 role.base.direct = false;
4796 role.base.ad_disabled = !accessed_dirty;
4797 role.base.guest_mode = true;
4798 role.base.access = ACC_ALL;
4800 /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */
4802 role.ext.execonly = execonly;
4808 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4809 bool accessed_dirty, gpa_t new_eptp)
4811 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4812 u8 level = vmx_eptp_page_walk_level(new_eptp);
4813 union kvm_mmu_role new_role =
4814 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4817 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base);
4819 if (new_role.as_u64 == context->mmu_role.as_u64)
4822 context->mmu_role.as_u64 = new_role.as_u64;
4824 context->shadow_root_level = level;
4826 context->ept_ad = accessed_dirty;
4827 context->page_fault = ept_page_fault;
4828 context->gva_to_gpa = ept_gva_to_gpa;
4829 context->sync_page = ept_sync_page;
4830 context->invlpg = ept_invlpg;
4831 context->root_level = level;
4832 context->direct_map = false;
4834 update_permission_bitmask(context, true);
4835 update_pkru_bitmask(context);
4836 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4837 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4839 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4841 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4843 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4844 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4846 kvm_init_shadow_mmu(vcpu, ®s);
4848 context->get_guest_pgd = get_cr3;
4849 context->get_pdptr = kvm_pdptr_read;
4850 context->inject_page_fault = kvm_inject_page_fault;
4853 static union kvm_mmu_role
4854 kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu, struct kvm_mmu_role_regs *regs)
4856 union kvm_mmu_role role;
4858 role = kvm_calc_shadow_root_page_role_common(vcpu, regs, false);
4861 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4862 * shadow pages of their own and so "direct" has no meaning. Set it
4863 * to "true" to try to detect bogus usage of the nested MMU.
4865 role.base.direct = true;
4866 role.base.level = role_regs_to_root_level(regs);
4870 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4872 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4873 union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu, ®s);
4874 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4876 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4879 g_context->mmu_role.as_u64 = new_role.as_u64;
4880 g_context->get_guest_pgd = get_cr3;
4881 g_context->get_pdptr = kvm_pdptr_read;
4882 g_context->inject_page_fault = kvm_inject_page_fault;
4883 g_context->root_level = new_role.base.level;
4886 * L2 page tables are never shadowed, so there is no need to sync
4889 g_context->invlpg = NULL;
4892 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4893 * L1's nested page tables (e.g. EPT12). The nested translation
4894 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4895 * L2's page tables as the first level of translation and L1's
4896 * nested page tables as the second level of translation. Basically
4897 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4899 if (!is_paging(vcpu))
4900 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4901 else if (is_long_mode(vcpu))
4902 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4903 else if (is_pae(vcpu))
4904 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4906 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4908 reset_guest_paging_metadata(vcpu, g_context);
4911 void kvm_init_mmu(struct kvm_vcpu *vcpu)
4913 if (mmu_is_nested(vcpu))
4914 init_kvm_nested_mmu(vcpu);
4915 else if (tdp_enabled)
4916 init_kvm_tdp_mmu(vcpu);
4918 init_kvm_softmmu(vcpu);
4920 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4922 static union kvm_mmu_page_role
4923 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4925 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4926 union kvm_mmu_role role;
4929 role = kvm_calc_tdp_mmu_root_page_role(vcpu, ®s, true);
4931 role = kvm_calc_shadow_mmu_root_page_role(vcpu, ®s, true);
4936 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu)
4939 * Invalidate all MMU roles to force them to reinitialize as CPUID
4940 * information is factored into reserved bit calculations.
4942 vcpu->arch.root_mmu.mmu_role.ext.valid = 0;
4943 vcpu->arch.guest_mmu.mmu_role.ext.valid = 0;
4944 vcpu->arch.nested_mmu.mmu_role.ext.valid = 0;
4945 kvm_mmu_reset_context(vcpu);
4948 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
4949 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
4950 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
4951 * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise
4952 * sweep the problem under the rug.
4954 * KVM's horrific CPUID ABI makes the problem all but impossible to
4955 * solve, as correctly handling multiple vCPU models (with respect to
4956 * paging and physical address properties) in a single VM would require
4957 * tracking all relevant CPUID information in kvm_mmu_page_role. That
4958 * is very undesirable as it would double the memory requirements for
4959 * gfn_track (see struct kvm_mmu_page_role comments), and in practice
4960 * no sane VMM mucks with the core vCPU model on the fly.
4962 if (vcpu->arch.last_vmentry_cpu != -1) {
4963 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n");
4964 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n");
4968 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4970 kvm_mmu_unload(vcpu);
4973 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4975 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4979 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
4982 r = mmu_alloc_special_roots(vcpu);
4985 if (vcpu->arch.mmu->direct_map)
4986 r = mmu_alloc_direct_roots(vcpu);
4988 r = mmu_alloc_shadow_roots(vcpu);
4992 kvm_mmu_sync_roots(vcpu);
4994 kvm_mmu_load_pgd(vcpu);
4995 static_call(kvm_x86_tlb_flush_current)(vcpu);
5000 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
5002 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
5003 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
5004 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
5005 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
5008 static bool need_remote_flush(u64 old, u64 new)
5010 if (!is_shadow_present_pte(old))
5012 if (!is_shadow_present_pte(new))
5014 if ((old ^ new) & PT64_BASE_ADDR_MASK)
5016 old ^= shadow_nx_mask;
5017 new ^= shadow_nx_mask;
5018 return (old & ~new & PT64_PERM_MASK) != 0;
5021 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5028 * Assume that the pte write on a page table of the same type
5029 * as the current vcpu paging mode since we update the sptes only
5030 * when they have the same mode.
5032 if (is_pae(vcpu) && *bytes == 4) {
5033 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5038 if (*bytes == 4 || *bytes == 8) {
5039 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5048 * If we're seeing too many writes to a page, it may no longer be a page table,
5049 * or we may be forking, in which case it is better to unmap the page.
5051 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5054 * Skip write-flooding detected for the sp whose level is 1, because
5055 * it can become unsync, then the guest page is not write-protected.
5057 if (sp->role.level == PG_LEVEL_4K)
5060 atomic_inc(&sp->write_flooding_count);
5061 return atomic_read(&sp->write_flooding_count) >= 3;
5065 * Misaligned accesses are too much trouble to fix up; also, they usually
5066 * indicate a page is not used as a page table.
5068 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5071 unsigned offset, pte_size, misaligned;
5073 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5074 gpa, bytes, sp->role.word);
5076 offset = offset_in_page(gpa);
5077 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5080 * Sometimes, the OS only writes the last one bytes to update status
5081 * bits, for example, in linux, andb instruction is used in clear_bit().
5083 if (!(offset & (pte_size - 1)) && bytes == 1)
5086 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5087 misaligned |= bytes < 4;
5092 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5094 unsigned page_offset, quadrant;
5098 page_offset = offset_in_page(gpa);
5099 level = sp->role.level;
5101 if (!sp->role.gpte_is_8_bytes) {
5102 page_offset <<= 1; /* 32->64 */
5104 * A 32-bit pde maps 4MB while the shadow pdes map
5105 * only 2MB. So we need to double the offset again
5106 * and zap two pdes instead of one.
5108 if (level == PT32_ROOT_LEVEL) {
5109 page_offset &= ~7; /* kill rounding error */
5113 quadrant = page_offset >> PAGE_SHIFT;
5114 page_offset &= ~PAGE_MASK;
5115 if (quadrant != sp->role.quadrant)
5119 spte = &sp->spt[page_offset / sizeof(*spte)];
5123 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5124 const u8 *new, int bytes,
5125 struct kvm_page_track_notifier_node *node)
5127 gfn_t gfn = gpa >> PAGE_SHIFT;
5128 struct kvm_mmu_page *sp;
5129 LIST_HEAD(invalid_list);
5130 u64 entry, gentry, *spte;
5135 * If we don't have indirect shadow pages, it means no page is
5136 * write-protected, so we can exit simply.
5138 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5141 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5144 * No need to care whether allocation memory is successful
5145 * or not since pte prefetch is skipped if it does not have
5146 * enough objects in the cache.
5148 mmu_topup_memory_caches(vcpu, true);
5150 write_lock(&vcpu->kvm->mmu_lock);
5152 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5154 ++vcpu->kvm->stat.mmu_pte_write;
5155 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5157 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5158 if (detect_write_misaligned(sp, gpa, bytes) ||
5159 detect_write_flooding(sp)) {
5160 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5161 ++vcpu->kvm->stat.mmu_flooded;
5165 spte = get_written_sptes(sp, gpa, &npte);
5171 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
5172 if (gentry && sp->role.level != PG_LEVEL_4K)
5173 ++vcpu->kvm->stat.mmu_pde_zapped;
5174 if (need_remote_flush(entry, *spte))
5179 kvm_mmu_remote_flush_or_zap(vcpu->kvm, &invalid_list, flush);
5180 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5181 write_unlock(&vcpu->kvm->mmu_lock);
5184 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5185 void *insn, int insn_len)
5187 int r, emulation_type = EMULTYPE_PF;
5188 bool direct = vcpu->arch.mmu->direct_map;
5190 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5191 return RET_PF_RETRY;
5194 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5195 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5196 if (r == RET_PF_EMULATE)
5200 if (r == RET_PF_INVALID) {
5201 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5202 lower_32_bits(error_code), false);
5203 if (KVM_BUG_ON(r == RET_PF_INVALID, vcpu->kvm))
5209 if (r != RET_PF_EMULATE)
5213 * Before emulating the instruction, check if the error code
5214 * was due to a RO violation while translating the guest page.
5215 * This can occur when using nested virtualization with nested
5216 * paging in both guests. If true, we simply unprotect the page
5217 * and resume the guest.
5219 if (vcpu->arch.mmu->direct_map &&
5220 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5221 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5226 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5227 * optimistically try to just unprotect the page and let the processor
5228 * re-execute the instruction that caused the page fault. Do not allow
5229 * retrying MMIO emulation, as it's not only pointless but could also
5230 * cause us to enter an infinite loop because the processor will keep
5231 * faulting on the non-existent MMIO address. Retrying an instruction
5232 * from a nested guest is also pointless and dangerous as we are only
5233 * explicitly shadowing L1's page tables, i.e. unprotecting something
5234 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5236 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5237 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5239 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5242 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5244 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5245 gva_t gva, hpa_t root_hpa)
5249 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5250 if (mmu != &vcpu->arch.guest_mmu) {
5251 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5252 if (is_noncanonical_address(gva, vcpu))
5255 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5261 if (root_hpa == INVALID_PAGE) {
5262 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5265 * INVLPG is required to invalidate any global mappings for the VA,
5266 * irrespective of PCID. Since it would take us roughly similar amount
5267 * of work to determine whether any of the prev_root mappings of the VA
5268 * is marked global, or to just sync it blindly, so we might as well
5269 * just always sync it.
5271 * Mappings not reachable via the current cr3 or the prev_roots will be
5272 * synced when switching to that cr3, so nothing needs to be done here
5275 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5276 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5277 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5279 mmu->invlpg(vcpu, gva, root_hpa);
5283 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5285 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5286 ++vcpu->stat.invlpg;
5288 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5291 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5293 struct kvm_mmu *mmu = vcpu->arch.mmu;
5294 bool tlb_flush = false;
5297 if (pcid == kvm_get_active_pcid(vcpu)) {
5298 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5302 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5303 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5304 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5305 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5311 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5313 ++vcpu->stat.invlpg;
5316 * Mappings not reachable via the current cr3 or the prev_roots will be
5317 * synced when switching to that cr3, so nothing needs to be done here
5322 void kvm_configure_mmu(bool enable_tdp, int tdp_forced_root_level,
5323 int tdp_max_root_level, int tdp_huge_page_level)
5325 tdp_enabled = enable_tdp;
5326 tdp_root_level = tdp_forced_root_level;
5327 max_tdp_level = tdp_max_root_level;
5330 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5331 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5332 * the kernel is not. But, KVM never creates a page size greater than
5333 * what is used by the kernel for any given HVA, i.e. the kernel's
5334 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5337 max_huge_page_level = tdp_huge_page_level;
5338 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5339 max_huge_page_level = PG_LEVEL_1G;
5341 max_huge_page_level = PG_LEVEL_2M;
5343 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5345 /* The return value indicates if tlb flush on all vcpus is needed. */
5346 typedef bool (*slot_level_handler) (struct kvm *kvm,
5347 struct kvm_rmap_head *rmap_head,
5348 const struct kvm_memory_slot *slot);
5350 /* The caller should hold mmu-lock before calling this function. */
5351 static __always_inline bool
5352 slot_handle_level_range(struct kvm *kvm, const struct kvm_memory_slot *memslot,
5353 slot_level_handler fn, int start_level, int end_level,
5354 gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield,
5357 struct slot_rmap_walk_iterator iterator;
5359 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5360 end_gfn, &iterator) {
5362 flush |= fn(kvm, iterator.rmap, memslot);
5364 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5365 if (flush && flush_on_yield) {
5366 kvm_flush_remote_tlbs_with_address(kvm,
5368 iterator.gfn - start_gfn + 1);
5371 cond_resched_rwlock_write(&kvm->mmu_lock);
5378 static __always_inline bool
5379 slot_handle_level(struct kvm *kvm, const struct kvm_memory_slot *memslot,
5380 slot_level_handler fn, int start_level, int end_level,
5381 bool flush_on_yield)
5383 return slot_handle_level_range(kvm, memslot, fn, start_level,
5384 end_level, memslot->base_gfn,
5385 memslot->base_gfn + memslot->npages - 1,
5386 flush_on_yield, false);
5389 static __always_inline bool
5390 slot_handle_leaf(struct kvm *kvm, const struct kvm_memory_slot *memslot,
5391 slot_level_handler fn, bool flush_on_yield)
5393 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5394 PG_LEVEL_4K, flush_on_yield);
5397 static void free_mmu_pages(struct kvm_mmu *mmu)
5399 if (!tdp_enabled && mmu->pae_root)
5400 set_memory_encrypted((unsigned long)mmu->pae_root, 1);
5401 free_page((unsigned long)mmu->pae_root);
5402 free_page((unsigned long)mmu->pml4_root);
5403 free_page((unsigned long)mmu->pml5_root);
5406 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5411 mmu->root_hpa = INVALID_PAGE;
5413 mmu->translate_gpa = translate_gpa;
5414 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5415 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5418 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5419 * while the PDP table is a per-vCPU construct that's allocated at MMU
5420 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5421 * x86_64. Therefore we need to allocate the PDP table in the first
5422 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5423 * generally doesn't use PAE paging and can skip allocating the PDP
5424 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5425 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5426 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5428 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5431 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5435 mmu->pae_root = page_address(page);
5438 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5439 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5440 * that KVM's writes and the CPU's reads get along. Note, this is
5441 * only necessary when using shadow paging, as 64-bit NPT can get at
5442 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5443 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5446 set_memory_decrypted((unsigned long)mmu->pae_root, 1);
5448 WARN_ON_ONCE(shadow_me_mask);
5450 for (i = 0; i < 4; ++i)
5451 mmu->pae_root[i] = INVALID_PAE_ROOT;
5456 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5460 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5461 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5463 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5464 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5466 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5468 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5469 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5471 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5473 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5477 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5479 goto fail_allocate_root;
5483 free_mmu_pages(&vcpu->arch.guest_mmu);
5487 #define BATCH_ZAP_PAGES 10
5488 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5490 struct kvm_mmu_page *sp, *node;
5491 int nr_zapped, batch = 0;
5494 list_for_each_entry_safe_reverse(sp, node,
5495 &kvm->arch.active_mmu_pages, link) {
5497 * No obsolete valid page exists before a newly created page
5498 * since active_mmu_pages is a FIFO list.
5500 if (!is_obsolete_sp(kvm, sp))
5504 * Invalid pages should never land back on the list of active
5505 * pages. Skip the bogus page, otherwise we'll get stuck in an
5506 * infinite loop if the page gets put back on the list (again).
5508 if (WARN_ON(sp->role.invalid))
5512 * No need to flush the TLB since we're only zapping shadow
5513 * pages with an obsolete generation number and all vCPUS have
5514 * loaded a new root, i.e. the shadow pages being zapped cannot
5515 * be in active use by the guest.
5517 if (batch >= BATCH_ZAP_PAGES &&
5518 cond_resched_rwlock_write(&kvm->mmu_lock)) {
5523 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5524 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5531 * Trigger a remote TLB flush before freeing the page tables to ensure
5532 * KVM is not in the middle of a lockless shadow page table walk, which
5533 * may reference the pages.
5535 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5539 * Fast invalidate all shadow pages and use lock-break technique
5540 * to zap obsolete pages.
5542 * It's required when memslot is being deleted or VM is being
5543 * destroyed, in these cases, we should ensure that KVM MMU does
5544 * not use any resource of the being-deleted slot or all slots
5545 * after calling the function.
5547 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5549 lockdep_assert_held(&kvm->slots_lock);
5551 write_lock(&kvm->mmu_lock);
5552 trace_kvm_mmu_zap_all_fast(kvm);
5555 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5556 * held for the entire duration of zapping obsolete pages, it's
5557 * impossible for there to be multiple invalid generations associated
5558 * with *valid* shadow pages at any given time, i.e. there is exactly
5559 * one valid generation and (at most) one invalid generation.
5561 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5563 /* In order to ensure all threads see this change when
5564 * handling the MMU reload signal, this must happen in the
5565 * same critical section as kvm_reload_remote_mmus, and
5566 * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages
5567 * could drop the MMU lock and yield.
5569 if (is_tdp_mmu_enabled(kvm))
5570 kvm_tdp_mmu_invalidate_all_roots(kvm);
5573 * Notify all vcpus to reload its shadow page table and flush TLB.
5574 * Then all vcpus will switch to new shadow page table with the new
5577 * Note: we need to do this under the protection of mmu_lock,
5578 * otherwise, vcpu would purge shadow page but miss tlb flush.
5580 kvm_reload_remote_mmus(kvm);
5582 kvm_zap_obsolete_pages(kvm);
5584 write_unlock(&kvm->mmu_lock);
5586 if (is_tdp_mmu_enabled(kvm)) {
5587 read_lock(&kvm->mmu_lock);
5588 kvm_tdp_mmu_zap_invalidated_roots(kvm);
5589 read_unlock(&kvm->mmu_lock);
5593 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5595 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5598 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5599 struct kvm_memory_slot *slot,
5600 struct kvm_page_track_notifier_node *node)
5602 kvm_mmu_zap_all_fast(kvm);
5605 void kvm_mmu_init_vm(struct kvm *kvm)
5607 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5609 spin_lock_init(&kvm->arch.mmu_unsync_pages_lock);
5611 if (!kvm_mmu_init_tdp_mmu(kvm))
5613 * No smp_load/store wrappers needed here as we are in
5614 * VM init and there cannot be any memslots / other threads
5615 * accessing this struct kvm yet.
5617 kvm->arch.memslots_have_rmaps = true;
5619 node->track_write = kvm_mmu_pte_write;
5620 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5621 kvm_page_track_register_notifier(kvm, node);
5624 void kvm_mmu_uninit_vm(struct kvm *kvm)
5626 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5628 kvm_page_track_unregister_notifier(kvm, node);
5630 kvm_mmu_uninit_tdp_mmu(kvm);
5634 * Invalidate (zap) SPTEs that cover GFNs from gfn_start and up to gfn_end
5635 * (not including it)
5637 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5639 struct kvm_memslots *slots;
5640 struct kvm_memory_slot *memslot;
5644 write_lock(&kvm->mmu_lock);
5646 kvm_inc_notifier_count(kvm, gfn_start, gfn_end);
5648 if (kvm_memslots_have_rmaps(kvm)) {
5649 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5650 slots = __kvm_memslots(kvm, i);
5651 kvm_for_each_memslot(memslot, slots) {
5654 start = max(gfn_start, memslot->base_gfn);
5655 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5659 flush = slot_handle_level_range(kvm,
5660 (const struct kvm_memory_slot *) memslot,
5661 kvm_zap_rmapp, PG_LEVEL_4K,
5662 KVM_MAX_HUGEPAGE_LEVEL, start,
5663 end - 1, true, flush);
5667 kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
5668 gfn_end - gfn_start);
5671 if (is_tdp_mmu_enabled(kvm)) {
5672 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++)
5673 flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start,
5676 kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
5677 gfn_end - gfn_start);
5681 kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end);
5683 kvm_dec_notifier_count(kvm, gfn_start, gfn_end);
5685 write_unlock(&kvm->mmu_lock);
5688 static bool slot_rmap_write_protect(struct kvm *kvm,
5689 struct kvm_rmap_head *rmap_head,
5690 const struct kvm_memory_slot *slot)
5692 return __rmap_write_protect(kvm, rmap_head, false);
5695 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5696 const struct kvm_memory_slot *memslot,
5701 if (kvm_memslots_have_rmaps(kvm)) {
5702 write_lock(&kvm->mmu_lock);
5703 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5704 start_level, KVM_MAX_HUGEPAGE_LEVEL,
5706 write_unlock(&kvm->mmu_lock);
5709 if (is_tdp_mmu_enabled(kvm)) {
5710 read_lock(&kvm->mmu_lock);
5711 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level);
5712 read_unlock(&kvm->mmu_lock);
5716 * We can flush all the TLBs out of the mmu lock without TLB
5717 * corruption since we just change the spte from writable to
5718 * readonly so that we only need to care the case of changing
5719 * spte from present to present (changing the spte from present
5720 * to nonpresent will flush all the TLBs immediately), in other
5721 * words, the only case we care is mmu_spte_update() where we
5722 * have checked Host-writable | MMU-writable instead of
5723 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5727 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5730 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5731 struct kvm_rmap_head *rmap_head,
5732 const struct kvm_memory_slot *slot)
5735 struct rmap_iterator iter;
5736 int need_tlb_flush = 0;
5738 struct kvm_mmu_page *sp;
5741 for_each_rmap_spte(rmap_head, &iter, sptep) {
5742 sp = sptep_to_sp(sptep);
5743 pfn = spte_to_pfn(*sptep);
5746 * We cannot do huge page mapping for indirect shadow pages,
5747 * which are found on the last rmap (level = 1) when not using
5748 * tdp; such shadow pages are synced with the page table in
5749 * the guest, and the guest page table is using 4K page size
5750 * mapping if the indirect sp has level = 1.
5752 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5753 sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
5754 pfn, PG_LEVEL_NUM)) {
5755 pte_list_remove(kvm, rmap_head, sptep);
5757 if (kvm_available_flush_tlb_with_range())
5758 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5759 KVM_PAGES_PER_HPAGE(sp->role.level));
5767 return need_tlb_flush;
5770 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5771 const struct kvm_memory_slot *slot)
5775 if (kvm_memslots_have_rmaps(kvm)) {
5776 write_lock(&kvm->mmu_lock);
5777 flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true);
5779 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5780 write_unlock(&kvm->mmu_lock);
5783 if (is_tdp_mmu_enabled(kvm)) {
5784 read_lock(&kvm->mmu_lock);
5785 flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush);
5787 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5788 read_unlock(&kvm->mmu_lock);
5792 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5793 const struct kvm_memory_slot *memslot)
5796 * All current use cases for flushing the TLBs for a specific memslot
5797 * related to dirty logging, and many do the TLB flush out of mmu_lock.
5798 * The interaction between the various operations on memslot must be
5799 * serialized by slots_locks to ensure the TLB flush from one operation
5800 * is observed by any other operation on the same memslot.
5802 lockdep_assert_held(&kvm->slots_lock);
5803 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5807 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5808 const struct kvm_memory_slot *memslot)
5812 if (kvm_memslots_have_rmaps(kvm)) {
5813 write_lock(&kvm->mmu_lock);
5814 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty,
5816 write_unlock(&kvm->mmu_lock);
5819 if (is_tdp_mmu_enabled(kvm)) {
5820 read_lock(&kvm->mmu_lock);
5821 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5822 read_unlock(&kvm->mmu_lock);
5826 * It's also safe to flush TLBs out of mmu lock here as currently this
5827 * function is only used for dirty logging, in which case flushing TLB
5828 * out of mmu lock also guarantees no dirty pages will be lost in
5832 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5835 void kvm_mmu_zap_all(struct kvm *kvm)
5837 struct kvm_mmu_page *sp, *node;
5838 LIST_HEAD(invalid_list);
5841 write_lock(&kvm->mmu_lock);
5843 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5844 if (WARN_ON(sp->role.invalid))
5846 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5848 if (cond_resched_rwlock_write(&kvm->mmu_lock))
5852 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5854 if (is_tdp_mmu_enabled(kvm))
5855 kvm_tdp_mmu_zap_all(kvm);
5857 write_unlock(&kvm->mmu_lock);
5860 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5862 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5864 gen &= MMIO_SPTE_GEN_MASK;
5867 * Generation numbers are incremented in multiples of the number of
5868 * address spaces in order to provide unique generations across all
5869 * address spaces. Strip what is effectively the address space
5870 * modifier prior to checking for a wrap of the MMIO generation so
5871 * that a wrap in any address space is detected.
5873 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5876 * The very rare case: if the MMIO generation number has wrapped,
5877 * zap all shadow pages.
5879 if (unlikely(gen == 0)) {
5880 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5881 kvm_mmu_zap_all_fast(kvm);
5885 static unsigned long
5886 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5889 int nr_to_scan = sc->nr_to_scan;
5890 unsigned long freed = 0;
5892 mutex_lock(&kvm_lock);
5894 list_for_each_entry(kvm, &vm_list, vm_list) {
5896 LIST_HEAD(invalid_list);
5899 * Never scan more than sc->nr_to_scan VM instances.
5900 * Will not hit this condition practically since we do not try
5901 * to shrink more than one VM and it is very unlikely to see
5902 * !n_used_mmu_pages so many times.
5907 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5908 * here. We may skip a VM instance errorneosly, but we do not
5909 * want to shrink a VM that only started to populate its MMU
5912 if (!kvm->arch.n_used_mmu_pages &&
5913 !kvm_has_zapped_obsolete_pages(kvm))
5916 idx = srcu_read_lock(&kvm->srcu);
5917 write_lock(&kvm->mmu_lock);
5919 if (kvm_has_zapped_obsolete_pages(kvm)) {
5920 kvm_mmu_commit_zap_page(kvm,
5921 &kvm->arch.zapped_obsolete_pages);
5925 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5928 write_unlock(&kvm->mmu_lock);
5929 srcu_read_unlock(&kvm->srcu, idx);
5932 * unfair on small ones
5933 * per-vm shrinkers cry out
5934 * sadness comes quickly
5936 list_move_tail(&kvm->vm_list, &vm_list);
5940 mutex_unlock(&kvm_lock);
5944 static unsigned long
5945 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5947 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5950 static struct shrinker mmu_shrinker = {
5951 .count_objects = mmu_shrink_count,
5952 .scan_objects = mmu_shrink_scan,
5953 .seeks = DEFAULT_SEEKS * 10,
5956 static void mmu_destroy_caches(void)
5958 kmem_cache_destroy(pte_list_desc_cache);
5959 kmem_cache_destroy(mmu_page_header_cache);
5962 static bool get_nx_auto_mode(void)
5964 /* Return true when CPU has the bug, and mitigations are ON */
5965 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5968 static void __set_nx_huge_pages(bool val)
5970 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5973 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5975 bool old_val = nx_huge_pages;
5978 /* In "auto" mode deploy workaround only if CPU has the bug. */
5979 if (sysfs_streq(val, "off"))
5981 else if (sysfs_streq(val, "force"))
5983 else if (sysfs_streq(val, "auto"))
5984 new_val = get_nx_auto_mode();
5985 else if (strtobool(val, &new_val) < 0)
5988 __set_nx_huge_pages(new_val);
5990 if (new_val != old_val) {
5993 mutex_lock(&kvm_lock);
5995 list_for_each_entry(kvm, &vm_list, vm_list) {
5996 mutex_lock(&kvm->slots_lock);
5997 kvm_mmu_zap_all_fast(kvm);
5998 mutex_unlock(&kvm->slots_lock);
6000 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6002 mutex_unlock(&kvm_lock);
6008 int kvm_mmu_module_init(void)
6012 if (nx_huge_pages == -1)
6013 __set_nx_huge_pages(get_nx_auto_mode());
6016 * MMU roles use union aliasing which is, generally speaking, an
6017 * undefined behavior. However, we supposedly know how compilers behave
6018 * and the current status quo is unlikely to change. Guardians below are
6019 * supposed to let us know if the assumption becomes false.
6021 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
6022 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
6023 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
6025 kvm_mmu_reset_all_pte_masks();
6027 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
6028 sizeof(struct pte_list_desc),
6029 0, SLAB_ACCOUNT, NULL);
6030 if (!pte_list_desc_cache)
6033 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
6034 sizeof(struct kvm_mmu_page),
6035 0, SLAB_ACCOUNT, NULL);
6036 if (!mmu_page_header_cache)
6039 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
6042 ret = register_shrinker(&mmu_shrinker);
6049 mmu_destroy_caches();
6054 * Calculate mmu pages needed for kvm.
6056 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
6058 unsigned long nr_mmu_pages;
6059 unsigned long nr_pages = 0;
6060 struct kvm_memslots *slots;
6061 struct kvm_memory_slot *memslot;
6064 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6065 slots = __kvm_memslots(kvm, i);
6067 kvm_for_each_memslot(memslot, slots)
6068 nr_pages += memslot->npages;
6071 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
6072 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
6074 return nr_mmu_pages;
6077 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6079 kvm_mmu_unload(vcpu);
6080 free_mmu_pages(&vcpu->arch.root_mmu);
6081 free_mmu_pages(&vcpu->arch.guest_mmu);
6082 mmu_free_memory_caches(vcpu);
6085 void kvm_mmu_module_exit(void)
6087 mmu_destroy_caches();
6088 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6089 unregister_shrinker(&mmu_shrinker);
6090 mmu_audit_disable();
6093 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6095 unsigned int old_val;
6098 old_val = nx_huge_pages_recovery_ratio;
6099 err = param_set_uint(val, kp);
6103 if (READ_ONCE(nx_huge_pages) &&
6104 !old_val && nx_huge_pages_recovery_ratio) {
6107 mutex_lock(&kvm_lock);
6109 list_for_each_entry(kvm, &vm_list, vm_list)
6110 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6112 mutex_unlock(&kvm_lock);
6118 static void kvm_recover_nx_lpages(struct kvm *kvm)
6120 unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits;
6122 struct kvm_mmu_page *sp;
6124 LIST_HEAD(invalid_list);
6128 rcu_idx = srcu_read_lock(&kvm->srcu);
6129 write_lock(&kvm->mmu_lock);
6131 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6132 to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0;
6133 for ( ; to_zap; --to_zap) {
6134 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
6138 * We use a separate list instead of just using active_mmu_pages
6139 * because the number of lpage_disallowed pages is expected to
6140 * be relatively small compared to the total.
6142 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6143 struct kvm_mmu_page,
6144 lpage_disallowed_link);
6145 WARN_ON_ONCE(!sp->lpage_disallowed);
6146 if (is_tdp_mmu_page(sp)) {
6147 flush |= kvm_tdp_mmu_zap_sp(kvm, sp);
6149 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6150 WARN_ON_ONCE(sp->lpage_disallowed);
6153 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
6154 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6155 cond_resched_rwlock_write(&kvm->mmu_lock);
6159 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6161 write_unlock(&kvm->mmu_lock);
6162 srcu_read_unlock(&kvm->srcu, rcu_idx);
6165 static long get_nx_lpage_recovery_timeout(u64 start_time)
6167 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6168 ? start_time + 60 * HZ - get_jiffies_64()
6169 : MAX_SCHEDULE_TIMEOUT;
6172 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6175 long remaining_time;
6178 start_time = get_jiffies_64();
6179 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6181 set_current_state(TASK_INTERRUPTIBLE);
6182 while (!kthread_should_stop() && remaining_time > 0) {
6183 schedule_timeout(remaining_time);
6184 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6185 set_current_state(TASK_INTERRUPTIBLE);
6188 set_current_state(TASK_RUNNING);
6190 if (kthread_should_stop())
6193 kvm_recover_nx_lpages(kvm);
6197 int kvm_mmu_post_init_vm(struct kvm *kvm)
6201 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6202 "kvm-nx-lpage-recovery",
6203 &kvm->arch.nx_lpage_recovery_thread);
6205 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6210 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6212 if (kvm->arch.nx_lpage_recovery_thread)
6213 kthread_stop(kvm->arch.nx_lpage_recovery_thread);