arch/x86/kvm/lapic.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __KVM_X86_LAPIC_H
   3 #define __KVM_X86_LAPIC_H
   4
   5 #include <kvm/iodev.h>
   6
   7 #include <linux/kvm_host.h>
   8
   9 #define KVM_APIC_INIT           0
  10 #define KVM_APIC_SIPI           1
  11 #define KVM_APIC_LVT_NUM        6
  12
  13 #define APIC_SHORT_MASK                 0xc0000
  14 #define APIC_DEST_NOSHORT               0x0
  15 #define APIC_DEST_MASK                  0x800
  16
  17 #define APIC_BUS_CYCLE_NS       1
  18 #define APIC_BUS_FREQUENCY      (1000000000ULL / APIC_BUS_CYCLE_NS)
  19
  20 #define APIC_BROADCAST                  0xFF
  21 #define X2APIC_BROADCAST                0xFFFFFFFFul
  22
  23 enum lapic_mode {
  24         LAPIC_MODE_DISABLED = 0,
  25         LAPIC_MODE_INVALID = X2APIC_ENABLE,
  26         LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
  27         LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
  28 };
  29
  30 struct kvm_timer {
  31         struct hrtimer timer;
  32         s64 period;                             /* unit: ns */
  33         ktime_t target_expiration;
  34         u32 timer_mode;
  35         u32 timer_mode_mask;
  36         u64 tscdeadline;
  37         u64 expired_tscdeadline;
  38         u32 timer_advance_ns;
  39         s64 advance_expire_delta;
  40         atomic_t pending;                       /* accumulated triggered timers */
  41         bool hv_timer_in_use;
  42 };
  43
  44 struct kvm_lapic {
  45         unsigned long base_address;
  46         struct kvm_io_device dev;
  47         struct kvm_timer lapic_timer;
  48         u32 divide_count;
  49         struct kvm_vcpu *vcpu;
  50         bool sw_enabled;
  51         bool irr_pending;
  52         bool lvt0_in_nmi_mode;
  53         /* Number of bits set in ISR. */
  54         s16 isr_count;
  55         /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
  56         int highest_isr_cache;
  57         /**
  58          * APIC register page.  The layout matches the register layout seen by
  59          * the guest 1:1, because it is accessed by the vmx microcode.
  60          * Note: Only one register, the TPR, is used by the microcode.
  61          */
  62         void *regs;
  63         gpa_t vapic_addr;
  64         struct gfn_to_hva_cache vapic_cache;
  65         unsigned long pending_events;
  66         unsigned int sipi_vector;
  67 };
  68
  69 struct dest_map;
  70
  71 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
  72 void kvm_free_lapic(struct kvm_vcpu *vcpu);
  73
  74 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
  75 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
  76 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
  77 void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
  78 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
  79 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
  80 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
  81 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
  82 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
  83 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
  84 void kvm_recalculate_apic_map(struct kvm *kvm);
  85 void kvm_apic_set_version(struct kvm_vcpu *vcpu);
  86 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
  87 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
  88                        void *data);
  89 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
  90                            int shorthand, unsigned int dest, int dest_mode);
  91 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
  92 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
  93 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
  94 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
  95 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
  96                      struct dest_map *dest_map);
  97 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
  98 void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
  99
 100 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 101                 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
 102 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
 103
 104 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
 105 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
 106 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
 107 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
 108 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
 109 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
 110
 111 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
 112 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
 113
 114 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
 115 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
 116
 117 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
 118 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
 119 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
 120
 121 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
 122 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
 123
 124 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
 125 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
 126
 127 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
 128 {
 129         return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE;
 130 }
 131
 132 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
 133 void kvm_lapic_init(void);
 134 void kvm_lapic_exit(void);
 135
 136 #define VEC_POS(v) ((v) & (32 - 1))
 137 #define REG_POS(v) (((v) >> 5) << 4)
 138
 139 static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
 140 {
 141         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 142 }
 143
 144 static inline void kvm_lapic_set_vector(int vec, void *bitmap)
 145 {
 146         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 147 }
 148
 149 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
 150 {
 151         kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
 152         /*
 153          * irr_pending must be true if any interrupt is pending; set it after
 154          * APIC_IRR to avoid race with apic_clear_irr
 155          */
 156         apic->irr_pending = true;
 157 }
 158
 159 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
 160 {
 161         return *((u32 *) (apic->regs + reg_off));
 162 }
 163
 164 static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val)
 165 {
 166         *((u32 *) (regs + reg_off)) = val;
 167 }
 168
 169 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
 170 {
 171         __kvm_lapic_set_reg(apic->regs, reg_off, val);
 172 }
 173
 174 extern struct static_key kvm_no_apic_vcpu;
 175
 176 static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
 177 {
 178         if (static_key_false(&kvm_no_apic_vcpu))
 179                 return vcpu->arch.apic;
 180         return true;
 181 }
 182
 183 extern struct static_key_deferred apic_hw_disabled;
 184
 185 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
 186 {
 187         if (static_key_false(&apic_hw_disabled.key))
 188                 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 189         return MSR_IA32_APICBASE_ENABLE;
 190 }
 191
 192 extern struct static_key_deferred apic_sw_disabled;
 193
 194 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
 195 {
 196         if (static_key_false(&apic_sw_disabled.key))
 197                 return apic->sw_enabled;
 198         return true;
 199 }
 200
 201 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
 202 {
 203         return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
 204 }
 205
 206 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 207 {
 208         return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
 209 }
 210
 211 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
 212 {
 213         return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
 214 }
 215
 216 static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
 217 {
 218         return vcpu->arch.apic && vcpu->arch.apicv_active;
 219 }
 220
 221 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
 222 {
 223         return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
 224 }
 225
 226 static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
 227 {
 228         return (irq->delivery_mode == APIC_DM_LOWEST ||
 229                         irq->msi_redir_hint);
 230 }
 231
 232 static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
 233 {
 234         return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
 235 }
 236
 237 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
 238
 239 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
 240
 241 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
 242                               unsigned long *vcpu_bitmap);
 243
 244 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 245                         struct kvm_vcpu **dest_vcpu);
 246 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 247                         const unsigned long *bitmap, u32 bitmap_size);
 248 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
 249 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
 250 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
 251 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
 252 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
 253 bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);
 254
 255 static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
 256 {
 257         return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
 258 }
 259
 260 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
 261 {
 262         return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
 263 }
 264
 265 #endif