1 // SPDX-License-Identifier: GPL-2.0-only
4 * Local APIC virtualization
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2007 Novell
8 * Copyright (C) 2007 Intel
9 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
12 * Dor Laor <dor.laor@qumranet.com>
13 * Gregory Haskins <ghaskins@novell.com>
14 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
16 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
19 #include <linux/kvm_host.h>
20 #include <linux/kvm.h>
22 #include <linux/highmem.h>
23 #include <linux/smp.h>
24 #include <linux/hrtimer.h>
26 #include <linux/export.h>
27 #include <linux/math64.h>
28 #include <linux/slab.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/delay.h>
35 #include <linux/atomic.h>
36 #include <linux/jump_label.h>
37 #include "kvm_cache_regs.h"
46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48 #define mod_64(x, y) ((x) % (y))
56 /* 14 is the version for Xeon and Pentium 8.4.8*/
57 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
58 #define LAPIC_MMIO_LENGTH (1 << 12)
59 /* followed define is not in apicdef.h */
60 #define MAX_APIC_VECTOR 256
61 #define APIC_VECTORS_PER_REG 32
63 static bool lapic_timer_advance_dynamic __read_mostly;
64 #define LAPIC_TIMER_ADVANCE_ADJUST_MIN 100 /* clock cycles */
65 #define LAPIC_TIMER_ADVANCE_ADJUST_MAX 10000 /* clock cycles */
66 #define LAPIC_TIMER_ADVANCE_NS_INIT 1000
67 #define LAPIC_TIMER_ADVANCE_NS_MAX 5000
68 /* step-by-step approximation to mitigate fluctuation */
69 #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
71 static inline int apic_test_vector(int vec, void *bitmap)
73 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
76 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
78 struct kvm_lapic *apic = vcpu->arch.apic;
80 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
81 apic_test_vector(vector, apic->regs + APIC_IRR);
84 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
86 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
89 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
91 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
94 struct static_key_deferred apic_hw_disabled __read_mostly;
95 struct static_key_deferred apic_sw_disabled __read_mostly;
97 static inline int apic_enabled(struct kvm_lapic *apic)
99 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
103 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
106 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
107 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
109 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
111 return apic->vcpu->vcpu_id;
114 static bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu)
116 return pi_inject_timer && kvm_vcpu_apicv_active(vcpu);
119 bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu)
121 return kvm_x86_ops.set_hv_timer
122 && !(kvm_mwait_in_guest(vcpu->kvm) ||
123 kvm_can_post_timer_interrupt(vcpu));
125 EXPORT_SYMBOL_GPL(kvm_can_use_hv_timer);
127 static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu)
129 return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE;
132 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
133 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
135 case KVM_APIC_MODE_X2APIC: {
136 u32 offset = (dest_id >> 16) * 16;
137 u32 max_apic_id = map->max_apic_id;
139 if (offset <= max_apic_id) {
140 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
142 offset = array_index_nospec(offset, map->max_apic_id + 1);
143 *cluster = &map->phys_map[offset];
144 *mask = dest_id & (0xffff >> (16 - cluster_size));
151 case KVM_APIC_MODE_XAPIC_FLAT:
152 *cluster = map->xapic_flat_map;
153 *mask = dest_id & 0xff;
155 case KVM_APIC_MODE_XAPIC_CLUSTER:
156 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
157 *mask = dest_id & 0xf;
165 static void kvm_apic_map_free(struct rcu_head *rcu)
167 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
173 * CLEAN -> DIRTY and UPDATE_IN_PROGRESS -> DIRTY changes happen without a lock.
175 * DIRTY -> UPDATE_IN_PROGRESS and UPDATE_IN_PROGRESS -> CLEAN happen with
176 * apic_map_lock_held.
184 void kvm_recalculate_apic_map(struct kvm *kvm)
186 struct kvm_apic_map *new, *old = NULL;
187 struct kvm_vcpu *vcpu;
189 u32 max_id = 255; /* enough space for any xAPIC ID */
191 /* Read kvm->arch.apic_map_dirty before kvm->arch.apic_map. */
192 if (atomic_read_acquire(&kvm->arch.apic_map_dirty) == CLEAN)
195 mutex_lock(&kvm->arch.apic_map_lock);
197 * Read kvm->arch.apic_map_dirty before kvm->arch.apic_map
198 * (if clean) or the APIC registers (if dirty).
200 if (atomic_cmpxchg_acquire(&kvm->arch.apic_map_dirty,
201 DIRTY, UPDATE_IN_PROGRESS) == CLEAN) {
202 /* Someone else has updated the map. */
203 mutex_unlock(&kvm->arch.apic_map_lock);
207 kvm_for_each_vcpu(i, vcpu, kvm)
208 if (kvm_apic_present(vcpu))
209 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
211 new = kvzalloc(sizeof(struct kvm_apic_map) +
212 sizeof(struct kvm_lapic *) * ((u64)max_id + 1),
218 new->max_apic_id = max_id;
220 kvm_for_each_vcpu(i, vcpu, kvm) {
221 struct kvm_lapic *apic = vcpu->arch.apic;
222 struct kvm_lapic **cluster;
228 if (!kvm_apic_present(vcpu))
231 xapic_id = kvm_xapic_id(apic);
232 x2apic_id = kvm_x2apic_id(apic);
234 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
235 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
236 x2apic_id <= new->max_apic_id)
237 new->phys_map[x2apic_id] = apic;
239 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
240 * prevent them from masking VCPUs with APIC ID <= 0xff.
242 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
243 new->phys_map[xapic_id] = apic;
245 if (!kvm_apic_sw_enabled(apic))
248 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
250 if (apic_x2apic_mode(apic)) {
251 new->mode |= KVM_APIC_MODE_X2APIC;
253 ldr = GET_APIC_LOGICAL_ID(ldr);
254 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
255 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
257 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
260 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
264 cluster[ffs(mask) - 1] = apic;
267 old = rcu_dereference_protected(kvm->arch.apic_map,
268 lockdep_is_held(&kvm->arch.apic_map_lock));
269 rcu_assign_pointer(kvm->arch.apic_map, new);
271 * Write kvm->arch.apic_map before clearing apic->apic_map_dirty.
272 * If another update has come in, leave it DIRTY.
274 atomic_cmpxchg_release(&kvm->arch.apic_map_dirty,
275 UPDATE_IN_PROGRESS, CLEAN);
276 mutex_unlock(&kvm->arch.apic_map_lock);
279 call_rcu(&old->rcu, kvm_apic_map_free);
281 kvm_make_scan_ioapic_request(kvm);
284 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
286 bool enabled = val & APIC_SPIV_APIC_ENABLED;
288 kvm_lapic_set_reg(apic, APIC_SPIV, val);
290 if (enabled != apic->sw_enabled) {
291 apic->sw_enabled = enabled;
293 static_key_slow_dec_deferred(&apic_sw_disabled);
295 static_key_slow_inc(&apic_sw_disabled.key);
297 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
301 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
303 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
304 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
307 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
309 kvm_lapic_set_reg(apic, APIC_LDR, id);
310 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
313 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
315 return ((id >> 4) << 16) | (1 << (id & 0xf));
318 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
320 u32 ldr = kvm_apic_calc_x2apic_ldr(id);
322 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
324 kvm_lapic_set_reg(apic, APIC_ID, id);
325 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
326 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
329 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
331 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
334 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
336 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
339 static inline int apic_lvtt_period(struct kvm_lapic *apic)
341 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
344 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
346 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
349 static inline int apic_lvt_nmi_mode(u32 lvt_val)
351 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
354 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
356 struct kvm_lapic *apic = vcpu->arch.apic;
357 u32 v = APIC_VERSION;
359 if (!lapic_in_kernel(vcpu))
363 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
364 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
365 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
366 * version first and level-triggered interrupts never get EOIed in
369 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) &&
370 !ioapic_in_kernel(vcpu->kvm))
371 v |= APIC_LVR_DIRECTED_EOI;
372 kvm_lapic_set_reg(apic, APIC_LVR, v);
375 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
376 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
377 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
378 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
379 LINT_MASK, LINT_MASK, /* LVT0-1 */
380 LVT_MASK /* LVTERR */
383 static int find_highest_vector(void *bitmap)
388 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
389 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
390 reg = bitmap + REG_POS(vec);
392 return __fls(*reg) + vec;
398 static u8 count_vectors(void *bitmap)
404 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
405 reg = bitmap + REG_POS(vec);
406 count += hweight32(*reg);
412 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
415 u32 pir_val, irr_val, prev_irr_val;
418 max_updated_irr = -1;
421 for (i = vec = 0; i <= 7; i++, vec += 32) {
422 pir_val = READ_ONCE(pir[i]);
423 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
425 prev_irr_val = irr_val;
426 irr_val |= xchg(&pir[i], 0);
427 *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
428 if (prev_irr_val != irr_val) {
430 __fls(irr_val ^ prev_irr_val) + vec;
434 *max_irr = __fls(irr_val) + vec;
437 return ((max_updated_irr != -1) &&
438 (max_updated_irr == *max_irr));
440 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
442 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
444 struct kvm_lapic *apic = vcpu->arch.apic;
446 return __kvm_apic_update_irr(pir, apic->regs, max_irr);
448 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
450 static inline int apic_search_irr(struct kvm_lapic *apic)
452 return find_highest_vector(apic->regs + APIC_IRR);
455 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
460 * Note that irr_pending is just a hint. It will be always
461 * true with virtual interrupt delivery enabled.
463 if (!apic->irr_pending)
466 result = apic_search_irr(apic);
467 ASSERT(result == -1 || result >= 16);
472 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
474 struct kvm_vcpu *vcpu;
478 if (unlikely(vcpu->arch.apicv_active)) {
479 /* need to update RVI */
480 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
481 kvm_x86_ops.hwapic_irr_update(vcpu,
482 apic_find_highest_irr(apic));
484 apic->irr_pending = false;
485 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
486 if (apic_search_irr(apic) != -1)
487 apic->irr_pending = true;
491 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
493 struct kvm_vcpu *vcpu;
495 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
501 * With APIC virtualization enabled, all caching is disabled
502 * because the processor can modify ISR under the hood. Instead
505 if (unlikely(vcpu->arch.apicv_active))
506 kvm_x86_ops.hwapic_isr_update(vcpu, vec);
509 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
511 * ISR (in service register) bit is set when injecting an interrupt.
512 * The highest vector is injected. Thus the latest bit set matches
513 * the highest bit in ISR.
515 apic->highest_isr_cache = vec;
519 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
524 * Note that isr_count is always 1, and highest_isr_cache
525 * is always -1, with APIC virtualization enabled.
527 if (!apic->isr_count)
529 if (likely(apic->highest_isr_cache != -1))
530 return apic->highest_isr_cache;
532 result = find_highest_vector(apic->regs + APIC_ISR);
533 ASSERT(result == -1 || result >= 16);
538 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
540 struct kvm_vcpu *vcpu;
541 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
547 * We do get here for APIC virtualization enabled if the guest
548 * uses the Hyper-V APIC enlightenment. In this case we may need
549 * to trigger a new interrupt delivery by writing the SVI field;
550 * on the other hand isr_count and highest_isr_cache are unused
551 * and must be left alone.
553 if (unlikely(vcpu->arch.apicv_active))
554 kvm_x86_ops.hwapic_isr_update(vcpu,
555 apic_find_highest_isr(apic));
558 BUG_ON(apic->isr_count < 0);
559 apic->highest_isr_cache = -1;
563 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
565 /* This may race with setting of irr in __apic_accept_irq() and
566 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
567 * will cause vmexit immediately and the value will be recalculated
568 * on the next vmentry.
570 return apic_find_highest_irr(vcpu->arch.apic);
572 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
574 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
575 int vector, int level, int trig_mode,
576 struct dest_map *dest_map);
578 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
579 struct dest_map *dest_map)
581 struct kvm_lapic *apic = vcpu->arch.apic;
583 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
584 irq->level, irq->trig_mode, dest_map);
587 static int __pv_send_ipi(unsigned long *ipi_bitmap, struct kvm_apic_map *map,
588 struct kvm_lapic_irq *irq, u32 min)
591 struct kvm_vcpu *vcpu;
593 if (min > map->max_apic_id)
596 for_each_set_bit(i, ipi_bitmap,
597 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
598 if (map->phys_map[min + i]) {
599 vcpu = map->phys_map[min + i]->vcpu;
600 count += kvm_apic_set_irq(vcpu, irq, NULL);
607 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
608 unsigned long ipi_bitmap_high, u32 min,
609 unsigned long icr, int op_64_bit)
611 struct kvm_apic_map *map;
612 struct kvm_lapic_irq irq = {0};
613 int cluster_size = op_64_bit ? 64 : 32;
616 if (icr & (APIC_DEST_MASK | APIC_SHORT_MASK))
619 irq.vector = icr & APIC_VECTOR_MASK;
620 irq.delivery_mode = icr & APIC_MODE_MASK;
621 irq.level = (icr & APIC_INT_ASSERT) != 0;
622 irq.trig_mode = icr & APIC_INT_LEVELTRIG;
625 map = rcu_dereference(kvm->arch.apic_map);
629 count = __pv_send_ipi(&ipi_bitmap_low, map, &irq, min);
631 count += __pv_send_ipi(&ipi_bitmap_high, map, &irq, min);
638 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
641 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
645 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
648 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
652 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
654 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
657 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
660 if (pv_eoi_get_user(vcpu, &val) < 0) {
661 printk(KERN_WARNING "Can't read EOI MSR value: 0x%llx\n",
662 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
668 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
670 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
671 printk(KERN_WARNING "Can't set EOI MSR value: 0x%llx\n",
672 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
675 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
678 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
680 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
681 printk(KERN_WARNING "Can't clear EOI MSR value: 0x%llx\n",
682 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
685 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
688 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
691 if (apic->vcpu->arch.apicv_active)
692 highest_irr = kvm_x86_ops.sync_pir_to_irr(apic->vcpu);
694 highest_irr = apic_find_highest_irr(apic);
695 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
700 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
702 u32 tpr, isrv, ppr, old_ppr;
705 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
706 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
707 isr = apic_find_highest_isr(apic);
708 isrv = (isr != -1) ? isr : 0;
710 if ((tpr & 0xf0) >= (isrv & 0xf0))
717 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
719 return ppr < old_ppr;
722 static void apic_update_ppr(struct kvm_lapic *apic)
726 if (__apic_update_ppr(apic, &ppr) &&
727 apic_has_interrupt_for_ppr(apic, ppr) != -1)
728 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
731 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
733 apic_update_ppr(vcpu->arch.apic);
735 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
737 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
739 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
740 apic_update_ppr(apic);
743 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
745 return mda == (apic_x2apic_mode(apic) ?
746 X2APIC_BROADCAST : APIC_BROADCAST);
749 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
751 if (kvm_apic_broadcast(apic, mda))
754 if (apic_x2apic_mode(apic))
755 return mda == kvm_x2apic_id(apic);
758 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
759 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
760 * this allows unique addressing of VCPUs with APIC ID over 0xff.
761 * The 0xff condition is needed because writeable xAPIC ID.
763 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
766 return mda == kvm_xapic_id(apic);
769 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
773 if (kvm_apic_broadcast(apic, mda))
776 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
778 if (apic_x2apic_mode(apic))
779 return ((logical_id >> 16) == (mda >> 16))
780 && (logical_id & mda & 0xffff) != 0;
782 logical_id = GET_APIC_LOGICAL_ID(logical_id);
784 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
786 return (logical_id & mda) != 0;
787 case APIC_DFR_CLUSTER:
788 return ((logical_id >> 4) == (mda >> 4))
789 && (logical_id & mda & 0xf) != 0;
795 /* The KVM local APIC implementation has two quirks:
797 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
798 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
799 * KVM doesn't do that aliasing.
801 * - in-kernel IOAPIC messages have to be delivered directly to
802 * x2APIC, because the kernel does not support interrupt remapping.
803 * In order to support broadcast without interrupt remapping, x2APIC
804 * rewrites the destination of non-IPI messages from APIC_BROADCAST
805 * to X2APIC_BROADCAST.
807 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
808 * important when userspace wants to use x2APIC-format MSIs, because
809 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
811 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
812 struct kvm_lapic *source, struct kvm_lapic *target)
814 bool ipi = source != NULL;
816 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
817 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
818 return X2APIC_BROADCAST;
823 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
824 int shorthand, unsigned int dest, int dest_mode)
826 struct kvm_lapic *target = vcpu->arch.apic;
827 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
831 case APIC_DEST_NOSHORT:
832 if (dest_mode == APIC_DEST_PHYSICAL)
833 return kvm_apic_match_physical_addr(target, mda);
835 return kvm_apic_match_logical_addr(target, mda);
837 return target == source;
838 case APIC_DEST_ALLINC:
840 case APIC_DEST_ALLBUT:
841 return target != source;
846 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
848 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
849 const unsigned long *bitmap, u32 bitmap_size)
854 mod = vector % dest_vcpus;
856 for (i = 0; i <= mod; i++) {
857 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
858 BUG_ON(idx == bitmap_size);
864 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
866 if (!kvm->arch.disabled_lapic_found) {
867 kvm->arch.disabled_lapic_found = true;
869 "Disabled LAPIC found during irq injection\n");
873 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
874 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
876 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
877 if ((irq->dest_id == APIC_BROADCAST &&
878 map->mode != KVM_APIC_MODE_X2APIC))
880 if (irq->dest_id == X2APIC_BROADCAST)
883 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
884 if (irq->dest_id == (x2apic_ipi ?
885 X2APIC_BROADCAST : APIC_BROADCAST))
892 /* Return true if the interrupt can be handled by using *bitmap as index mask
893 * for valid destinations in *dst array.
894 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
895 * Note: we may have zero kvm_lapic destinations when we return true, which
896 * means that the interrupt should be dropped. In this case, *bitmap would be
897 * zero and *dst undefined.
899 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
900 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
901 struct kvm_apic_map *map, struct kvm_lapic ***dst,
902 unsigned long *bitmap)
906 if (irq->shorthand == APIC_DEST_SELF && src) {
910 } else if (irq->shorthand)
913 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
916 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
917 if (irq->dest_id > map->max_apic_id) {
920 u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1);
921 *dst = &map->phys_map[dest_id];
928 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
932 if (!kvm_lowest_prio_delivery(irq))
935 if (!kvm_vector_hashing_enabled()) {
937 for_each_set_bit(i, bitmap, 16) {
942 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
943 (*dst)[lowest]->vcpu) < 0)
950 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
953 if (!(*dst)[lowest]) {
954 kvm_apic_disabled_lapic_found(kvm);
960 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
965 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
966 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
968 struct kvm_apic_map *map;
969 unsigned long bitmap;
970 struct kvm_lapic **dst = NULL;
976 if (irq->shorthand == APIC_DEST_SELF) {
977 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
982 map = rcu_dereference(kvm->arch.apic_map);
984 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
987 for_each_set_bit(i, &bitmap, 16) {
990 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
999 * This routine tries to handle interrupts in posted mode, here is how
1000 * it deals with different cases:
1001 * - For single-destination interrupts, handle it in posted mode
1002 * - Else if vector hashing is enabled and it is a lowest-priority
1003 * interrupt, handle it in posted mode and use the following mechanism
1004 * to find the destination vCPU.
1005 * 1. For lowest-priority interrupts, store all the possible
1006 * destination vCPUs in an array.
1007 * 2. Use "guest vector % max number of destination vCPUs" to find
1008 * the right destination vCPU in the array for the lowest-priority
1010 * - Otherwise, use remapped mode to inject the interrupt.
1012 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
1013 struct kvm_vcpu **dest_vcpu)
1015 struct kvm_apic_map *map;
1016 unsigned long bitmap;
1017 struct kvm_lapic **dst = NULL;
1024 map = rcu_dereference(kvm->arch.apic_map);
1026 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1027 hweight16(bitmap) == 1) {
1028 unsigned long i = find_first_bit(&bitmap, 16);
1031 *dest_vcpu = dst[i]->vcpu;
1041 * Add a pending IRQ into lapic.
1042 * Return 1 if successfully added and 0 if discarded.
1044 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1045 int vector, int level, int trig_mode,
1046 struct dest_map *dest_map)
1049 struct kvm_vcpu *vcpu = apic->vcpu;
1051 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1053 switch (delivery_mode) {
1054 case APIC_DM_LOWEST:
1055 vcpu->arch.apic_arb_prio++;
1058 if (unlikely(trig_mode && !level))
1061 /* FIXME add logic for vcpu on reset */
1062 if (unlikely(!apic_enabled(apic)))
1068 __set_bit(vcpu->vcpu_id, dest_map->map);
1069 dest_map->vectors[vcpu->vcpu_id] = vector;
1072 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1074 kvm_lapic_set_vector(vector,
1075 apic->regs + APIC_TMR);
1077 kvm_lapic_clear_vector(vector,
1078 apic->regs + APIC_TMR);
1081 if (kvm_x86_ops.deliver_posted_interrupt(vcpu, vector)) {
1082 kvm_lapic_set_irr(vector, apic);
1083 kvm_make_request(KVM_REQ_EVENT, vcpu);
1084 kvm_vcpu_kick(vcpu);
1090 vcpu->arch.pv.pv_unhalted = 1;
1091 kvm_make_request(KVM_REQ_EVENT, vcpu);
1092 kvm_vcpu_kick(vcpu);
1097 kvm_make_request(KVM_REQ_SMI, vcpu);
1098 kvm_vcpu_kick(vcpu);
1103 kvm_inject_nmi(vcpu);
1104 kvm_vcpu_kick(vcpu);
1108 if (!trig_mode || level) {
1110 /* assumes that there are only KVM_APIC_INIT/SIPI */
1111 apic->pending_events = (1UL << KVM_APIC_INIT);
1112 kvm_make_request(KVM_REQ_EVENT, vcpu);
1113 kvm_vcpu_kick(vcpu);
1117 case APIC_DM_STARTUP:
1119 apic->sipi_vector = vector;
1120 /* make sure sipi_vector is visible for the receiver */
1122 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1123 kvm_make_request(KVM_REQ_EVENT, vcpu);
1124 kvm_vcpu_kick(vcpu);
1127 case APIC_DM_EXTINT:
1129 * Should only be called by kvm_apic_local_deliver() with LVT0,
1130 * before NMI watchdog was enabled. Already handled by
1131 * kvm_apic_accept_pic_intr().
1136 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1144 * This routine identifies the destination vcpus mask meant to receive the
1145 * IOAPIC interrupts. It either uses kvm_apic_map_get_dest_lapic() to find
1146 * out the destination vcpus array and set the bitmap or it traverses to
1147 * each available vcpu to identify the same.
1149 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
1150 unsigned long *vcpu_bitmap)
1152 struct kvm_lapic **dest_vcpu = NULL;
1153 struct kvm_lapic *src = NULL;
1154 struct kvm_apic_map *map;
1155 struct kvm_vcpu *vcpu;
1156 unsigned long bitmap;
1161 map = rcu_dereference(kvm->arch.apic_map);
1163 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dest_vcpu,
1166 for_each_set_bit(i, &bitmap, 16) {
1169 vcpu_idx = dest_vcpu[i]->vcpu->vcpu_idx;
1170 __set_bit(vcpu_idx, vcpu_bitmap);
1173 kvm_for_each_vcpu(i, vcpu, kvm) {
1174 if (!kvm_apic_present(vcpu))
1176 if (!kvm_apic_match_dest(vcpu, NULL,
1181 __set_bit(i, vcpu_bitmap);
1187 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1189 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1192 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1194 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1197 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1201 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1202 if (!kvm_ioapic_handles_vector(apic, vector))
1205 /* Request a KVM exit to inform the userspace IOAPIC. */
1206 if (irqchip_split(apic->vcpu->kvm)) {
1207 apic->vcpu->arch.pending_ioapic_eoi = vector;
1208 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1212 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1213 trigger_mode = IOAPIC_LEVEL_TRIG;
1215 trigger_mode = IOAPIC_EDGE_TRIG;
1217 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1220 static int apic_set_eoi(struct kvm_lapic *apic)
1222 int vector = apic_find_highest_isr(apic);
1224 trace_kvm_eoi(apic, vector);
1227 * Not every write EOI will has corresponding ISR,
1228 * one example is when Kernel check timer on setup_IO_APIC
1233 apic_clear_isr(vector, apic);
1234 apic_update_ppr(apic);
1236 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1237 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1239 kvm_ioapic_send_eoi(apic, vector);
1240 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1245 * this interface assumes a trap-like exit, which has already finished
1246 * desired side effect including vISR and vPPR update.
1248 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1250 struct kvm_lapic *apic = vcpu->arch.apic;
1252 trace_kvm_eoi(apic, vector);
1254 kvm_ioapic_send_eoi(apic, vector);
1255 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1257 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1259 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high)
1261 struct kvm_lapic_irq irq;
1263 irq.vector = icr_low & APIC_VECTOR_MASK;
1264 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1265 irq.dest_mode = icr_low & APIC_DEST_MASK;
1266 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1267 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1268 irq.shorthand = icr_low & APIC_SHORT_MASK;
1269 irq.msi_redir_hint = false;
1270 if (apic_x2apic_mode(apic))
1271 irq.dest_id = icr_high;
1273 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1275 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1277 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1280 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1282 ktime_t remaining, now;
1286 ASSERT(apic != NULL);
1288 /* if initial count is 0, current count should also be 0 */
1289 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1290 apic->lapic_timer.period == 0)
1294 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1295 if (ktime_to_ns(remaining) < 0)
1298 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1299 tmcct = div64_u64(ns,
1300 (APIC_BUS_CYCLE_NS * apic->divide_count));
1305 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1307 struct kvm_vcpu *vcpu = apic->vcpu;
1308 struct kvm_run *run = vcpu->run;
1310 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1311 run->tpr_access.rip = kvm_rip_read(vcpu);
1312 run->tpr_access.is_write = write;
1315 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1317 if (apic->vcpu->arch.tpr_access_reporting)
1318 __report_tpr_access(apic, write);
1321 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1325 if (offset >= LAPIC_MMIO_LENGTH)
1332 case APIC_TMCCT: /* Timer CCR */
1333 if (apic_lvtt_tscdeadline(apic))
1336 val = apic_get_tmcct(apic);
1339 apic_update_ppr(apic);
1340 val = kvm_lapic_get_reg(apic, offset);
1343 report_tpr_access(apic, false);
1346 val = kvm_lapic_get_reg(apic, offset);
1353 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1355 return container_of(dev, struct kvm_lapic, dev);
1358 #define APIC_REG_MASK(reg) (1ull << ((reg) >> 4))
1359 #define APIC_REGS_MASK(first, count) \
1360 (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1362 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1365 unsigned char alignment = offset & 0xf;
1367 /* this bitmask has a bit cleared for each reserved register */
1368 u64 valid_reg_mask =
1369 APIC_REG_MASK(APIC_ID) |
1370 APIC_REG_MASK(APIC_LVR) |
1371 APIC_REG_MASK(APIC_TASKPRI) |
1372 APIC_REG_MASK(APIC_PROCPRI) |
1373 APIC_REG_MASK(APIC_LDR) |
1374 APIC_REG_MASK(APIC_DFR) |
1375 APIC_REG_MASK(APIC_SPIV) |
1376 APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) |
1377 APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) |
1378 APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) |
1379 APIC_REG_MASK(APIC_ESR) |
1380 APIC_REG_MASK(APIC_ICR) |
1381 APIC_REG_MASK(APIC_ICR2) |
1382 APIC_REG_MASK(APIC_LVTT) |
1383 APIC_REG_MASK(APIC_LVTTHMR) |
1384 APIC_REG_MASK(APIC_LVTPC) |
1385 APIC_REG_MASK(APIC_LVT0) |
1386 APIC_REG_MASK(APIC_LVT1) |
1387 APIC_REG_MASK(APIC_LVTERR) |
1388 APIC_REG_MASK(APIC_TMICT) |
1389 APIC_REG_MASK(APIC_TMCCT) |
1390 APIC_REG_MASK(APIC_TDCR);
1392 /* ARBPRI is not valid on x2APIC */
1393 if (!apic_x2apic_mode(apic))
1394 valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI);
1396 if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset)))
1399 result = __apic_read(apic, offset & ~0xf);
1401 trace_kvm_apic_read(offset, result);
1407 memcpy(data, (char *)&result + alignment, len);
1410 printk(KERN_ERR "Local APIC read with len = %x, "
1411 "should be 1,2, or 4 instead\n", len);
1416 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1418 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1420 return addr >= apic->base_address &&
1421 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1424 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1425 gpa_t address, int len, void *data)
1427 struct kvm_lapic *apic = to_lapic(this);
1428 u32 offset = address - apic->base_address;
1430 if (!apic_mmio_in_range(apic, address))
1433 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1434 if (!kvm_check_has_quirk(vcpu->kvm,
1435 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1438 memset(data, 0xff, len);
1442 kvm_lapic_reg_read(apic, offset, len, data);
1447 static void update_divide_count(struct kvm_lapic *apic)
1449 u32 tmp1, tmp2, tdcr;
1451 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1453 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1454 apic->divide_count = 0x1 << (tmp2 & 0x7);
1457 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1460 * Do not allow the guest to program periodic timers with small
1461 * interval, since the hrtimers are not throttled by the host
1464 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1465 s64 min_period = min_timer_period_us * 1000LL;
1467 if (apic->lapic_timer.period < min_period) {
1468 pr_info_ratelimited(
1469 "kvm: vcpu %i: requested %lld ns "
1470 "lapic timer period limited to %lld ns\n",
1471 apic->vcpu->vcpu_id,
1472 apic->lapic_timer.period, min_period);
1473 apic->lapic_timer.period = min_period;
1478 static void cancel_hv_timer(struct kvm_lapic *apic);
1480 static void apic_update_lvtt(struct kvm_lapic *apic)
1482 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1483 apic->lapic_timer.timer_mode_mask;
1485 if (apic->lapic_timer.timer_mode != timer_mode) {
1486 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1487 APIC_LVT_TIMER_TSCDEADLINE)) {
1488 hrtimer_cancel(&apic->lapic_timer.timer);
1490 if (apic->lapic_timer.hv_timer_in_use)
1491 cancel_hv_timer(apic);
1493 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1494 apic->lapic_timer.period = 0;
1495 apic->lapic_timer.tscdeadline = 0;
1497 apic->lapic_timer.timer_mode = timer_mode;
1498 limit_periodic_timer_frequency(apic);
1503 * On APICv, this test will cause a busy wait
1504 * during a higher-priority task.
1507 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1509 struct kvm_lapic *apic = vcpu->arch.apic;
1510 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1512 if (kvm_apic_hw_enabled(apic)) {
1513 int vec = reg & APIC_VECTOR_MASK;
1514 void *bitmap = apic->regs + APIC_ISR;
1516 if (vcpu->arch.apicv_active)
1517 bitmap = apic->regs + APIC_IRR;
1519 if (apic_test_vector(vec, bitmap))
1525 static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles)
1527 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;
1530 * If the guest TSC is running at a different ratio than the host, then
1531 * convert the delay to nanoseconds to achieve an accurate delay. Note
1532 * that __delay() uses delay_tsc whenever the hardware has TSC, thus
1533 * always for VMX enabled hardware.
1535 if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) {
1536 __delay(min(guest_cycles,
1537 nsec_to_cycles(vcpu, timer_advance_ns)));
1539 u64 delay_ns = guest_cycles * 1000000ULL;
1540 do_div(delay_ns, vcpu->arch.virtual_tsc_khz);
1541 ndelay(min_t(u32, delay_ns, timer_advance_ns));
1545 static inline void adjust_lapic_timer_advance(struct kvm_vcpu *vcpu,
1546 s64 advance_expire_delta)
1548 struct kvm_lapic *apic = vcpu->arch.apic;
1549 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
1552 /* Do not adjust for tiny fluctuations or large random spikes. */
1553 if (abs(advance_expire_delta) > LAPIC_TIMER_ADVANCE_ADJUST_MAX ||
1554 abs(advance_expire_delta) < LAPIC_TIMER_ADVANCE_ADJUST_MIN)
1558 if (advance_expire_delta < 0) {
1559 ns = -advance_expire_delta * 1000000ULL;
1560 do_div(ns, vcpu->arch.virtual_tsc_khz);
1561 timer_advance_ns -= ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
1564 ns = advance_expire_delta * 1000000ULL;
1565 do_div(ns, vcpu->arch.virtual_tsc_khz);
1566 timer_advance_ns += ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
1569 if (unlikely(timer_advance_ns > LAPIC_TIMER_ADVANCE_NS_MAX))
1570 timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
1571 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
1574 static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1576 struct kvm_lapic *apic = vcpu->arch.apic;
1577 u64 guest_tsc, tsc_deadline;
1579 if (apic->lapic_timer.expired_tscdeadline == 0)
1582 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1583 apic->lapic_timer.expired_tscdeadline = 0;
1584 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1585 apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline;
1587 if (guest_tsc < tsc_deadline)
1588 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
1590 if (lapic_timer_advance_dynamic)
1591 adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta);
1594 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1596 if (lapic_timer_int_injected(vcpu))
1597 __kvm_wait_lapic_expire(vcpu);
1599 EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire);
1601 static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic)
1603 struct kvm_timer *ktimer = &apic->lapic_timer;
1605 kvm_apic_local_deliver(apic, APIC_LVTT);
1606 if (apic_lvtt_tscdeadline(apic)) {
1607 ktimer->tscdeadline = 0;
1608 } else if (apic_lvtt_oneshot(apic)) {
1609 ktimer->tscdeadline = 0;
1610 ktimer->target_expiration = 0;
1614 static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn)
1616 struct kvm_vcpu *vcpu = apic->vcpu;
1617 struct kvm_timer *ktimer = &apic->lapic_timer;
1619 if (atomic_read(&apic->lapic_timer.pending))
1622 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
1623 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1625 if (!from_timer_fn && vcpu->arch.apicv_active) {
1626 WARN_ON(kvm_get_running_vcpu() != vcpu);
1627 kvm_apic_inject_pending_timer_irqs(apic);
1631 if (kvm_use_posted_timer_interrupt(apic->vcpu)) {
1632 if (apic->lapic_timer.timer_advance_ns)
1633 __kvm_wait_lapic_expire(vcpu);
1634 kvm_apic_inject_pending_timer_irqs(apic);
1638 atomic_inc(&apic->lapic_timer.pending);
1639 kvm_set_pending_timer(vcpu);
1642 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1644 struct kvm_timer *ktimer = &apic->lapic_timer;
1645 u64 guest_tsc, tscdeadline = ktimer->tscdeadline;
1648 struct kvm_vcpu *vcpu = apic->vcpu;
1649 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1650 unsigned long flags;
1653 if (unlikely(!tscdeadline || !this_tsc_khz))
1656 local_irq_save(flags);
1659 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1661 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1662 do_div(ns, this_tsc_khz);
1664 if (likely(tscdeadline > guest_tsc) &&
1665 likely(ns > apic->lapic_timer.timer_advance_ns)) {
1666 expire = ktime_add_ns(now, ns);
1667 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns);
1668 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD);
1670 apic_timer_expired(apic, false);
1672 local_irq_restore(flags);
1675 static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict)
1677 return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count;
1680 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1682 ktime_t now, remaining;
1683 u64 ns_remaining_old, ns_remaining_new;
1685 apic->lapic_timer.period =
1686 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));
1687 limit_periodic_timer_frequency(apic);
1690 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1691 if (ktime_to_ns(remaining) < 0)
1694 ns_remaining_old = ktime_to_ns(remaining);
1695 ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1696 apic->divide_count, old_divisor);
1698 apic->lapic_timer.tscdeadline +=
1699 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1700 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1701 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1704 static bool set_target_expiration(struct kvm_lapic *apic, u32 count_reg)
1711 apic->lapic_timer.period =
1712 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));
1714 if (!apic->lapic_timer.period) {
1715 apic->lapic_timer.tscdeadline = 0;
1719 limit_periodic_timer_frequency(apic);
1720 deadline = apic->lapic_timer.period;
1722 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1723 if (unlikely(count_reg != APIC_TMICT)) {
1724 deadline = tmict_to_ns(apic,
1725 kvm_lapic_get_reg(apic, count_reg));
1726 if (unlikely(deadline <= 0))
1727 deadline = apic->lapic_timer.period;
1728 else if (unlikely(deadline > apic->lapic_timer.period)) {
1729 pr_info_ratelimited(
1730 "kvm: vcpu %i: requested lapic timer restore with "
1731 "starting count register %#x=%u (%lld ns) > initial count (%lld ns). "
1732 "Using initial count to start timer.\n",
1733 apic->vcpu->vcpu_id,
1735 kvm_lapic_get_reg(apic, count_reg),
1736 deadline, apic->lapic_timer.period);
1737 kvm_lapic_set_reg(apic, count_reg, 0);
1738 deadline = apic->lapic_timer.period;
1743 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1744 nsec_to_cycles(apic->vcpu, deadline);
1745 apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline);
1750 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1752 ktime_t now = ktime_get();
1757 * Synchronize both deadlines to the same time source or
1758 * differences in the periods (caused by differences in the
1759 * underlying clocks or numerical approximation errors) will
1760 * cause the two to drift apart over time as the errors
1763 apic->lapic_timer.target_expiration =
1764 ktime_add_ns(apic->lapic_timer.target_expiration,
1765 apic->lapic_timer.period);
1766 delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1767 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1768 nsec_to_cycles(apic->vcpu, delta);
1771 static void start_sw_period(struct kvm_lapic *apic)
1773 if (!apic->lapic_timer.period)
1776 if (ktime_after(ktime_get(),
1777 apic->lapic_timer.target_expiration)) {
1778 apic_timer_expired(apic, false);
1780 if (apic_lvtt_oneshot(apic))
1783 advance_periodic_target_expiration(apic);
1786 hrtimer_start(&apic->lapic_timer.timer,
1787 apic->lapic_timer.target_expiration,
1788 HRTIMER_MODE_ABS_HARD);
1791 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1793 if (!lapic_in_kernel(vcpu))
1796 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1798 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1800 static void cancel_hv_timer(struct kvm_lapic *apic)
1802 WARN_ON(preemptible());
1803 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1804 kvm_x86_ops.cancel_hv_timer(apic->vcpu);
1805 apic->lapic_timer.hv_timer_in_use = false;
1808 static bool start_hv_timer(struct kvm_lapic *apic)
1810 struct kvm_timer *ktimer = &apic->lapic_timer;
1811 struct kvm_vcpu *vcpu = apic->vcpu;
1814 WARN_ON(preemptible());
1815 if (!kvm_can_use_hv_timer(vcpu))
1818 if (!ktimer->tscdeadline)
1821 if (kvm_x86_ops.set_hv_timer(vcpu, ktimer->tscdeadline, &expired))
1824 ktimer->hv_timer_in_use = true;
1825 hrtimer_cancel(&ktimer->timer);
1828 * To simplify handling the periodic timer, leave the hv timer running
1829 * even if the deadline timer has expired, i.e. rely on the resulting
1830 * VM-Exit to recompute the periodic timer's target expiration.
1832 if (!apic_lvtt_period(apic)) {
1834 * Cancel the hv timer if the sw timer fired while the hv timer
1835 * was being programmed, or if the hv timer itself expired.
1837 if (atomic_read(&ktimer->pending)) {
1838 cancel_hv_timer(apic);
1839 } else if (expired) {
1840 apic_timer_expired(apic, false);
1841 cancel_hv_timer(apic);
1845 trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use);
1850 static void start_sw_timer(struct kvm_lapic *apic)
1852 struct kvm_timer *ktimer = &apic->lapic_timer;
1854 WARN_ON(preemptible());
1855 if (apic->lapic_timer.hv_timer_in_use)
1856 cancel_hv_timer(apic);
1857 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1860 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1861 start_sw_period(apic);
1862 else if (apic_lvtt_tscdeadline(apic))
1863 start_sw_tscdeadline(apic);
1864 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1867 static void restart_apic_timer(struct kvm_lapic *apic)
1871 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending))
1874 if (!start_hv_timer(apic))
1875 start_sw_timer(apic);
1880 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1882 struct kvm_lapic *apic = vcpu->arch.apic;
1885 /* If the preempt notifier has already run, it also called apic_timer_expired */
1886 if (!apic->lapic_timer.hv_timer_in_use)
1888 WARN_ON(rcuwait_active(&vcpu->wait));
1889 cancel_hv_timer(apic);
1890 apic_timer_expired(apic, false);
1892 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1893 advance_periodic_target_expiration(apic);
1894 restart_apic_timer(apic);
1899 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1901 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1903 restart_apic_timer(vcpu->arch.apic);
1905 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1907 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1909 struct kvm_lapic *apic = vcpu->arch.apic;
1912 /* Possibly the TSC deadline timer is not enabled yet */
1913 if (apic->lapic_timer.hv_timer_in_use)
1914 start_sw_timer(apic);
1917 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1919 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1921 struct kvm_lapic *apic = vcpu->arch.apic;
1923 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1924 restart_apic_timer(apic);
1927 static void __start_apic_timer(struct kvm_lapic *apic, u32 count_reg)
1929 atomic_set(&apic->lapic_timer.pending, 0);
1931 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1932 && !set_target_expiration(apic, count_reg))
1935 restart_apic_timer(apic);
1938 static void start_apic_timer(struct kvm_lapic *apic)
1940 __start_apic_timer(apic, APIC_TMICT);
1943 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1945 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1947 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1948 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1949 if (lvt0_in_nmi_mode) {
1950 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1952 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1956 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1960 trace_kvm_apic_write(reg, val);
1963 case APIC_ID: /* Local APIC ID */
1964 if (!apic_x2apic_mode(apic))
1965 kvm_apic_set_xapic_id(apic, val >> 24);
1971 report_tpr_access(apic, true);
1972 apic_set_tpr(apic, val & 0xff);
1980 if (!apic_x2apic_mode(apic))
1981 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1987 if (!apic_x2apic_mode(apic)) {
1988 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1989 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
1996 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1997 mask |= APIC_SPIV_DIRECTED_EOI;
1998 apic_set_spiv(apic, val & mask);
1999 if (!(val & APIC_SPIV_APIC_ENABLED)) {
2003 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
2004 lvt_val = kvm_lapic_get_reg(apic,
2005 APIC_LVTT + 0x10 * i);
2006 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
2007 lvt_val | APIC_LVT_MASKED);
2009 apic_update_lvtt(apic);
2010 atomic_set(&apic->lapic_timer.pending, 0);
2016 /* No delay here, so we always clear the pending bit */
2018 kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2));
2019 kvm_lapic_set_reg(apic, APIC_ICR, val);
2023 if (!apic_x2apic_mode(apic))
2025 kvm_lapic_set_reg(apic, APIC_ICR2, val);
2029 apic_manage_nmi_watchdog(apic, val);
2035 /* TODO: Check vector */
2039 if (!kvm_apic_sw_enabled(apic))
2040 val |= APIC_LVT_MASKED;
2041 size = ARRAY_SIZE(apic_lvt_mask);
2042 index = array_index_nospec(
2043 (reg - APIC_LVTT) >> 4, size);
2044 val &= apic_lvt_mask[index];
2045 kvm_lapic_set_reg(apic, reg, val);
2050 if (!kvm_apic_sw_enabled(apic))
2051 val |= APIC_LVT_MASKED;
2052 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
2053 kvm_lapic_set_reg(apic, APIC_LVTT, val);
2054 apic_update_lvtt(apic);
2058 if (apic_lvtt_tscdeadline(apic))
2061 hrtimer_cancel(&apic->lapic_timer.timer);
2062 kvm_lapic_set_reg(apic, APIC_TMICT, val);
2063 start_apic_timer(apic);
2067 uint32_t old_divisor = apic->divide_count;
2069 kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb);
2070 update_divide_count(apic);
2071 if (apic->divide_count != old_divisor &&
2072 apic->lapic_timer.period) {
2073 hrtimer_cancel(&apic->lapic_timer.timer);
2074 update_target_expiration(apic, old_divisor);
2075 restart_apic_timer(apic);
2080 if (apic_x2apic_mode(apic) && val != 0)
2085 if (apic_x2apic_mode(apic)) {
2086 kvm_lapic_reg_write(apic, APIC_ICR,
2087 APIC_DEST_SELF | (val & APIC_VECTOR_MASK));
2096 kvm_recalculate_apic_map(apic->vcpu->kvm);
2100 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
2102 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
2103 gpa_t address, int len, const void *data)
2105 struct kvm_lapic *apic = to_lapic(this);
2106 unsigned int offset = address - apic->base_address;
2109 if (!apic_mmio_in_range(apic, address))
2112 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
2113 if (!kvm_check_has_quirk(vcpu->kvm,
2114 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
2121 * APIC register must be aligned on 128-bits boundary.
2122 * 32/64/128 bits registers must be accessed thru 32 bits.
2125 if (len != 4 || (offset & 0xf))
2130 kvm_lapic_reg_write(apic, offset & 0xff0, val);
2135 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
2137 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
2139 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
2141 /* emulate APIC access in a trap manner */
2142 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
2146 /* hw has done the conditional check and inst decode */
2149 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
2151 /* TODO: optimize to just emulate side effect w/o one more write */
2152 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
2154 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2156 void kvm_free_lapic(struct kvm_vcpu *vcpu)
2158 struct kvm_lapic *apic = vcpu->arch.apic;
2160 if (!vcpu->arch.apic)
2163 hrtimer_cancel(&apic->lapic_timer.timer);
2165 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2166 static_key_slow_dec_deferred(&apic_hw_disabled);
2168 if (!apic->sw_enabled)
2169 static_key_slow_dec_deferred(&apic_sw_disabled);
2172 free_page((unsigned long)apic->regs);
2178 *----------------------------------------------------------------------
2180 *----------------------------------------------------------------------
2182 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2184 struct kvm_lapic *apic = vcpu->arch.apic;
2186 if (!lapic_in_kernel(vcpu) ||
2187 !apic_lvtt_tscdeadline(apic))
2190 return apic->lapic_timer.tscdeadline;
2193 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2195 struct kvm_lapic *apic = vcpu->arch.apic;
2197 if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) ||
2198 apic_lvtt_period(apic))
2201 hrtimer_cancel(&apic->lapic_timer.timer);
2202 apic->lapic_timer.tscdeadline = data;
2203 start_apic_timer(apic);
2206 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2208 struct kvm_lapic *apic = vcpu->arch.apic;
2210 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
2211 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
2214 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2218 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2220 return (tpr & 0xf0) >> 4;
2223 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2225 u64 old_value = vcpu->arch.apic_base;
2226 struct kvm_lapic *apic = vcpu->arch.apic;
2229 value |= MSR_IA32_APICBASE_BSP;
2231 vcpu->arch.apic_base = value;
2233 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2234 kvm_update_cpuid_runtime(vcpu);
2239 /* update jump label if enable bit changes */
2240 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2241 if (value & MSR_IA32_APICBASE_ENABLE) {
2242 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2243 static_key_slow_dec_deferred(&apic_hw_disabled);
2245 static_key_slow_inc(&apic_hw_disabled.key);
2246 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
2250 if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2251 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2253 if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2254 kvm_x86_ops.set_virtual_apic_mode(vcpu);
2256 apic->base_address = apic->vcpu->arch.apic_base &
2257 MSR_IA32_APICBASE_BASE;
2259 if ((value & MSR_IA32_APICBASE_ENABLE) &&
2260 apic->base_address != APIC_DEFAULT_PHYS_BASE)
2261 pr_warn_once("APIC base relocation is unsupported by KVM");
2264 void kvm_apic_update_apicv(struct kvm_vcpu *vcpu)
2266 struct kvm_lapic *apic = vcpu->arch.apic;
2268 if (vcpu->arch.apicv_active) {
2269 /* irr_pending is always true when apicv is activated. */
2270 apic->irr_pending = true;
2271 apic->isr_count = 1;
2273 apic->irr_pending = (apic_search_irr(apic) != -1);
2274 apic->isr_count = count_vectors(apic->regs + APIC_ISR);
2277 EXPORT_SYMBOL_GPL(kvm_apic_update_apicv);
2279 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2281 struct kvm_lapic *apic = vcpu->arch.apic;
2287 /* Stop the timer in case it's a reset to an active apic */
2288 hrtimer_cancel(&apic->lapic_timer.timer);
2291 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2292 MSR_IA32_APICBASE_ENABLE);
2293 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2295 kvm_apic_set_version(apic->vcpu);
2297 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2298 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2299 apic_update_lvtt(apic);
2300 if (kvm_vcpu_is_reset_bsp(vcpu) &&
2301 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2302 kvm_lapic_set_reg(apic, APIC_LVT0,
2303 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2304 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2306 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
2307 apic_set_spiv(apic, 0xff);
2308 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2309 if (!apic_x2apic_mode(apic))
2310 kvm_apic_set_ldr(apic, 0);
2311 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2312 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2313 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2314 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2315 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2316 for (i = 0; i < 8; i++) {
2317 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2318 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2319 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2321 kvm_apic_update_apicv(vcpu);
2322 apic->highest_isr_cache = -1;
2323 update_divide_count(apic);
2324 atomic_set(&apic->lapic_timer.pending, 0);
2325 if (kvm_vcpu_is_bsp(vcpu))
2326 kvm_lapic_set_base(vcpu,
2327 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2328 vcpu->arch.pv_eoi.msr_val = 0;
2329 apic_update_ppr(apic);
2330 if (vcpu->arch.apicv_active) {
2331 kvm_x86_ops.apicv_post_state_restore(vcpu);
2332 kvm_x86_ops.hwapic_irr_update(vcpu, -1);
2333 kvm_x86_ops.hwapic_isr_update(vcpu, -1);
2336 vcpu->arch.apic_arb_prio = 0;
2337 vcpu->arch.apic_attention = 0;
2339 kvm_recalculate_apic_map(vcpu->kvm);
2343 *----------------------------------------------------------------------
2345 *----------------------------------------------------------------------
2348 static bool lapic_is_periodic(struct kvm_lapic *apic)
2350 return apic_lvtt_period(apic);
2353 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2355 struct kvm_lapic *apic = vcpu->arch.apic;
2357 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2358 return atomic_read(&apic->lapic_timer.pending);
2363 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2365 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2366 int vector, mode, trig_mode;
2368 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2369 vector = reg & APIC_VECTOR_MASK;
2370 mode = reg & APIC_MODE_MASK;
2371 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2372 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2378 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2380 struct kvm_lapic *apic = vcpu->arch.apic;
2383 kvm_apic_local_deliver(apic, APIC_LVT0);
2386 static const struct kvm_io_device_ops apic_mmio_ops = {
2387 .read = apic_mmio_read,
2388 .write = apic_mmio_write,
2391 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2393 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2394 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2396 apic_timer_expired(apic, true);
2398 if (lapic_is_periodic(apic)) {
2399 advance_periodic_target_expiration(apic);
2400 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2401 return HRTIMER_RESTART;
2403 return HRTIMER_NORESTART;
2406 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns)
2408 struct kvm_lapic *apic;
2410 ASSERT(vcpu != NULL);
2412 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT);
2416 vcpu->arch.apic = apic;
2418 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
2420 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2422 goto nomem_free_apic;
2426 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2427 HRTIMER_MODE_ABS_HARD);
2428 apic->lapic_timer.timer.function = apic_timer_fn;
2429 if (timer_advance_ns == -1) {
2430 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
2431 lapic_timer_advance_dynamic = true;
2433 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
2434 lapic_timer_advance_dynamic = false;
2438 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2439 * thinking that APIC state has changed.
2441 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2442 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2443 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2448 vcpu->arch.apic = NULL;
2453 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2455 struct kvm_lapic *apic = vcpu->arch.apic;
2458 if (!kvm_apic_hw_enabled(apic))
2461 __apic_update_ppr(apic, &ppr);
2462 return apic_has_interrupt_for_ppr(apic, ppr);
2465 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2467 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2469 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2471 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2472 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2477 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2479 struct kvm_lapic *apic = vcpu->arch.apic;
2481 if (atomic_read(&apic->lapic_timer.pending) > 0) {
2482 kvm_apic_inject_pending_timer_irqs(apic);
2483 atomic_set(&apic->lapic_timer.pending, 0);
2487 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2489 int vector = kvm_apic_has_interrupt(vcpu);
2490 struct kvm_lapic *apic = vcpu->arch.apic;
2497 * We get here even with APIC virtualization enabled, if doing
2498 * nested virtualization and L1 runs with the "acknowledge interrupt
2499 * on exit" mode. Then we cannot inject the interrupt via RVI,
2500 * because the process would deliver it through the IDT.
2503 apic_clear_irr(vector, apic);
2504 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2506 * For auto-EOI interrupts, there might be another pending
2507 * interrupt above PPR, so check whether to raise another
2510 apic_update_ppr(apic);
2513 * For normal interrupts, PPR has been raised and there cannot
2514 * be a higher-priority pending interrupt---except if there was
2515 * a concurrent interrupt injection, but that would have
2516 * triggered KVM_REQ_EVENT already.
2518 apic_set_isr(vector, apic);
2519 __apic_update_ppr(apic, &ppr);
2525 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2526 struct kvm_lapic_state *s, bool set)
2528 if (apic_x2apic_mode(vcpu->arch.apic)) {
2529 u32 *id = (u32 *)(s->regs + APIC_ID);
2530 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2532 if (vcpu->kvm->arch.x2apic_format) {
2533 if (*id != vcpu->vcpu_id)
2542 /* In x2APIC mode, the LDR is fixed and based on the id */
2544 *ldr = kvm_apic_calc_x2apic_ldr(*id);
2550 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2552 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2555 * Get calculated timer current count for remaining timer period (if
2556 * any) and store it in the returned register set.
2558 __kvm_lapic_set_reg(s->regs, APIC_TMCCT,
2559 __apic_read(vcpu->arch.apic, APIC_TMCCT));
2561 return kvm_apic_state_fixup(vcpu, s, false);
2564 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2566 struct kvm_lapic *apic = vcpu->arch.apic;
2569 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2570 /* set SPIV separately to get count of SW disabled APICs right */
2571 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2573 r = kvm_apic_state_fixup(vcpu, s, true);
2575 kvm_recalculate_apic_map(vcpu->kvm);
2578 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
2580 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
2581 kvm_recalculate_apic_map(vcpu->kvm);
2582 kvm_apic_set_version(vcpu);
2584 apic_update_ppr(apic);
2585 hrtimer_cancel(&apic->lapic_timer.timer);
2586 apic_update_lvtt(apic);
2587 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2588 update_divide_count(apic);
2589 __start_apic_timer(apic, APIC_TMCCT);
2590 kvm_apic_update_apicv(vcpu);
2591 apic->highest_isr_cache = -1;
2592 if (vcpu->arch.apicv_active) {
2593 kvm_x86_ops.apicv_post_state_restore(vcpu);
2594 kvm_x86_ops.hwapic_irr_update(vcpu,
2595 apic_find_highest_irr(apic));
2596 kvm_x86_ops.hwapic_isr_update(vcpu,
2597 apic_find_highest_isr(apic));
2599 kvm_make_request(KVM_REQ_EVENT, vcpu);
2600 if (ioapic_in_kernel(vcpu->kvm))
2601 kvm_rtc_eoi_tracking_restore_one(vcpu);
2603 vcpu->arch.apic_arb_prio = 0;
2608 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2610 struct hrtimer *timer;
2612 if (!lapic_in_kernel(vcpu) ||
2613 kvm_can_post_timer_interrupt(vcpu))
2616 timer = &vcpu->arch.apic->lapic_timer.timer;
2617 if (hrtimer_cancel(timer))
2618 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_HARD);
2622 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2624 * Detect whether guest triggered PV EOI since the
2625 * last entry. If yes, set EOI on guests's behalf.
2626 * Clear PV EOI in guest memory in any case.
2628 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2629 struct kvm_lapic *apic)
2634 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2635 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2637 * KVM_APIC_PV_EOI_PENDING is unset:
2638 * -> host disabled PV EOI.
2639 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2640 * -> host enabled PV EOI, guest did not execute EOI yet.
2641 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2642 * -> host enabled PV EOI, guest executed EOI.
2644 BUG_ON(!pv_eoi_enabled(vcpu));
2645 pending = pv_eoi_get_pending(vcpu);
2647 * Clear pending bit in any case: it will be set again on vmentry.
2648 * While this might not be ideal from performance point of view,
2649 * this makes sure pv eoi is only enabled when we know it's safe.
2651 pv_eoi_clr_pending(vcpu);
2654 vector = apic_set_eoi(apic);
2655 trace_kvm_pv_eoi(apic, vector);
2658 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2662 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2663 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2665 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2668 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2672 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2676 * apic_sync_pv_eoi_to_guest - called before vmentry
2678 * Detect whether it's safe to enable PV EOI and
2681 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2682 struct kvm_lapic *apic)
2684 if (!pv_eoi_enabled(vcpu) ||
2685 /* IRR set or many bits in ISR: could be nested. */
2686 apic->irr_pending ||
2687 /* Cache not set: could be safe but we don't bother. */
2688 apic->highest_isr_cache == -1 ||
2689 /* Need EOI to update ioapic. */
2690 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2692 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2693 * so we need not do anything here.
2698 pv_eoi_set_pending(apic->vcpu);
2701 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2704 int max_irr, max_isr;
2705 struct kvm_lapic *apic = vcpu->arch.apic;
2707 apic_sync_pv_eoi_to_guest(vcpu, apic);
2709 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2712 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2713 max_irr = apic_find_highest_irr(apic);
2716 max_isr = apic_find_highest_isr(apic);
2719 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2721 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2725 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2728 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2729 &vcpu->arch.apic->vapic_cache,
2730 vapic_addr, sizeof(u32)))
2732 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2734 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2737 vcpu->arch.apic->vapic_addr = vapic_addr;
2741 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2743 struct kvm_lapic *apic = vcpu->arch.apic;
2744 u32 reg = (msr - APIC_BASE_MSR) << 4;
2746 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2749 if (reg == APIC_ICR2)
2752 /* if this is ICR write vector before command */
2753 if (reg == APIC_ICR)
2754 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2755 return kvm_lapic_reg_write(apic, reg, (u32)data);
2758 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2760 struct kvm_lapic *apic = vcpu->arch.apic;
2761 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2763 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2766 if (reg == APIC_DFR || reg == APIC_ICR2)
2769 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2771 if (reg == APIC_ICR)
2772 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2774 *data = (((u64)high) << 32) | low;
2779 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2781 struct kvm_lapic *apic = vcpu->arch.apic;
2783 if (!lapic_in_kernel(vcpu))
2786 /* if this is ICR write vector before command */
2787 if (reg == APIC_ICR)
2788 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2789 return kvm_lapic_reg_write(apic, reg, (u32)data);
2792 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2794 struct kvm_lapic *apic = vcpu->arch.apic;
2797 if (!lapic_in_kernel(vcpu))
2800 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2802 if (reg == APIC_ICR)
2803 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2805 *data = (((u64)high) << 32) | low;
2810 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
2812 u64 addr = data & ~KVM_MSR_ENABLED;
2813 struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2814 unsigned long new_len;
2816 if (!IS_ALIGNED(addr, 4))
2819 vcpu->arch.pv_eoi.msr_val = data;
2820 if (!pv_eoi_enabled(vcpu))
2823 if (addr == ghc->gpa && len <= ghc->len)
2828 return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
2831 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2833 struct kvm_lapic *apic = vcpu->arch.apic;
2837 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2841 * INITs are latched while CPU is in specific states
2842 * (SMM, VMX non-root mode, SVM with GIF=0).
2843 * Because a CPU cannot be in these states immediately
2844 * after it has processed an INIT signal (and thus in
2845 * KVM_MP_STATE_INIT_RECEIVED state), just eat SIPIs
2846 * and leave the INIT pending.
2848 if (kvm_vcpu_latch_init(vcpu)) {
2849 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2850 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2851 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2855 pe = xchg(&apic->pending_events, 0);
2856 if (test_bit(KVM_APIC_INIT, &pe)) {
2857 kvm_vcpu_reset(vcpu, true);
2858 if (kvm_vcpu_is_bsp(apic->vcpu))
2859 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2861 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2863 if (test_bit(KVM_APIC_SIPI, &pe) &&
2864 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2865 /* evaluate pending_events before reading the vector */
2867 sipi_vector = apic->sipi_vector;
2868 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2869 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2873 void kvm_lapic_init(void)
2875 /* do not patch jump label more than once per second */
2876 jump_label_rate_limit(&apic_hw_disabled, HZ);
2877 jump_label_rate_limit(&apic_sw_disabled, HZ);
2880 void kvm_lapic_exit(void)
2882 static_key_deferred_flush(&apic_hw_disabled);
2883 static_key_deferred_flush(&apic_sw_disabled);