3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/export.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
49 #define mod_64(x, y) ((x) % (y))
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...) do {} while (0)
60 /* 14 is the version for Xeon and Pentium 8.4.8*/
61 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
62 #define LAPIC_MMIO_LENGTH (1 << 12)
63 /* followed define is not in apicdef.h */
64 #define APIC_SHORT_MASK 0xc0000
65 #define APIC_DEST_NOSHORT 0x0
66 #define APIC_DEST_MASK 0x800
67 #define MAX_APIC_VECTOR 256
68 #define APIC_VECTORS_PER_REG 32
70 #define APIC_BROADCAST 0xFF
71 #define X2APIC_BROADCAST 0xFFFFFFFFul
73 #define LAPIC_TIMER_ADVANCE_ADJUST_DONE 100
74 /* step-by-step approximation to mitigate fluctuation */
75 #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
77 static inline int apic_test_vector(int vec, void *bitmap)
79 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
82 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
84 struct kvm_lapic *apic = vcpu->arch.apic;
86 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
87 apic_test_vector(vector, apic->regs + APIC_IRR);
90 static inline void apic_clear_vector(int vec, void *bitmap)
92 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
95 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
97 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
100 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
102 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
105 struct static_key_deferred apic_hw_disabled __read_mostly;
106 struct static_key_deferred apic_sw_disabled __read_mostly;
108 static inline int apic_enabled(struct kvm_lapic *apic)
110 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
114 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
117 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
118 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
120 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
122 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
125 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
127 return apic->vcpu->vcpu_id;
130 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
131 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
133 case KVM_APIC_MODE_X2APIC: {
134 u32 offset = (dest_id >> 16) * 16;
135 u32 max_apic_id = map->max_apic_id;
137 if (offset <= max_apic_id) {
138 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
140 offset = array_index_nospec(offset, map->max_apic_id + 1);
141 *cluster = &map->phys_map[offset];
142 *mask = dest_id & (0xffff >> (16 - cluster_size));
149 case KVM_APIC_MODE_XAPIC_FLAT:
150 *cluster = map->xapic_flat_map;
151 *mask = dest_id & 0xff;
153 case KVM_APIC_MODE_XAPIC_CLUSTER:
154 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
155 *mask = dest_id & 0xf;
163 static void kvm_apic_map_free(struct rcu_head *rcu)
165 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
170 static void recalculate_apic_map(struct kvm *kvm)
172 struct kvm_apic_map *new, *old = NULL;
173 struct kvm_vcpu *vcpu;
175 u32 max_id = 255; /* enough space for any xAPIC ID */
177 mutex_lock(&kvm->arch.apic_map_lock);
179 kvm_for_each_vcpu(i, vcpu, kvm)
180 if (kvm_apic_present(vcpu))
181 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
183 new = kvzalloc(sizeof(struct kvm_apic_map) +
184 sizeof(struct kvm_lapic *) * ((u64)max_id + 1),
190 new->max_apic_id = max_id;
192 kvm_for_each_vcpu(i, vcpu, kvm) {
193 struct kvm_lapic *apic = vcpu->arch.apic;
194 struct kvm_lapic **cluster;
200 if (!kvm_apic_present(vcpu))
203 xapic_id = kvm_xapic_id(apic);
204 x2apic_id = kvm_x2apic_id(apic);
206 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
207 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
208 x2apic_id <= new->max_apic_id)
209 new->phys_map[x2apic_id] = apic;
211 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
212 * prevent them from masking VCPUs with APIC ID <= 0xff.
214 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
215 new->phys_map[xapic_id] = apic;
217 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
219 if (apic_x2apic_mode(apic)) {
220 new->mode |= KVM_APIC_MODE_X2APIC;
222 ldr = GET_APIC_LOGICAL_ID(ldr);
223 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
224 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
226 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
229 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
233 cluster[ffs(mask) - 1] = apic;
236 old = rcu_dereference_protected(kvm->arch.apic_map,
237 lockdep_is_held(&kvm->arch.apic_map_lock));
238 rcu_assign_pointer(kvm->arch.apic_map, new);
239 mutex_unlock(&kvm->arch.apic_map_lock);
242 call_rcu(&old->rcu, kvm_apic_map_free);
244 kvm_make_scan_ioapic_request(kvm);
247 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
249 bool enabled = val & APIC_SPIV_APIC_ENABLED;
251 kvm_lapic_set_reg(apic, APIC_SPIV, val);
253 if (enabled != apic->sw_enabled) {
254 apic->sw_enabled = enabled;
256 static_key_slow_dec_deferred(&apic_sw_disabled);
258 static_key_slow_inc(&apic_sw_disabled.key);
262 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
264 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
265 recalculate_apic_map(apic->vcpu->kvm);
268 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
270 kvm_lapic_set_reg(apic, APIC_LDR, id);
271 recalculate_apic_map(apic->vcpu->kvm);
274 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
276 return ((id >> 4) << 16) | (1 << (id & 0xf));
279 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
281 u32 ldr = kvm_apic_calc_x2apic_ldr(id);
283 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
285 kvm_lapic_set_reg(apic, APIC_ID, id);
286 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
287 recalculate_apic_map(apic->vcpu->kvm);
290 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
292 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
295 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
297 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
300 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
302 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
305 static inline int apic_lvtt_period(struct kvm_lapic *apic)
307 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
310 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
312 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
315 static inline int apic_lvt_nmi_mode(u32 lvt_val)
317 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
320 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
322 struct kvm_lapic *apic = vcpu->arch.apic;
323 struct kvm_cpuid_entry2 *feat;
324 u32 v = APIC_VERSION;
326 if (!lapic_in_kernel(vcpu))
330 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
331 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
332 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
333 * version first and level-triggered interrupts never get EOIed in
336 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
337 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
338 !ioapic_in_kernel(vcpu->kvm))
339 v |= APIC_LVR_DIRECTED_EOI;
340 kvm_lapic_set_reg(apic, APIC_LVR, v);
343 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
344 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
345 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
346 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
347 LINT_MASK, LINT_MASK, /* LVT0-1 */
348 LVT_MASK /* LVTERR */
351 static int find_highest_vector(void *bitmap)
356 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
357 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
358 reg = bitmap + REG_POS(vec);
360 return __fls(*reg) + vec;
366 static u8 count_vectors(void *bitmap)
372 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
373 reg = bitmap + REG_POS(vec);
374 count += hweight32(*reg);
380 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
383 u32 pir_val, irr_val, prev_irr_val;
386 max_updated_irr = -1;
389 for (i = vec = 0; i <= 7; i++, vec += 32) {
390 pir_val = READ_ONCE(pir[i]);
391 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
393 prev_irr_val = irr_val;
394 irr_val |= xchg(&pir[i], 0);
395 *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
396 if (prev_irr_val != irr_val) {
398 __fls(irr_val ^ prev_irr_val) + vec;
402 *max_irr = __fls(irr_val) + vec;
405 return ((max_updated_irr != -1) &&
406 (max_updated_irr == *max_irr));
408 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
410 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
412 struct kvm_lapic *apic = vcpu->arch.apic;
414 return __kvm_apic_update_irr(pir, apic->regs, max_irr);
416 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
418 static inline int apic_search_irr(struct kvm_lapic *apic)
420 return find_highest_vector(apic->regs + APIC_IRR);
423 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
428 * Note that irr_pending is just a hint. It will be always
429 * true with virtual interrupt delivery enabled.
431 if (!apic->irr_pending)
434 result = apic_search_irr(apic);
435 ASSERT(result == -1 || result >= 16);
440 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
442 struct kvm_vcpu *vcpu;
446 if (unlikely(vcpu->arch.apicv_active)) {
447 /* need to update RVI */
448 apic_clear_vector(vec, apic->regs + APIC_IRR);
449 kvm_x86_ops->hwapic_irr_update(vcpu,
450 apic_find_highest_irr(apic));
452 apic->irr_pending = false;
453 apic_clear_vector(vec, apic->regs + APIC_IRR);
454 if (apic_search_irr(apic) != -1)
455 apic->irr_pending = true;
459 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
461 struct kvm_vcpu *vcpu;
463 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
469 * With APIC virtualization enabled, all caching is disabled
470 * because the processor can modify ISR under the hood. Instead
473 if (unlikely(vcpu->arch.apicv_active))
474 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
477 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
479 * ISR (in service register) bit is set when injecting an interrupt.
480 * The highest vector is injected. Thus the latest bit set matches
481 * the highest bit in ISR.
483 apic->highest_isr_cache = vec;
487 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
492 * Note that isr_count is always 1, and highest_isr_cache
493 * is always -1, with APIC virtualization enabled.
495 if (!apic->isr_count)
497 if (likely(apic->highest_isr_cache != -1))
498 return apic->highest_isr_cache;
500 result = find_highest_vector(apic->regs + APIC_ISR);
501 ASSERT(result == -1 || result >= 16);
506 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
508 struct kvm_vcpu *vcpu;
509 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
515 * We do get here for APIC virtualization enabled if the guest
516 * uses the Hyper-V APIC enlightenment. In this case we may need
517 * to trigger a new interrupt delivery by writing the SVI field;
518 * on the other hand isr_count and highest_isr_cache are unused
519 * and must be left alone.
521 if (unlikely(vcpu->arch.apicv_active))
522 kvm_x86_ops->hwapic_isr_update(vcpu,
523 apic_find_highest_isr(apic));
526 BUG_ON(apic->isr_count < 0);
527 apic->highest_isr_cache = -1;
531 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
533 /* This may race with setting of irr in __apic_accept_irq() and
534 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
535 * will cause vmexit immediately and the value will be recalculated
536 * on the next vmentry.
538 return apic_find_highest_irr(vcpu->arch.apic);
540 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
542 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
543 int vector, int level, int trig_mode,
544 struct dest_map *dest_map);
546 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
547 struct dest_map *dest_map)
549 struct kvm_lapic *apic = vcpu->arch.apic;
551 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
552 irq->level, irq->trig_mode, dest_map);
555 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
556 unsigned long ipi_bitmap_high, u32 min,
557 unsigned long icr, int op_64_bit)
560 struct kvm_apic_map *map;
561 struct kvm_vcpu *vcpu;
562 struct kvm_lapic_irq irq = {0};
563 int cluster_size = op_64_bit ? 64 : 32;
566 irq.vector = icr & APIC_VECTOR_MASK;
567 irq.delivery_mode = icr & APIC_MODE_MASK;
568 irq.level = (icr & APIC_INT_ASSERT) != 0;
569 irq.trig_mode = icr & APIC_INT_LEVELTRIG;
571 if (icr & APIC_DEST_MASK)
573 if (icr & APIC_SHORT_MASK)
577 map = rcu_dereference(kvm->arch.apic_map);
579 if (unlikely(!map)) {
584 if (min > map->max_apic_id)
586 /* Bits above cluster_size are masked in the caller. */
587 for_each_set_bit(i, &ipi_bitmap_low,
588 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
589 if (map->phys_map[min + i]) {
590 vcpu = map->phys_map[min + i]->vcpu;
591 count += kvm_apic_set_irq(vcpu, &irq, NULL);
597 if (min > map->max_apic_id)
600 for_each_set_bit(i, &ipi_bitmap_high,
601 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
602 if (map->phys_map[min + i]) {
603 vcpu = map->phys_map[min + i]->vcpu;
604 count += kvm_apic_set_irq(vcpu, &irq, NULL);
613 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
616 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
620 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
623 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
627 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
629 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
632 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
635 if (pv_eoi_get_user(vcpu, &val) < 0)
636 apic_debug("Can't read EOI MSR value: 0x%llx\n",
637 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
641 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
643 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
644 apic_debug("Can't set EOI MSR value: 0x%llx\n",
645 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
648 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
651 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
653 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
654 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
655 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
658 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
661 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
664 if (apic->vcpu->arch.apicv_active)
665 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
667 highest_irr = apic_find_highest_irr(apic);
668 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
673 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
675 u32 tpr, isrv, ppr, old_ppr;
678 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
679 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
680 isr = apic_find_highest_isr(apic);
681 isrv = (isr != -1) ? isr : 0;
683 if ((tpr & 0xf0) >= (isrv & 0xf0))
688 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
689 apic, ppr, isr, isrv);
693 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
695 return ppr < old_ppr;
698 static void apic_update_ppr(struct kvm_lapic *apic)
702 if (__apic_update_ppr(apic, &ppr) &&
703 apic_has_interrupt_for_ppr(apic, ppr) != -1)
704 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
707 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
709 apic_update_ppr(vcpu->arch.apic);
711 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
713 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
715 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
716 apic_update_ppr(apic);
719 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
721 return mda == (apic_x2apic_mode(apic) ?
722 X2APIC_BROADCAST : APIC_BROADCAST);
725 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
727 if (kvm_apic_broadcast(apic, mda))
730 if (apic_x2apic_mode(apic))
731 return mda == kvm_x2apic_id(apic);
734 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
735 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
736 * this allows unique addressing of VCPUs with APIC ID over 0xff.
737 * The 0xff condition is needed because writeable xAPIC ID.
739 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
742 return mda == kvm_xapic_id(apic);
745 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
749 if (kvm_apic_broadcast(apic, mda))
752 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
754 if (apic_x2apic_mode(apic))
755 return ((logical_id >> 16) == (mda >> 16))
756 && (logical_id & mda & 0xffff) != 0;
758 logical_id = GET_APIC_LOGICAL_ID(logical_id);
760 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
762 return (logical_id & mda) != 0;
763 case APIC_DFR_CLUSTER:
764 return ((logical_id >> 4) == (mda >> 4))
765 && (logical_id & mda & 0xf) != 0;
767 apic_debug("Bad DFR vcpu %d: %08x\n",
768 apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
773 /* The KVM local APIC implementation has two quirks:
775 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
776 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
777 * KVM doesn't do that aliasing.
779 * - in-kernel IOAPIC messages have to be delivered directly to
780 * x2APIC, because the kernel does not support interrupt remapping.
781 * In order to support broadcast without interrupt remapping, x2APIC
782 * rewrites the destination of non-IPI messages from APIC_BROADCAST
783 * to X2APIC_BROADCAST.
785 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
786 * important when userspace wants to use x2APIC-format MSIs, because
787 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
789 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
790 struct kvm_lapic *source, struct kvm_lapic *target)
792 bool ipi = source != NULL;
794 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
795 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
796 return X2APIC_BROADCAST;
801 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
802 int short_hand, unsigned int dest, int dest_mode)
804 struct kvm_lapic *target = vcpu->arch.apic;
805 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
807 apic_debug("target %p, source %p, dest 0x%x, "
808 "dest_mode 0x%x, short_hand 0x%x\n",
809 target, source, dest, dest_mode, short_hand);
812 switch (short_hand) {
813 case APIC_DEST_NOSHORT:
814 if (dest_mode == APIC_DEST_PHYSICAL)
815 return kvm_apic_match_physical_addr(target, mda);
817 return kvm_apic_match_logical_addr(target, mda);
819 return target == source;
820 case APIC_DEST_ALLINC:
822 case APIC_DEST_ALLBUT:
823 return target != source;
825 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
830 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
832 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
833 const unsigned long *bitmap, u32 bitmap_size)
838 mod = vector % dest_vcpus;
840 for (i = 0; i <= mod; i++) {
841 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
842 BUG_ON(idx == bitmap_size);
848 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
850 if (!kvm->arch.disabled_lapic_found) {
851 kvm->arch.disabled_lapic_found = true;
853 "Disabled LAPIC found during irq injection\n");
857 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
858 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
860 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
861 if ((irq->dest_id == APIC_BROADCAST &&
862 map->mode != KVM_APIC_MODE_X2APIC))
864 if (irq->dest_id == X2APIC_BROADCAST)
867 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
868 if (irq->dest_id == (x2apic_ipi ?
869 X2APIC_BROADCAST : APIC_BROADCAST))
876 /* Return true if the interrupt can be handled by using *bitmap as index mask
877 * for valid destinations in *dst array.
878 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
879 * Note: we may have zero kvm_lapic destinations when we return true, which
880 * means that the interrupt should be dropped. In this case, *bitmap would be
881 * zero and *dst undefined.
883 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
884 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
885 struct kvm_apic_map *map, struct kvm_lapic ***dst,
886 unsigned long *bitmap)
890 if (irq->shorthand == APIC_DEST_SELF && src) {
894 } else if (irq->shorthand)
897 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
900 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
901 if (irq->dest_id > map->max_apic_id) {
904 u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1);
905 *dst = &map->phys_map[dest_id];
912 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
916 if (!kvm_lowest_prio_delivery(irq))
919 if (!kvm_vector_hashing_enabled()) {
921 for_each_set_bit(i, bitmap, 16) {
926 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
927 (*dst)[lowest]->vcpu) < 0)
934 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
937 if (!(*dst)[lowest]) {
938 kvm_apic_disabled_lapic_found(kvm);
944 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
949 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
950 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
952 struct kvm_apic_map *map;
953 unsigned long bitmap;
954 struct kvm_lapic **dst = NULL;
960 if (irq->shorthand == APIC_DEST_SELF) {
961 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
966 map = rcu_dereference(kvm->arch.apic_map);
968 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
971 for_each_set_bit(i, &bitmap, 16) {
974 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
983 * This routine tries to handler interrupts in posted mode, here is how
984 * it deals with different cases:
985 * - For single-destination interrupts, handle it in posted mode
986 * - Else if vector hashing is enabled and it is a lowest-priority
987 * interrupt, handle it in posted mode and use the following mechanism
988 * to find the destinaiton vCPU.
989 * 1. For lowest-priority interrupts, store all the possible
990 * destination vCPUs in an array.
991 * 2. Use "guest vector % max number of destination vCPUs" to find
992 * the right destination vCPU in the array for the lowest-priority
994 * - Otherwise, use remapped mode to inject the interrupt.
996 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
997 struct kvm_vcpu **dest_vcpu)
999 struct kvm_apic_map *map;
1000 unsigned long bitmap;
1001 struct kvm_lapic **dst = NULL;
1008 map = rcu_dereference(kvm->arch.apic_map);
1010 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1011 hweight16(bitmap) == 1) {
1012 unsigned long i = find_first_bit(&bitmap, 16);
1015 *dest_vcpu = dst[i]->vcpu;
1025 * Add a pending IRQ into lapic.
1026 * Return 1 if successfully added and 0 if discarded.
1028 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1029 int vector, int level, int trig_mode,
1030 struct dest_map *dest_map)
1033 struct kvm_vcpu *vcpu = apic->vcpu;
1035 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1037 switch (delivery_mode) {
1038 case APIC_DM_LOWEST:
1039 vcpu->arch.apic_arb_prio++;
1042 if (unlikely(trig_mode && !level))
1045 /* FIXME add logic for vcpu on reset */
1046 if (unlikely(!apic_enabled(apic)))
1052 __set_bit(vcpu->vcpu_id, dest_map->map);
1053 dest_map->vectors[vcpu->vcpu_id] = vector;
1056 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1058 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
1060 apic_clear_vector(vector, apic->regs + APIC_TMR);
1063 if (vcpu->arch.apicv_active)
1064 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
1066 kvm_lapic_set_irr(vector, apic);
1068 kvm_make_request(KVM_REQ_EVENT, vcpu);
1069 kvm_vcpu_kick(vcpu);
1075 vcpu->arch.pv.pv_unhalted = 1;
1076 kvm_make_request(KVM_REQ_EVENT, vcpu);
1077 kvm_vcpu_kick(vcpu);
1082 kvm_make_request(KVM_REQ_SMI, vcpu);
1083 kvm_vcpu_kick(vcpu);
1088 kvm_inject_nmi(vcpu);
1089 kvm_vcpu_kick(vcpu);
1093 if (!trig_mode || level) {
1095 /* assumes that there are only KVM_APIC_INIT/SIPI */
1096 apic->pending_events = (1UL << KVM_APIC_INIT);
1097 /* make sure pending_events is visible before sending
1100 kvm_make_request(KVM_REQ_EVENT, vcpu);
1101 kvm_vcpu_kick(vcpu);
1103 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1108 case APIC_DM_STARTUP:
1109 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1110 vcpu->vcpu_id, vector);
1112 apic->sipi_vector = vector;
1113 /* make sure sipi_vector is visible for the receiver */
1115 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1116 kvm_make_request(KVM_REQ_EVENT, vcpu);
1117 kvm_vcpu_kick(vcpu);
1120 case APIC_DM_EXTINT:
1122 * Should only be called by kvm_apic_local_deliver() with LVT0,
1123 * before NMI watchdog was enabled. Already handled by
1124 * kvm_apic_accept_pic_intr().
1129 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1136 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1138 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1141 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1143 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1146 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1150 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1151 if (!kvm_ioapic_handles_vector(apic, vector))
1154 /* Request a KVM exit to inform the userspace IOAPIC. */
1155 if (irqchip_split(apic->vcpu->kvm)) {
1156 apic->vcpu->arch.pending_ioapic_eoi = vector;
1157 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1161 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1162 trigger_mode = IOAPIC_LEVEL_TRIG;
1164 trigger_mode = IOAPIC_EDGE_TRIG;
1166 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1169 static int apic_set_eoi(struct kvm_lapic *apic)
1171 int vector = apic_find_highest_isr(apic);
1173 trace_kvm_eoi(apic, vector);
1176 * Not every write EOI will has corresponding ISR,
1177 * one example is when Kernel check timer on setup_IO_APIC
1182 apic_clear_isr(vector, apic);
1183 apic_update_ppr(apic);
1185 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1186 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1188 kvm_ioapic_send_eoi(apic, vector);
1189 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1194 * this interface assumes a trap-like exit, which has already finished
1195 * desired side effect including vISR and vPPR update.
1197 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1199 struct kvm_lapic *apic = vcpu->arch.apic;
1201 trace_kvm_eoi(apic, vector);
1203 kvm_ioapic_send_eoi(apic, vector);
1204 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1206 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1208 static void apic_send_ipi(struct kvm_lapic *apic)
1210 u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1211 u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1212 struct kvm_lapic_irq irq;
1214 irq.vector = icr_low & APIC_VECTOR_MASK;
1215 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1216 irq.dest_mode = icr_low & APIC_DEST_MASK;
1217 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1218 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1219 irq.shorthand = icr_low & APIC_SHORT_MASK;
1220 irq.msi_redir_hint = false;
1221 if (apic_x2apic_mode(apic))
1222 irq.dest_id = icr_high;
1224 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1226 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1228 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1229 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1230 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1231 "msi_redir_hint 0x%x\n",
1232 icr_high, icr_low, irq.shorthand, irq.dest_id,
1233 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1234 irq.vector, irq.msi_redir_hint);
1236 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1239 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1241 ktime_t remaining, now;
1245 ASSERT(apic != NULL);
1247 /* if initial count is 0, current count should also be 0 */
1248 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1249 apic->lapic_timer.period == 0)
1253 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1254 if (ktime_to_ns(remaining) < 0)
1257 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1258 tmcct = div64_u64(ns,
1259 (APIC_BUS_CYCLE_NS * apic->divide_count));
1264 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1266 struct kvm_vcpu *vcpu = apic->vcpu;
1267 struct kvm_run *run = vcpu->run;
1269 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1270 run->tpr_access.rip = kvm_rip_read(vcpu);
1271 run->tpr_access.is_write = write;
1274 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1276 if (apic->vcpu->arch.tpr_access_reporting)
1277 __report_tpr_access(apic, write);
1280 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1284 if (offset >= LAPIC_MMIO_LENGTH)
1289 apic_debug("Access APIC ARBPRI register which is for P6\n");
1292 case APIC_TMCCT: /* Timer CCR */
1293 if (apic_lvtt_tscdeadline(apic))
1296 val = apic_get_tmcct(apic);
1299 apic_update_ppr(apic);
1300 val = kvm_lapic_get_reg(apic, offset);
1303 report_tpr_access(apic, false);
1306 val = kvm_lapic_get_reg(apic, offset);
1313 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1315 return container_of(dev, struct kvm_lapic, dev);
1318 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1321 unsigned char alignment = offset & 0xf;
1323 /* this bitmask has a bit cleared for each reserved register */
1324 static const u64 rmask = 0x43ff01ffffffe70cULL;
1326 if ((alignment + len) > 4) {
1327 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1332 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1333 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1338 result = __apic_read(apic, offset & ~0xf);
1340 trace_kvm_apic_read(offset, result);
1346 memcpy(data, (char *)&result + alignment, len);
1349 printk(KERN_ERR "Local APIC read with len = %x, "
1350 "should be 1,2, or 4 instead\n", len);
1355 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1357 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1359 return addr >= apic->base_address &&
1360 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1363 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1364 gpa_t address, int len, void *data)
1366 struct kvm_lapic *apic = to_lapic(this);
1367 u32 offset = address - apic->base_address;
1369 if (!apic_mmio_in_range(apic, address))
1372 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1373 if (!kvm_check_has_quirk(vcpu->kvm,
1374 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1377 memset(data, 0xff, len);
1381 kvm_lapic_reg_read(apic, offset, len, data);
1386 static void update_divide_count(struct kvm_lapic *apic)
1388 u32 tmp1, tmp2, tdcr;
1390 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1392 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1393 apic->divide_count = 0x1 << (tmp2 & 0x7);
1395 apic_debug("timer divide count is 0x%x\n",
1396 apic->divide_count);
1399 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1402 * Do not allow the guest to program periodic timers with small
1403 * interval, since the hrtimers are not throttled by the host
1406 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1407 s64 min_period = min_timer_period_us * 1000LL;
1409 if (apic->lapic_timer.period < min_period) {
1410 pr_info_ratelimited(
1411 "kvm: vcpu %i: requested %lld ns "
1412 "lapic timer period limited to %lld ns\n",
1413 apic->vcpu->vcpu_id,
1414 apic->lapic_timer.period, min_period);
1415 apic->lapic_timer.period = min_period;
1420 static void apic_update_lvtt(struct kvm_lapic *apic)
1422 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1423 apic->lapic_timer.timer_mode_mask;
1425 if (apic->lapic_timer.timer_mode != timer_mode) {
1426 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1427 APIC_LVT_TIMER_TSCDEADLINE)) {
1428 hrtimer_cancel(&apic->lapic_timer.timer);
1429 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1430 apic->lapic_timer.period = 0;
1431 apic->lapic_timer.tscdeadline = 0;
1433 apic->lapic_timer.timer_mode = timer_mode;
1434 limit_periodic_timer_frequency(apic);
1438 static void apic_timer_expired(struct kvm_lapic *apic)
1440 struct kvm_vcpu *vcpu = apic->vcpu;
1441 struct swait_queue_head *q = &vcpu->wq;
1442 struct kvm_timer *ktimer = &apic->lapic_timer;
1444 if (atomic_read(&apic->lapic_timer.pending))
1447 atomic_inc(&apic->lapic_timer.pending);
1448 kvm_set_pending_timer(vcpu);
1451 * For x86, the atomic_inc() is serialized, thus
1452 * using swait_active() is safe.
1454 if (swait_active(q))
1457 if (apic_lvtt_tscdeadline(apic))
1458 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1462 * On APICv, this test will cause a busy wait
1463 * during a higher-priority task.
1466 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1468 struct kvm_lapic *apic = vcpu->arch.apic;
1469 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1471 if (kvm_apic_hw_enabled(apic)) {
1472 int vec = reg & APIC_VECTOR_MASK;
1473 void *bitmap = apic->regs + APIC_ISR;
1475 if (vcpu->arch.apicv_active)
1476 bitmap = apic->regs + APIC_IRR;
1478 if (apic_test_vector(vec, bitmap))
1484 static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles)
1486 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;
1489 * If the guest TSC is running at a different ratio than the host, then
1490 * convert the delay to nanoseconds to achieve an accurate delay. Note
1491 * that __delay() uses delay_tsc whenever the hardware has TSC, thus
1492 * always for VMX enabled hardware.
1494 if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) {
1495 __delay(min(guest_cycles,
1496 nsec_to_cycles(vcpu, timer_advance_ns)));
1498 u64 delay_ns = guest_cycles * 1000000ULL;
1499 do_div(delay_ns, vcpu->arch.virtual_tsc_khz);
1500 ndelay(min_t(u32, delay_ns, timer_advance_ns));
1504 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1506 struct kvm_lapic *apic = vcpu->arch.apic;
1507 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
1508 u64 guest_tsc, tsc_deadline, ns;
1510 if (apic->lapic_timer.expired_tscdeadline == 0)
1513 if (!lapic_timer_int_injected(vcpu))
1516 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1517 apic->lapic_timer.expired_tscdeadline = 0;
1518 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1519 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1521 if (guest_tsc < tsc_deadline)
1522 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
1524 if (!apic->lapic_timer.timer_advance_adjust_done) {
1526 if (guest_tsc < tsc_deadline) {
1527 ns = (tsc_deadline - guest_tsc) * 1000000ULL;
1528 do_div(ns, vcpu->arch.virtual_tsc_khz);
1529 timer_advance_ns -= min((u32)ns,
1530 timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP);
1533 ns = (guest_tsc - tsc_deadline) * 1000000ULL;
1534 do_div(ns, vcpu->arch.virtual_tsc_khz);
1535 timer_advance_ns += min((u32)ns,
1536 timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP);
1538 if (abs(guest_tsc - tsc_deadline) < LAPIC_TIMER_ADVANCE_ADJUST_DONE)
1539 apic->lapic_timer.timer_advance_adjust_done = true;
1540 if (unlikely(timer_advance_ns > 5000)) {
1541 timer_advance_ns = 0;
1542 apic->lapic_timer.timer_advance_adjust_done = true;
1544 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
1548 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1550 struct kvm_timer *ktimer = &apic->lapic_timer;
1551 u64 guest_tsc, tscdeadline = ktimer->tscdeadline;
1554 struct kvm_vcpu *vcpu = apic->vcpu;
1555 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1556 unsigned long flags;
1559 if (unlikely(!tscdeadline || !this_tsc_khz))
1562 local_irq_save(flags);
1565 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1567 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1568 do_div(ns, this_tsc_khz);
1570 if (likely(tscdeadline > guest_tsc) &&
1571 likely(ns > apic->lapic_timer.timer_advance_ns)) {
1572 expire = ktime_add_ns(now, ns);
1573 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns);
1574 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_PINNED);
1576 apic_timer_expired(apic);
1578 local_irq_restore(flags);
1581 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1583 ktime_t now, remaining;
1584 u64 ns_remaining_old, ns_remaining_new;
1586 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1587 * APIC_BUS_CYCLE_NS * apic->divide_count;
1588 limit_periodic_timer_frequency(apic);
1591 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1592 if (ktime_to_ns(remaining) < 0)
1595 ns_remaining_old = ktime_to_ns(remaining);
1596 ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1597 apic->divide_count, old_divisor);
1599 apic->lapic_timer.tscdeadline +=
1600 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1601 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1602 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1605 static bool set_target_expiration(struct kvm_lapic *apic)
1611 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1612 * APIC_BUS_CYCLE_NS * apic->divide_count;
1614 if (!apic->lapic_timer.period) {
1615 apic->lapic_timer.tscdeadline = 0;
1619 limit_periodic_timer_frequency(apic);
1621 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1623 "timer initial count 0x%x, period %lldns, "
1624 "expire @ 0x%016" PRIx64 ".\n", __func__,
1625 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1626 kvm_lapic_get_reg(apic, APIC_TMICT),
1627 apic->lapic_timer.period,
1628 ktime_to_ns(ktime_add_ns(now,
1629 apic->lapic_timer.period)));
1631 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1632 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1633 apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1638 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1640 ktime_t now = ktime_get();
1645 * Synchronize both deadlines to the same time source or
1646 * differences in the periods (caused by differences in the
1647 * underlying clocks or numerical approximation errors) will
1648 * cause the two to drift apart over time as the errors
1651 apic->lapic_timer.target_expiration =
1652 ktime_add_ns(apic->lapic_timer.target_expiration,
1653 apic->lapic_timer.period);
1654 delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1655 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1656 nsec_to_cycles(apic->vcpu, delta);
1659 static void start_sw_period(struct kvm_lapic *apic)
1661 if (!apic->lapic_timer.period)
1664 if (ktime_after(ktime_get(),
1665 apic->lapic_timer.target_expiration)) {
1666 apic_timer_expired(apic);
1668 if (apic_lvtt_oneshot(apic))
1671 advance_periodic_target_expiration(apic);
1674 hrtimer_start(&apic->lapic_timer.timer,
1675 apic->lapic_timer.target_expiration,
1676 HRTIMER_MODE_ABS_PINNED);
1679 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1681 if (!lapic_in_kernel(vcpu))
1684 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1686 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1688 static void cancel_hv_timer(struct kvm_lapic *apic)
1690 WARN_ON(preemptible());
1691 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1692 kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1693 apic->lapic_timer.hv_timer_in_use = false;
1696 static bool start_hv_timer(struct kvm_lapic *apic)
1698 struct kvm_timer *ktimer = &apic->lapic_timer;
1701 WARN_ON(preemptible());
1702 if (!kvm_x86_ops->set_hv_timer)
1705 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1708 if (!ktimer->tscdeadline)
1711 r = kvm_x86_ops->set_hv_timer(apic->vcpu, ktimer->tscdeadline);
1715 ktimer->hv_timer_in_use = true;
1716 hrtimer_cancel(&ktimer->timer);
1719 * Also recheck ktimer->pending, in case the sw timer triggered in
1720 * the window. For periodic timer, leave the hv timer running for
1721 * simplicity, and the deadline will be recomputed on the next vmexit.
1723 if (!apic_lvtt_period(apic) && (r || atomic_read(&ktimer->pending))) {
1725 apic_timer_expired(apic);
1729 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, true);
1733 static void start_sw_timer(struct kvm_lapic *apic)
1735 struct kvm_timer *ktimer = &apic->lapic_timer;
1737 WARN_ON(preemptible());
1738 if (apic->lapic_timer.hv_timer_in_use)
1739 cancel_hv_timer(apic);
1740 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1743 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1744 start_sw_period(apic);
1745 else if (apic_lvtt_tscdeadline(apic))
1746 start_sw_tscdeadline(apic);
1747 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1750 static void restart_apic_timer(struct kvm_lapic *apic)
1753 if (!start_hv_timer(apic))
1754 start_sw_timer(apic);
1758 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1760 struct kvm_lapic *apic = vcpu->arch.apic;
1763 /* If the preempt notifier has already run, it also called apic_timer_expired */
1764 if (!apic->lapic_timer.hv_timer_in_use)
1766 WARN_ON(swait_active(&vcpu->wq));
1767 cancel_hv_timer(apic);
1768 apic_timer_expired(apic);
1770 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1771 advance_periodic_target_expiration(apic);
1772 restart_apic_timer(apic);
1777 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1779 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1781 restart_apic_timer(vcpu->arch.apic);
1783 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1785 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1787 struct kvm_lapic *apic = vcpu->arch.apic;
1790 /* Possibly the TSC deadline timer is not enabled yet */
1791 if (apic->lapic_timer.hv_timer_in_use)
1792 start_sw_timer(apic);
1795 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1797 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1799 struct kvm_lapic *apic = vcpu->arch.apic;
1801 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1802 restart_apic_timer(apic);
1805 static void start_apic_timer(struct kvm_lapic *apic)
1807 atomic_set(&apic->lapic_timer.pending, 0);
1809 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1810 && !set_target_expiration(apic))
1813 restart_apic_timer(apic);
1816 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1818 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1820 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1821 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1822 if (lvt0_in_nmi_mode) {
1823 apic_debug("Receive NMI setting on APIC_LVT0 "
1824 "for cpu %d\n", apic->vcpu->vcpu_id);
1825 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1827 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1831 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1835 trace_kvm_apic_write(reg, val);
1838 case APIC_ID: /* Local APIC ID */
1839 if (!apic_x2apic_mode(apic))
1840 kvm_apic_set_xapic_id(apic, val >> 24);
1846 report_tpr_access(apic, true);
1847 apic_set_tpr(apic, val & 0xff);
1855 if (!apic_x2apic_mode(apic))
1856 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1862 if (!apic_x2apic_mode(apic)) {
1863 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1864 recalculate_apic_map(apic->vcpu->kvm);
1871 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1872 mask |= APIC_SPIV_DIRECTED_EOI;
1873 apic_set_spiv(apic, val & mask);
1874 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1878 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1879 lvt_val = kvm_lapic_get_reg(apic,
1880 APIC_LVTT + 0x10 * i);
1881 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1882 lvt_val | APIC_LVT_MASKED);
1884 apic_update_lvtt(apic);
1885 atomic_set(&apic->lapic_timer.pending, 0);
1891 /* No delay here, so we always clear the pending bit */
1892 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1893 apic_send_ipi(apic);
1897 if (!apic_x2apic_mode(apic))
1899 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1903 apic_manage_nmi_watchdog(apic, val);
1909 /* TODO: Check vector */
1910 if (!kvm_apic_sw_enabled(apic))
1911 val |= APIC_LVT_MASKED;
1913 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1914 kvm_lapic_set_reg(apic, reg, val);
1919 if (!kvm_apic_sw_enabled(apic))
1920 val |= APIC_LVT_MASKED;
1921 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1922 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1923 apic_update_lvtt(apic);
1927 if (apic_lvtt_tscdeadline(apic))
1930 hrtimer_cancel(&apic->lapic_timer.timer);
1931 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1932 start_apic_timer(apic);
1936 uint32_t old_divisor = apic->divide_count;
1939 apic_debug("KVM_WRITE:TDCR %x\n", val);
1940 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1941 update_divide_count(apic);
1942 if (apic->divide_count != old_divisor &&
1943 apic->lapic_timer.period) {
1944 hrtimer_cancel(&apic->lapic_timer.timer);
1945 update_target_expiration(apic, old_divisor);
1946 restart_apic_timer(apic);
1951 if (apic_x2apic_mode(apic) && val != 0) {
1952 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1958 if (apic_x2apic_mode(apic)) {
1959 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1968 apic_debug("Local APIC Write to read-only register %x\n", reg);
1971 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1973 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1974 gpa_t address, int len, const void *data)
1976 struct kvm_lapic *apic = to_lapic(this);
1977 unsigned int offset = address - apic->base_address;
1980 if (!apic_mmio_in_range(apic, address))
1983 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1984 if (!kvm_check_has_quirk(vcpu->kvm,
1985 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1992 * APIC register must be aligned on 128-bits boundary.
1993 * 32/64/128 bits registers must be accessed thru 32 bits.
1996 if (len != 4 || (offset & 0xf)) {
1997 /* Don't shout loud, $infamous_os would cause only noise. */
1998 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
2004 /* too common printing */
2005 if (offset != APIC_EOI)
2006 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
2007 "0x%x\n", __func__, offset, len, val);
2009 kvm_lapic_reg_write(apic, offset & 0xff0, val);
2014 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
2016 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
2018 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
2020 /* emulate APIC access in a trap manner */
2021 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
2025 /* hw has done the conditional check and inst decode */
2028 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
2030 /* TODO: optimize to just emulate side effect w/o one more write */
2031 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
2033 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2035 void kvm_free_lapic(struct kvm_vcpu *vcpu)
2037 struct kvm_lapic *apic = vcpu->arch.apic;
2039 if (!vcpu->arch.apic)
2042 hrtimer_cancel(&apic->lapic_timer.timer);
2044 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2045 static_key_slow_dec_deferred(&apic_hw_disabled);
2047 if (!apic->sw_enabled)
2048 static_key_slow_dec_deferred(&apic_sw_disabled);
2051 free_page((unsigned long)apic->regs);
2057 *----------------------------------------------------------------------
2059 *----------------------------------------------------------------------
2061 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2063 struct kvm_lapic *apic = vcpu->arch.apic;
2065 if (!lapic_in_kernel(vcpu) ||
2066 !apic_lvtt_tscdeadline(apic))
2069 return apic->lapic_timer.tscdeadline;
2072 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2074 struct kvm_lapic *apic = vcpu->arch.apic;
2076 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
2077 apic_lvtt_period(apic))
2080 hrtimer_cancel(&apic->lapic_timer.timer);
2081 apic->lapic_timer.tscdeadline = data;
2082 start_apic_timer(apic);
2085 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2087 struct kvm_lapic *apic = vcpu->arch.apic;
2089 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
2090 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
2093 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2097 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2099 return (tpr & 0xf0) >> 4;
2102 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2104 u64 old_value = vcpu->arch.apic_base;
2105 struct kvm_lapic *apic = vcpu->arch.apic;
2108 value |= MSR_IA32_APICBASE_BSP;
2110 vcpu->arch.apic_base = value;
2112 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2113 kvm_update_cpuid(vcpu);
2118 /* update jump label if enable bit changes */
2119 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2120 if (value & MSR_IA32_APICBASE_ENABLE) {
2121 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2122 static_key_slow_dec_deferred(&apic_hw_disabled);
2124 static_key_slow_inc(&apic_hw_disabled.key);
2125 recalculate_apic_map(vcpu->kvm);
2129 if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2130 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2132 if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2133 kvm_x86_ops->set_virtual_apic_mode(vcpu);
2135 apic->base_address = apic->vcpu->arch.apic_base &
2136 MSR_IA32_APICBASE_BASE;
2138 if ((value & MSR_IA32_APICBASE_ENABLE) &&
2139 apic->base_address != APIC_DEFAULT_PHYS_BASE)
2140 pr_warn_once("APIC base relocation is unsupported by KVM");
2142 /* with FSB delivery interrupt, we can restart APIC functionality */
2143 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
2144 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
2148 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2150 struct kvm_lapic *apic = vcpu->arch.apic;
2156 apic_debug("%s\n", __func__);
2158 /* Stop the timer in case it's a reset to an active apic */
2159 hrtimer_cancel(&apic->lapic_timer.timer);
2162 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2163 MSR_IA32_APICBASE_ENABLE);
2164 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2166 kvm_apic_set_version(apic->vcpu);
2168 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2169 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2170 apic_update_lvtt(apic);
2171 if (kvm_vcpu_is_reset_bsp(vcpu) &&
2172 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2173 kvm_lapic_set_reg(apic, APIC_LVT0,
2174 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2175 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2177 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
2178 apic_set_spiv(apic, 0xff);
2179 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2180 if (!apic_x2apic_mode(apic))
2181 kvm_apic_set_ldr(apic, 0);
2182 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2183 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2184 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2185 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2186 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2187 for (i = 0; i < 8; i++) {
2188 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2189 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2190 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2192 apic->irr_pending = vcpu->arch.apicv_active;
2193 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
2194 apic->highest_isr_cache = -1;
2195 update_divide_count(apic);
2196 atomic_set(&apic->lapic_timer.pending, 0);
2197 if (kvm_vcpu_is_bsp(vcpu))
2198 kvm_lapic_set_base(vcpu,
2199 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2200 vcpu->arch.pv_eoi.msr_val = 0;
2201 apic_update_ppr(apic);
2202 if (vcpu->arch.apicv_active) {
2203 kvm_x86_ops->apicv_post_state_restore(vcpu);
2204 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2205 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2208 vcpu->arch.apic_arb_prio = 0;
2209 vcpu->arch.apic_attention = 0;
2211 apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
2212 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
2213 vcpu, kvm_lapic_get_reg(apic, APIC_ID),
2214 vcpu->arch.apic_base, apic->base_address);
2218 *----------------------------------------------------------------------
2220 *----------------------------------------------------------------------
2223 static bool lapic_is_periodic(struct kvm_lapic *apic)
2225 return apic_lvtt_period(apic);
2228 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2230 struct kvm_lapic *apic = vcpu->arch.apic;
2232 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2233 return atomic_read(&apic->lapic_timer.pending);
2238 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2240 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2241 int vector, mode, trig_mode;
2243 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2244 vector = reg & APIC_VECTOR_MASK;
2245 mode = reg & APIC_MODE_MASK;
2246 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2247 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2253 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2255 struct kvm_lapic *apic = vcpu->arch.apic;
2258 kvm_apic_local_deliver(apic, APIC_LVT0);
2261 static const struct kvm_io_device_ops apic_mmio_ops = {
2262 .read = apic_mmio_read,
2263 .write = apic_mmio_write,
2266 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2268 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2269 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2271 apic_timer_expired(apic);
2273 if (lapic_is_periodic(apic)) {
2274 advance_periodic_target_expiration(apic);
2275 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2276 return HRTIMER_RESTART;
2278 return HRTIMER_NORESTART;
2281 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns)
2283 struct kvm_lapic *apic;
2285 ASSERT(vcpu != NULL);
2286 apic_debug("apic_init %d\n", vcpu->vcpu_id);
2288 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT);
2292 vcpu->arch.apic = apic;
2294 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
2296 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2298 goto nomem_free_apic;
2302 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2303 HRTIMER_MODE_ABS_PINNED);
2304 apic->lapic_timer.timer.function = apic_timer_fn;
2305 if (timer_advance_ns == -1) {
2306 apic->lapic_timer.timer_advance_ns = 1000;
2307 apic->lapic_timer.timer_advance_adjust_done = false;
2309 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
2310 apic->lapic_timer.timer_advance_adjust_done = true;
2315 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2316 * thinking that APIC satet has changed.
2318 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2319 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2320 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2329 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2331 struct kvm_lapic *apic = vcpu->arch.apic;
2334 if (!apic_enabled(apic))
2337 __apic_update_ppr(apic, &ppr);
2338 return apic_has_interrupt_for_ppr(apic, ppr);
2341 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2343 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2346 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2348 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2349 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2354 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2356 struct kvm_lapic *apic = vcpu->arch.apic;
2358 if (atomic_read(&apic->lapic_timer.pending) > 0) {
2359 kvm_apic_local_deliver(apic, APIC_LVTT);
2360 if (apic_lvtt_tscdeadline(apic))
2361 apic->lapic_timer.tscdeadline = 0;
2362 if (apic_lvtt_oneshot(apic)) {
2363 apic->lapic_timer.tscdeadline = 0;
2364 apic->lapic_timer.target_expiration = 0;
2366 atomic_set(&apic->lapic_timer.pending, 0);
2370 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2372 int vector = kvm_apic_has_interrupt(vcpu);
2373 struct kvm_lapic *apic = vcpu->arch.apic;
2380 * We get here even with APIC virtualization enabled, if doing
2381 * nested virtualization and L1 runs with the "acknowledge interrupt
2382 * on exit" mode. Then we cannot inject the interrupt via RVI,
2383 * because the process would deliver it through the IDT.
2386 apic_clear_irr(vector, apic);
2387 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2389 * For auto-EOI interrupts, there might be another pending
2390 * interrupt above PPR, so check whether to raise another
2393 apic_update_ppr(apic);
2396 * For normal interrupts, PPR has been raised and there cannot
2397 * be a higher-priority pending interrupt---except if there was
2398 * a concurrent interrupt injection, but that would have
2399 * triggered KVM_REQ_EVENT already.
2401 apic_set_isr(vector, apic);
2402 __apic_update_ppr(apic, &ppr);
2408 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2409 struct kvm_lapic_state *s, bool set)
2411 if (apic_x2apic_mode(vcpu->arch.apic)) {
2412 u32 *id = (u32 *)(s->regs + APIC_ID);
2413 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2415 if (vcpu->kvm->arch.x2apic_format) {
2416 if (*id != vcpu->vcpu_id)
2425 /* In x2APIC mode, the LDR is fixed and based on the id */
2427 *ldr = kvm_apic_calc_x2apic_ldr(*id);
2433 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2435 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2436 return kvm_apic_state_fixup(vcpu, s, false);
2439 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2441 struct kvm_lapic *apic = vcpu->arch.apic;
2445 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2446 /* set SPIV separately to get count of SW disabled APICs right */
2447 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2449 r = kvm_apic_state_fixup(vcpu, s, true);
2452 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
2454 recalculate_apic_map(vcpu->kvm);
2455 kvm_apic_set_version(vcpu);
2457 apic_update_ppr(apic);
2458 hrtimer_cancel(&apic->lapic_timer.timer);
2459 apic_update_lvtt(apic);
2460 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2461 update_divide_count(apic);
2462 start_apic_timer(apic);
2463 apic->irr_pending = true;
2464 apic->isr_count = vcpu->arch.apicv_active ?
2465 1 : count_vectors(apic->regs + APIC_ISR);
2466 apic->highest_isr_cache = -1;
2467 if (vcpu->arch.apicv_active) {
2468 kvm_x86_ops->apicv_post_state_restore(vcpu);
2469 kvm_x86_ops->hwapic_irr_update(vcpu,
2470 apic_find_highest_irr(apic));
2471 kvm_x86_ops->hwapic_isr_update(vcpu,
2472 apic_find_highest_isr(apic));
2474 kvm_make_request(KVM_REQ_EVENT, vcpu);
2475 if (ioapic_in_kernel(vcpu->kvm))
2476 kvm_rtc_eoi_tracking_restore_one(vcpu);
2478 vcpu->arch.apic_arb_prio = 0;
2483 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2485 struct hrtimer *timer;
2487 if (!lapic_in_kernel(vcpu))
2490 timer = &vcpu->arch.apic->lapic_timer.timer;
2491 if (hrtimer_cancel(timer))
2492 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2496 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2498 * Detect whether guest triggered PV EOI since the
2499 * last entry. If yes, set EOI on guests's behalf.
2500 * Clear PV EOI in guest memory in any case.
2502 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2503 struct kvm_lapic *apic)
2508 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2509 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2511 * KVM_APIC_PV_EOI_PENDING is unset:
2512 * -> host disabled PV EOI.
2513 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2514 * -> host enabled PV EOI, guest did not execute EOI yet.
2515 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2516 * -> host enabled PV EOI, guest executed EOI.
2518 BUG_ON(!pv_eoi_enabled(vcpu));
2519 pending = pv_eoi_get_pending(vcpu);
2521 * Clear pending bit in any case: it will be set again on vmentry.
2522 * While this might not be ideal from performance point of view,
2523 * this makes sure pv eoi is only enabled when we know it's safe.
2525 pv_eoi_clr_pending(vcpu);
2528 vector = apic_set_eoi(apic);
2529 trace_kvm_pv_eoi(apic, vector);
2532 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2536 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2537 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2539 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2542 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2546 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2550 * apic_sync_pv_eoi_to_guest - called before vmentry
2552 * Detect whether it's safe to enable PV EOI and
2555 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2556 struct kvm_lapic *apic)
2558 if (!pv_eoi_enabled(vcpu) ||
2559 /* IRR set or many bits in ISR: could be nested. */
2560 apic->irr_pending ||
2561 /* Cache not set: could be safe but we don't bother. */
2562 apic->highest_isr_cache == -1 ||
2563 /* Need EOI to update ioapic. */
2564 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2566 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2567 * so we need not do anything here.
2572 pv_eoi_set_pending(apic->vcpu);
2575 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2578 int max_irr, max_isr;
2579 struct kvm_lapic *apic = vcpu->arch.apic;
2581 apic_sync_pv_eoi_to_guest(vcpu, apic);
2583 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2586 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2587 max_irr = apic_find_highest_irr(apic);
2590 max_isr = apic_find_highest_isr(apic);
2593 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2595 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2599 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2602 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2603 &vcpu->arch.apic->vapic_cache,
2604 vapic_addr, sizeof(u32)))
2606 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2608 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2611 vcpu->arch.apic->vapic_addr = vapic_addr;
2615 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2617 struct kvm_lapic *apic = vcpu->arch.apic;
2618 u32 reg = (msr - APIC_BASE_MSR) << 4;
2620 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2623 if (reg == APIC_ICR2)
2626 /* if this is ICR write vector before command */
2627 if (reg == APIC_ICR)
2628 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2629 return kvm_lapic_reg_write(apic, reg, (u32)data);
2632 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2634 struct kvm_lapic *apic = vcpu->arch.apic;
2635 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2637 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2640 if (reg == APIC_DFR || reg == APIC_ICR2) {
2641 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2646 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2648 if (reg == APIC_ICR)
2649 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2651 *data = (((u64)high) << 32) | low;
2656 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2658 struct kvm_lapic *apic = vcpu->arch.apic;
2660 if (!lapic_in_kernel(vcpu))
2663 /* if this is ICR write vector before command */
2664 if (reg == APIC_ICR)
2665 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2666 return kvm_lapic_reg_write(apic, reg, (u32)data);
2669 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2671 struct kvm_lapic *apic = vcpu->arch.apic;
2674 if (!lapic_in_kernel(vcpu))
2677 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2679 if (reg == APIC_ICR)
2680 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2682 *data = (((u64)high) << 32) | low;
2687 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
2689 u64 addr = data & ~KVM_MSR_ENABLED;
2690 struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2691 unsigned long new_len;
2693 if (!IS_ALIGNED(addr, 4))
2696 vcpu->arch.pv_eoi.msr_val = data;
2697 if (!pv_eoi_enabled(vcpu))
2700 if (addr == ghc->gpa && len <= ghc->len)
2705 return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
2708 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2710 struct kvm_lapic *apic = vcpu->arch.apic;
2714 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2718 * INITs are latched while in SMM. Because an SMM CPU cannot
2719 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2720 * and delay processing of INIT until the next RSM.
2723 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2724 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2725 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2729 pe = xchg(&apic->pending_events, 0);
2730 if (test_bit(KVM_APIC_INIT, &pe)) {
2731 kvm_vcpu_reset(vcpu, true);
2732 if (kvm_vcpu_is_bsp(apic->vcpu))
2733 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2735 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2737 if (test_bit(KVM_APIC_SIPI, &pe) &&
2738 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2739 /* evaluate pending_events before reading the vector */
2741 sipi_vector = apic->sipi_vector;
2742 apic_debug("vcpu %d received sipi with vector # %x\n",
2743 vcpu->vcpu_id, sipi_vector);
2744 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2745 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2749 void kvm_lapic_init(void)
2751 /* do not patch jump label more than once per second */
2752 jump_label_rate_limit(&apic_hw_disabled, HZ);
2753 jump_label_rate_limit(&apic_sw_disabled, HZ);
2756 void kvm_lapic_exit(void)
2758 static_key_deferred_flush(&apic_hw_disabled);
2759 static_key_deferred_flush(&apic_sw_disabled);