1 // SPDX-License-Identifier: GPL-2.0-only
4 * Local APIC virtualization
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2007 Novell
8 * Copyright (C) 2007 Intel
9 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
12 * Dor Laor <dor.laor@qumranet.com>
13 * Gregory Haskins <ghaskins@novell.com>
14 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
16 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
19 #include <linux/kvm_host.h>
20 #include <linux/kvm.h>
22 #include <linux/highmem.h>
23 #include <linux/smp.h>
24 #include <linux/hrtimer.h>
26 #include <linux/export.h>
27 #include <linux/math64.h>
28 #include <linux/slab.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/delay.h>
35 #include <linux/atomic.h>
36 #include <linux/jump_label.h>
37 #include "kvm_cache_regs.h"
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #define mod_64(x, y) ((x) % (y))
55 /* 14 is the version for Xeon and Pentium 8.4.8*/
56 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
57 #define LAPIC_MMIO_LENGTH (1 << 12)
58 /* followed define is not in apicdef.h */
59 #define APIC_SHORT_MASK 0xc0000
60 #define APIC_DEST_NOSHORT 0x0
61 #define APIC_DEST_MASK 0x800
62 #define MAX_APIC_VECTOR 256
63 #define APIC_VECTORS_PER_REG 32
65 #define APIC_BROADCAST 0xFF
66 #define X2APIC_BROADCAST 0xFFFFFFFFul
68 #define LAPIC_TIMER_ADVANCE_ADJUST_DONE 100
69 #define LAPIC_TIMER_ADVANCE_ADJUST_INIT 1000
70 /* step-by-step approximation to mitigate fluctuation */
71 #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
73 static inline int apic_test_vector(int vec, void *bitmap)
75 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
78 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
80 struct kvm_lapic *apic = vcpu->arch.apic;
82 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
83 apic_test_vector(vector, apic->regs + APIC_IRR);
86 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
88 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
91 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
93 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
96 struct static_key_deferred apic_hw_disabled __read_mostly;
97 struct static_key_deferred apic_sw_disabled __read_mostly;
99 static inline int apic_enabled(struct kvm_lapic *apic)
101 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
105 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
108 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
109 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
111 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
113 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
116 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
118 return apic->vcpu->vcpu_id;
121 bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu)
123 return pi_inject_timer && kvm_vcpu_apicv_active(vcpu);
125 EXPORT_SYMBOL_GPL(kvm_can_post_timer_interrupt);
127 static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu)
129 return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE;
132 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
133 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
135 case KVM_APIC_MODE_X2APIC: {
136 u32 offset = (dest_id >> 16) * 16;
137 u32 max_apic_id = map->max_apic_id;
139 if (offset <= max_apic_id) {
140 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
142 offset = array_index_nospec(offset, map->max_apic_id + 1);
143 *cluster = &map->phys_map[offset];
144 *mask = dest_id & (0xffff >> (16 - cluster_size));
151 case KVM_APIC_MODE_XAPIC_FLAT:
152 *cluster = map->xapic_flat_map;
153 *mask = dest_id & 0xff;
155 case KVM_APIC_MODE_XAPIC_CLUSTER:
156 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
157 *mask = dest_id & 0xf;
165 static void kvm_apic_map_free(struct rcu_head *rcu)
167 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
172 static void recalculate_apic_map(struct kvm *kvm)
174 struct kvm_apic_map *new, *old = NULL;
175 struct kvm_vcpu *vcpu;
177 u32 max_id = 255; /* enough space for any xAPIC ID */
179 mutex_lock(&kvm->arch.apic_map_lock);
181 kvm_for_each_vcpu(i, vcpu, kvm)
182 if (kvm_apic_present(vcpu))
183 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
185 new = kvzalloc(sizeof(struct kvm_apic_map) +
186 sizeof(struct kvm_lapic *) * ((u64)max_id + 1),
192 new->max_apic_id = max_id;
194 kvm_for_each_vcpu(i, vcpu, kvm) {
195 struct kvm_lapic *apic = vcpu->arch.apic;
196 struct kvm_lapic **cluster;
202 if (!kvm_apic_present(vcpu))
205 xapic_id = kvm_xapic_id(apic);
206 x2apic_id = kvm_x2apic_id(apic);
208 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
209 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
210 x2apic_id <= new->max_apic_id)
211 new->phys_map[x2apic_id] = apic;
213 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
214 * prevent them from masking VCPUs with APIC ID <= 0xff.
216 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
217 new->phys_map[xapic_id] = apic;
219 if (!kvm_apic_sw_enabled(apic))
222 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
224 if (apic_x2apic_mode(apic)) {
225 new->mode |= KVM_APIC_MODE_X2APIC;
227 ldr = GET_APIC_LOGICAL_ID(ldr);
228 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
229 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
231 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
234 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
238 cluster[ffs(mask) - 1] = apic;
241 old = rcu_dereference_protected(kvm->arch.apic_map,
242 lockdep_is_held(&kvm->arch.apic_map_lock));
243 rcu_assign_pointer(kvm->arch.apic_map, new);
244 mutex_unlock(&kvm->arch.apic_map_lock);
247 call_rcu(&old->rcu, kvm_apic_map_free);
249 kvm_make_scan_ioapic_request(kvm);
252 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
254 bool enabled = val & APIC_SPIV_APIC_ENABLED;
256 kvm_lapic_set_reg(apic, APIC_SPIV, val);
258 if (enabled != apic->sw_enabled) {
259 apic->sw_enabled = enabled;
261 static_key_slow_dec_deferred(&apic_sw_disabled);
263 static_key_slow_inc(&apic_sw_disabled.key);
265 recalculate_apic_map(apic->vcpu->kvm);
269 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
271 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
272 recalculate_apic_map(apic->vcpu->kvm);
275 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
277 kvm_lapic_set_reg(apic, APIC_LDR, id);
278 recalculate_apic_map(apic->vcpu->kvm);
281 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
283 return ((id >> 4) << 16) | (1 << (id & 0xf));
286 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
288 u32 ldr = kvm_apic_calc_x2apic_ldr(id);
290 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
292 kvm_lapic_set_reg(apic, APIC_ID, id);
293 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
294 recalculate_apic_map(apic->vcpu->kvm);
297 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
299 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
302 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
304 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
307 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
309 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
312 static inline int apic_lvtt_period(struct kvm_lapic *apic)
314 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
317 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
319 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
322 static inline int apic_lvt_nmi_mode(u32 lvt_val)
324 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
327 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
329 struct kvm_lapic *apic = vcpu->arch.apic;
330 struct kvm_cpuid_entry2 *feat;
331 u32 v = APIC_VERSION;
333 if (!lapic_in_kernel(vcpu))
337 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
338 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
339 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
340 * version first and level-triggered interrupts never get EOIed in
343 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
344 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
345 !ioapic_in_kernel(vcpu->kvm))
346 v |= APIC_LVR_DIRECTED_EOI;
347 kvm_lapic_set_reg(apic, APIC_LVR, v);
350 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
351 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
352 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
353 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
354 LINT_MASK, LINT_MASK, /* LVT0-1 */
355 LVT_MASK /* LVTERR */
358 static int find_highest_vector(void *bitmap)
363 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
364 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
365 reg = bitmap + REG_POS(vec);
367 return __fls(*reg) + vec;
373 static u8 count_vectors(void *bitmap)
379 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
380 reg = bitmap + REG_POS(vec);
381 count += hweight32(*reg);
387 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
390 u32 pir_val, irr_val, prev_irr_val;
393 max_updated_irr = -1;
396 for (i = vec = 0; i <= 7; i++, vec += 32) {
397 pir_val = READ_ONCE(pir[i]);
398 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
400 prev_irr_val = irr_val;
401 irr_val |= xchg(&pir[i], 0);
402 *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
403 if (prev_irr_val != irr_val) {
405 __fls(irr_val ^ prev_irr_val) + vec;
409 *max_irr = __fls(irr_val) + vec;
412 return ((max_updated_irr != -1) &&
413 (max_updated_irr == *max_irr));
415 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
417 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
419 struct kvm_lapic *apic = vcpu->arch.apic;
421 return __kvm_apic_update_irr(pir, apic->regs, max_irr);
423 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
425 static inline int apic_search_irr(struct kvm_lapic *apic)
427 return find_highest_vector(apic->regs + APIC_IRR);
430 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
435 * Note that irr_pending is just a hint. It will be always
436 * true with virtual interrupt delivery enabled.
438 if (!apic->irr_pending)
441 result = apic_search_irr(apic);
442 ASSERT(result == -1 || result >= 16);
447 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
449 struct kvm_vcpu *vcpu;
453 if (unlikely(vcpu->arch.apicv_active)) {
454 /* need to update RVI */
455 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
456 kvm_x86_ops->hwapic_irr_update(vcpu,
457 apic_find_highest_irr(apic));
459 apic->irr_pending = false;
460 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
461 if (apic_search_irr(apic) != -1)
462 apic->irr_pending = true;
466 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
468 struct kvm_vcpu *vcpu;
470 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
476 * With APIC virtualization enabled, all caching is disabled
477 * because the processor can modify ISR under the hood. Instead
480 if (unlikely(vcpu->arch.apicv_active))
481 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
484 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
486 * ISR (in service register) bit is set when injecting an interrupt.
487 * The highest vector is injected. Thus the latest bit set matches
488 * the highest bit in ISR.
490 apic->highest_isr_cache = vec;
494 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
499 * Note that isr_count is always 1, and highest_isr_cache
500 * is always -1, with APIC virtualization enabled.
502 if (!apic->isr_count)
504 if (likely(apic->highest_isr_cache != -1))
505 return apic->highest_isr_cache;
507 result = find_highest_vector(apic->regs + APIC_ISR);
508 ASSERT(result == -1 || result >= 16);
513 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
515 struct kvm_vcpu *vcpu;
516 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
522 * We do get here for APIC virtualization enabled if the guest
523 * uses the Hyper-V APIC enlightenment. In this case we may need
524 * to trigger a new interrupt delivery by writing the SVI field;
525 * on the other hand isr_count and highest_isr_cache are unused
526 * and must be left alone.
528 if (unlikely(vcpu->arch.apicv_active))
529 kvm_x86_ops->hwapic_isr_update(vcpu,
530 apic_find_highest_isr(apic));
533 BUG_ON(apic->isr_count < 0);
534 apic->highest_isr_cache = -1;
538 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
540 /* This may race with setting of irr in __apic_accept_irq() and
541 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
542 * will cause vmexit immediately and the value will be recalculated
543 * on the next vmentry.
545 return apic_find_highest_irr(vcpu->arch.apic);
547 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
549 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
550 int vector, int level, int trig_mode,
551 struct dest_map *dest_map);
553 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
554 struct dest_map *dest_map)
556 struct kvm_lapic *apic = vcpu->arch.apic;
558 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
559 irq->level, irq->trig_mode, dest_map);
562 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
563 unsigned long ipi_bitmap_high, u32 min,
564 unsigned long icr, int op_64_bit)
567 struct kvm_apic_map *map;
568 struct kvm_vcpu *vcpu;
569 struct kvm_lapic_irq irq = {0};
570 int cluster_size = op_64_bit ? 64 : 32;
573 irq.vector = icr & APIC_VECTOR_MASK;
574 irq.delivery_mode = icr & APIC_MODE_MASK;
575 irq.level = (icr & APIC_INT_ASSERT) != 0;
576 irq.trig_mode = icr & APIC_INT_LEVELTRIG;
578 if (icr & APIC_DEST_MASK)
580 if (icr & APIC_SHORT_MASK)
584 map = rcu_dereference(kvm->arch.apic_map);
586 if (unlikely(!map)) {
591 if (min > map->max_apic_id)
593 /* Bits above cluster_size are masked in the caller. */
594 for_each_set_bit(i, &ipi_bitmap_low,
595 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
596 if (map->phys_map[min + i]) {
597 vcpu = map->phys_map[min + i]->vcpu;
598 count += kvm_apic_set_irq(vcpu, &irq, NULL);
604 if (min > map->max_apic_id)
607 for_each_set_bit(i, &ipi_bitmap_high,
608 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
609 if (map->phys_map[min + i]) {
610 vcpu = map->phys_map[min + i]->vcpu;
611 count += kvm_apic_set_irq(vcpu, &irq, NULL);
620 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
623 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
627 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
630 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
634 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
636 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
639 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
642 if (pv_eoi_get_user(vcpu, &val) < 0)
643 printk(KERN_WARNING "Can't read EOI MSR value: 0x%llx\n",
644 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
648 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
650 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
651 printk(KERN_WARNING "Can't set EOI MSR value: 0x%llx\n",
652 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
655 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
658 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
660 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
661 printk(KERN_WARNING "Can't clear EOI MSR value: 0x%llx\n",
662 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
665 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
668 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
671 if (apic->vcpu->arch.apicv_active)
672 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
674 highest_irr = apic_find_highest_irr(apic);
675 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
680 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
682 u32 tpr, isrv, ppr, old_ppr;
685 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
686 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
687 isr = apic_find_highest_isr(apic);
688 isrv = (isr != -1) ? isr : 0;
690 if ((tpr & 0xf0) >= (isrv & 0xf0))
697 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
699 return ppr < old_ppr;
702 static void apic_update_ppr(struct kvm_lapic *apic)
706 if (__apic_update_ppr(apic, &ppr) &&
707 apic_has_interrupt_for_ppr(apic, ppr) != -1)
708 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
711 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
713 apic_update_ppr(vcpu->arch.apic);
715 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
717 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
719 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
720 apic_update_ppr(apic);
723 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
725 return mda == (apic_x2apic_mode(apic) ?
726 X2APIC_BROADCAST : APIC_BROADCAST);
729 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
731 if (kvm_apic_broadcast(apic, mda))
734 if (apic_x2apic_mode(apic))
735 return mda == kvm_x2apic_id(apic);
738 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
739 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
740 * this allows unique addressing of VCPUs with APIC ID over 0xff.
741 * The 0xff condition is needed because writeable xAPIC ID.
743 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
746 return mda == kvm_xapic_id(apic);
749 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
753 if (kvm_apic_broadcast(apic, mda))
756 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
758 if (apic_x2apic_mode(apic))
759 return ((logical_id >> 16) == (mda >> 16))
760 && (logical_id & mda & 0xffff) != 0;
762 logical_id = GET_APIC_LOGICAL_ID(logical_id);
764 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
766 return (logical_id & mda) != 0;
767 case APIC_DFR_CLUSTER:
768 return ((logical_id >> 4) == (mda >> 4))
769 && (logical_id & mda & 0xf) != 0;
775 /* The KVM local APIC implementation has two quirks:
777 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
778 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
779 * KVM doesn't do that aliasing.
781 * - in-kernel IOAPIC messages have to be delivered directly to
782 * x2APIC, because the kernel does not support interrupt remapping.
783 * In order to support broadcast without interrupt remapping, x2APIC
784 * rewrites the destination of non-IPI messages from APIC_BROADCAST
785 * to X2APIC_BROADCAST.
787 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
788 * important when userspace wants to use x2APIC-format MSIs, because
789 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
791 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
792 struct kvm_lapic *source, struct kvm_lapic *target)
794 bool ipi = source != NULL;
796 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
797 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
798 return X2APIC_BROADCAST;
803 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
804 int short_hand, unsigned int dest, int dest_mode)
806 struct kvm_lapic *target = vcpu->arch.apic;
807 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
810 switch (short_hand) {
811 case APIC_DEST_NOSHORT:
812 if (dest_mode == APIC_DEST_PHYSICAL)
813 return kvm_apic_match_physical_addr(target, mda);
815 return kvm_apic_match_logical_addr(target, mda);
817 return target == source;
818 case APIC_DEST_ALLINC:
820 case APIC_DEST_ALLBUT:
821 return target != source;
826 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
828 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
829 const unsigned long *bitmap, u32 bitmap_size)
834 mod = vector % dest_vcpus;
836 for (i = 0; i <= mod; i++) {
837 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
838 BUG_ON(idx == bitmap_size);
844 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
846 if (!kvm->arch.disabled_lapic_found) {
847 kvm->arch.disabled_lapic_found = true;
849 "Disabled LAPIC found during irq injection\n");
853 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
854 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
856 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
857 if ((irq->dest_id == APIC_BROADCAST &&
858 map->mode != KVM_APIC_MODE_X2APIC))
860 if (irq->dest_id == X2APIC_BROADCAST)
863 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
864 if (irq->dest_id == (x2apic_ipi ?
865 X2APIC_BROADCAST : APIC_BROADCAST))
872 /* Return true if the interrupt can be handled by using *bitmap as index mask
873 * for valid destinations in *dst array.
874 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
875 * Note: we may have zero kvm_lapic destinations when we return true, which
876 * means that the interrupt should be dropped. In this case, *bitmap would be
877 * zero and *dst undefined.
879 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
880 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
881 struct kvm_apic_map *map, struct kvm_lapic ***dst,
882 unsigned long *bitmap)
886 if (irq->shorthand == APIC_DEST_SELF && src) {
890 } else if (irq->shorthand)
893 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
896 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
897 if (irq->dest_id > map->max_apic_id) {
900 u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1);
901 *dst = &map->phys_map[dest_id];
908 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
912 if (!kvm_lowest_prio_delivery(irq))
915 if (!kvm_vector_hashing_enabled()) {
917 for_each_set_bit(i, bitmap, 16) {
922 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
923 (*dst)[lowest]->vcpu) < 0)
930 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
933 if (!(*dst)[lowest]) {
934 kvm_apic_disabled_lapic_found(kvm);
940 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
945 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
946 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
948 struct kvm_apic_map *map;
949 unsigned long bitmap;
950 struct kvm_lapic **dst = NULL;
956 if (irq->shorthand == APIC_DEST_SELF) {
957 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
962 map = rcu_dereference(kvm->arch.apic_map);
964 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
967 for_each_set_bit(i, &bitmap, 16) {
970 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
979 * This routine tries to handler interrupts in posted mode, here is how
980 * it deals with different cases:
981 * - For single-destination interrupts, handle it in posted mode
982 * - Else if vector hashing is enabled and it is a lowest-priority
983 * interrupt, handle it in posted mode and use the following mechanism
984 * to find the destinaiton vCPU.
985 * 1. For lowest-priority interrupts, store all the possible
986 * destination vCPUs in an array.
987 * 2. Use "guest vector % max number of destination vCPUs" to find
988 * the right destination vCPU in the array for the lowest-priority
990 * - Otherwise, use remapped mode to inject the interrupt.
992 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
993 struct kvm_vcpu **dest_vcpu)
995 struct kvm_apic_map *map;
996 unsigned long bitmap;
997 struct kvm_lapic **dst = NULL;
1004 map = rcu_dereference(kvm->arch.apic_map);
1006 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1007 hweight16(bitmap) == 1) {
1008 unsigned long i = find_first_bit(&bitmap, 16);
1011 *dest_vcpu = dst[i]->vcpu;
1021 * Add a pending IRQ into lapic.
1022 * Return 1 if successfully added and 0 if discarded.
1024 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1025 int vector, int level, int trig_mode,
1026 struct dest_map *dest_map)
1029 struct kvm_vcpu *vcpu = apic->vcpu;
1031 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1033 switch (delivery_mode) {
1034 case APIC_DM_LOWEST:
1035 vcpu->arch.apic_arb_prio++;
1038 if (unlikely(trig_mode && !level))
1041 /* FIXME add logic for vcpu on reset */
1042 if (unlikely(!apic_enabled(apic)))
1048 __set_bit(vcpu->vcpu_id, dest_map->map);
1049 dest_map->vectors[vcpu->vcpu_id] = vector;
1052 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1054 kvm_lapic_set_vector(vector,
1055 apic->regs + APIC_TMR);
1057 kvm_lapic_clear_vector(vector,
1058 apic->regs + APIC_TMR);
1061 if (vcpu->arch.apicv_active)
1062 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
1064 kvm_lapic_set_irr(vector, apic);
1066 kvm_make_request(KVM_REQ_EVENT, vcpu);
1067 kvm_vcpu_kick(vcpu);
1073 vcpu->arch.pv.pv_unhalted = 1;
1074 kvm_make_request(KVM_REQ_EVENT, vcpu);
1075 kvm_vcpu_kick(vcpu);
1080 kvm_make_request(KVM_REQ_SMI, vcpu);
1081 kvm_vcpu_kick(vcpu);
1086 kvm_inject_nmi(vcpu);
1087 kvm_vcpu_kick(vcpu);
1091 if (!trig_mode || level) {
1093 /* assumes that there are only KVM_APIC_INIT/SIPI */
1094 apic->pending_events = (1UL << KVM_APIC_INIT);
1095 /* make sure pending_events is visible before sending
1098 kvm_make_request(KVM_REQ_EVENT, vcpu);
1099 kvm_vcpu_kick(vcpu);
1103 case APIC_DM_STARTUP:
1105 apic->sipi_vector = vector;
1106 /* make sure sipi_vector is visible for the receiver */
1108 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1109 kvm_make_request(KVM_REQ_EVENT, vcpu);
1110 kvm_vcpu_kick(vcpu);
1113 case APIC_DM_EXTINT:
1115 * Should only be called by kvm_apic_local_deliver() with LVT0,
1116 * before NMI watchdog was enabled. Already handled by
1117 * kvm_apic_accept_pic_intr().
1122 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1129 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1131 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1134 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1136 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1139 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1143 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1144 if (!kvm_ioapic_handles_vector(apic, vector))
1147 /* Request a KVM exit to inform the userspace IOAPIC. */
1148 if (irqchip_split(apic->vcpu->kvm)) {
1149 apic->vcpu->arch.pending_ioapic_eoi = vector;
1150 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1154 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1155 trigger_mode = IOAPIC_LEVEL_TRIG;
1157 trigger_mode = IOAPIC_EDGE_TRIG;
1159 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1162 static int apic_set_eoi(struct kvm_lapic *apic)
1164 int vector = apic_find_highest_isr(apic);
1166 trace_kvm_eoi(apic, vector);
1169 * Not every write EOI will has corresponding ISR,
1170 * one example is when Kernel check timer on setup_IO_APIC
1175 apic_clear_isr(vector, apic);
1176 apic_update_ppr(apic);
1178 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1179 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1181 kvm_ioapic_send_eoi(apic, vector);
1182 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1187 * this interface assumes a trap-like exit, which has already finished
1188 * desired side effect including vISR and vPPR update.
1190 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1192 struct kvm_lapic *apic = vcpu->arch.apic;
1194 trace_kvm_eoi(apic, vector);
1196 kvm_ioapic_send_eoi(apic, vector);
1197 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1199 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1201 static void apic_send_ipi(struct kvm_lapic *apic)
1203 u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1204 u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1205 struct kvm_lapic_irq irq;
1207 irq.vector = icr_low & APIC_VECTOR_MASK;
1208 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1209 irq.dest_mode = icr_low & APIC_DEST_MASK;
1210 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1211 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1212 irq.shorthand = icr_low & APIC_SHORT_MASK;
1213 irq.msi_redir_hint = false;
1214 if (apic_x2apic_mode(apic))
1215 irq.dest_id = icr_high;
1217 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1219 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1221 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1224 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1226 ktime_t remaining, now;
1230 ASSERT(apic != NULL);
1232 /* if initial count is 0, current count should also be 0 */
1233 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1234 apic->lapic_timer.period == 0)
1238 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1239 if (ktime_to_ns(remaining) < 0)
1242 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1243 tmcct = div64_u64(ns,
1244 (APIC_BUS_CYCLE_NS * apic->divide_count));
1249 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1251 struct kvm_vcpu *vcpu = apic->vcpu;
1252 struct kvm_run *run = vcpu->run;
1254 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1255 run->tpr_access.rip = kvm_rip_read(vcpu);
1256 run->tpr_access.is_write = write;
1259 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1261 if (apic->vcpu->arch.tpr_access_reporting)
1262 __report_tpr_access(apic, write);
1265 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1269 if (offset >= LAPIC_MMIO_LENGTH)
1276 case APIC_TMCCT: /* Timer CCR */
1277 if (apic_lvtt_tscdeadline(apic))
1280 val = apic_get_tmcct(apic);
1283 apic_update_ppr(apic);
1284 val = kvm_lapic_get_reg(apic, offset);
1287 report_tpr_access(apic, false);
1290 val = kvm_lapic_get_reg(apic, offset);
1297 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1299 return container_of(dev, struct kvm_lapic, dev);
1302 #define APIC_REG_MASK(reg) (1ull << ((reg) >> 4))
1303 #define APIC_REGS_MASK(first, count) \
1304 (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1306 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1309 unsigned char alignment = offset & 0xf;
1311 /* this bitmask has a bit cleared for each reserved register */
1312 u64 valid_reg_mask =
1313 APIC_REG_MASK(APIC_ID) |
1314 APIC_REG_MASK(APIC_LVR) |
1315 APIC_REG_MASK(APIC_TASKPRI) |
1316 APIC_REG_MASK(APIC_PROCPRI) |
1317 APIC_REG_MASK(APIC_LDR) |
1318 APIC_REG_MASK(APIC_DFR) |
1319 APIC_REG_MASK(APIC_SPIV) |
1320 APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) |
1321 APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) |
1322 APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) |
1323 APIC_REG_MASK(APIC_ESR) |
1324 APIC_REG_MASK(APIC_ICR) |
1325 APIC_REG_MASK(APIC_ICR2) |
1326 APIC_REG_MASK(APIC_LVTT) |
1327 APIC_REG_MASK(APIC_LVTTHMR) |
1328 APIC_REG_MASK(APIC_LVTPC) |
1329 APIC_REG_MASK(APIC_LVT0) |
1330 APIC_REG_MASK(APIC_LVT1) |
1331 APIC_REG_MASK(APIC_LVTERR) |
1332 APIC_REG_MASK(APIC_TMICT) |
1333 APIC_REG_MASK(APIC_TMCCT) |
1334 APIC_REG_MASK(APIC_TDCR);
1336 /* ARBPRI is not valid on x2APIC */
1337 if (!apic_x2apic_mode(apic))
1338 valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI);
1340 if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset)))
1343 result = __apic_read(apic, offset & ~0xf);
1345 trace_kvm_apic_read(offset, result);
1351 memcpy(data, (char *)&result + alignment, len);
1354 printk(KERN_ERR "Local APIC read with len = %x, "
1355 "should be 1,2, or 4 instead\n", len);
1360 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1362 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1364 return addr >= apic->base_address &&
1365 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1368 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1369 gpa_t address, int len, void *data)
1371 struct kvm_lapic *apic = to_lapic(this);
1372 u32 offset = address - apic->base_address;
1374 if (!apic_mmio_in_range(apic, address))
1377 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1378 if (!kvm_check_has_quirk(vcpu->kvm,
1379 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1382 memset(data, 0xff, len);
1386 kvm_lapic_reg_read(apic, offset, len, data);
1391 static void update_divide_count(struct kvm_lapic *apic)
1393 u32 tmp1, tmp2, tdcr;
1395 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1397 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1398 apic->divide_count = 0x1 << (tmp2 & 0x7);
1401 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1404 * Do not allow the guest to program periodic timers with small
1405 * interval, since the hrtimers are not throttled by the host
1408 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1409 s64 min_period = min_timer_period_us * 1000LL;
1411 if (apic->lapic_timer.period < min_period) {
1412 pr_info_ratelimited(
1413 "kvm: vcpu %i: requested %lld ns "
1414 "lapic timer period limited to %lld ns\n",
1415 apic->vcpu->vcpu_id,
1416 apic->lapic_timer.period, min_period);
1417 apic->lapic_timer.period = min_period;
1422 static void apic_update_lvtt(struct kvm_lapic *apic)
1424 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1425 apic->lapic_timer.timer_mode_mask;
1427 if (apic->lapic_timer.timer_mode != timer_mode) {
1428 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1429 APIC_LVT_TIMER_TSCDEADLINE)) {
1430 hrtimer_cancel(&apic->lapic_timer.timer);
1431 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1432 apic->lapic_timer.period = 0;
1433 apic->lapic_timer.tscdeadline = 0;
1435 apic->lapic_timer.timer_mode = timer_mode;
1436 limit_periodic_timer_frequency(apic);
1441 * On APICv, this test will cause a busy wait
1442 * during a higher-priority task.
1445 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1447 struct kvm_lapic *apic = vcpu->arch.apic;
1448 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1450 if (kvm_apic_hw_enabled(apic)) {
1451 int vec = reg & APIC_VECTOR_MASK;
1452 void *bitmap = apic->regs + APIC_ISR;
1454 if (vcpu->arch.apicv_active)
1455 bitmap = apic->regs + APIC_IRR;
1457 if (apic_test_vector(vec, bitmap))
1463 static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles)
1465 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;
1468 * If the guest TSC is running at a different ratio than the host, then
1469 * convert the delay to nanoseconds to achieve an accurate delay. Note
1470 * that __delay() uses delay_tsc whenever the hardware has TSC, thus
1471 * always for VMX enabled hardware.
1473 if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) {
1474 __delay(min(guest_cycles,
1475 nsec_to_cycles(vcpu, timer_advance_ns)));
1477 u64 delay_ns = guest_cycles * 1000000ULL;
1478 do_div(delay_ns, vcpu->arch.virtual_tsc_khz);
1479 ndelay(min_t(u32, delay_ns, timer_advance_ns));
1483 static inline void adjust_lapic_timer_advance(struct kvm_vcpu *vcpu,
1484 s64 advance_expire_delta)
1486 struct kvm_lapic *apic = vcpu->arch.apic;
1487 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
1491 if (advance_expire_delta < 0) {
1492 ns = -advance_expire_delta * 1000000ULL;
1493 do_div(ns, vcpu->arch.virtual_tsc_khz);
1494 timer_advance_ns -= min((u32)ns,
1495 timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP);
1498 ns = advance_expire_delta * 1000000ULL;
1499 do_div(ns, vcpu->arch.virtual_tsc_khz);
1500 timer_advance_ns += min((u32)ns,
1501 timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP);
1504 if (abs(advance_expire_delta) < LAPIC_TIMER_ADVANCE_ADJUST_DONE)
1505 apic->lapic_timer.timer_advance_adjust_done = true;
1506 if (unlikely(timer_advance_ns > 5000)) {
1507 timer_advance_ns = LAPIC_TIMER_ADVANCE_ADJUST_INIT;
1508 apic->lapic_timer.timer_advance_adjust_done = false;
1510 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
1513 static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1515 struct kvm_lapic *apic = vcpu->arch.apic;
1516 u64 guest_tsc, tsc_deadline;
1518 if (apic->lapic_timer.expired_tscdeadline == 0)
1521 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1522 apic->lapic_timer.expired_tscdeadline = 0;
1523 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1524 apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline;
1526 if (guest_tsc < tsc_deadline)
1527 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
1529 if (unlikely(!apic->lapic_timer.timer_advance_adjust_done))
1530 adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta);
1533 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1535 if (lapic_timer_int_injected(vcpu))
1536 __kvm_wait_lapic_expire(vcpu);
1538 EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire);
1540 static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic)
1542 struct kvm_timer *ktimer = &apic->lapic_timer;
1544 kvm_apic_local_deliver(apic, APIC_LVTT);
1545 if (apic_lvtt_tscdeadline(apic))
1546 ktimer->tscdeadline = 0;
1547 if (apic_lvtt_oneshot(apic)) {
1548 ktimer->tscdeadline = 0;
1549 ktimer->target_expiration = 0;
1553 static void apic_timer_expired(struct kvm_lapic *apic)
1555 struct kvm_vcpu *vcpu = apic->vcpu;
1556 struct kvm_timer *ktimer = &apic->lapic_timer;
1558 if (atomic_read(&apic->lapic_timer.pending))
1561 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
1562 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1564 if (kvm_use_posted_timer_interrupt(apic->vcpu)) {
1565 if (apic->lapic_timer.timer_advance_ns)
1566 __kvm_wait_lapic_expire(vcpu);
1567 kvm_apic_inject_pending_timer_irqs(apic);
1571 atomic_inc(&apic->lapic_timer.pending);
1572 kvm_set_pending_timer(vcpu);
1575 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1577 struct kvm_timer *ktimer = &apic->lapic_timer;
1578 u64 guest_tsc, tscdeadline = ktimer->tscdeadline;
1581 struct kvm_vcpu *vcpu = apic->vcpu;
1582 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1583 unsigned long flags;
1586 if (unlikely(!tscdeadline || !this_tsc_khz))
1589 local_irq_save(flags);
1592 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1594 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1595 do_div(ns, this_tsc_khz);
1597 if (likely(tscdeadline > guest_tsc) &&
1598 likely(ns > apic->lapic_timer.timer_advance_ns)) {
1599 expire = ktime_add_ns(now, ns);
1600 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns);
1601 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS);
1603 apic_timer_expired(apic);
1605 local_irq_restore(flags);
1608 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1610 ktime_t now, remaining;
1611 u64 ns_remaining_old, ns_remaining_new;
1613 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1614 * APIC_BUS_CYCLE_NS * apic->divide_count;
1615 limit_periodic_timer_frequency(apic);
1618 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1619 if (ktime_to_ns(remaining) < 0)
1622 ns_remaining_old = ktime_to_ns(remaining);
1623 ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1624 apic->divide_count, old_divisor);
1626 apic->lapic_timer.tscdeadline +=
1627 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1628 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1629 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1632 static bool set_target_expiration(struct kvm_lapic *apic)
1638 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1639 * APIC_BUS_CYCLE_NS * apic->divide_count;
1641 if (!apic->lapic_timer.period) {
1642 apic->lapic_timer.tscdeadline = 0;
1646 limit_periodic_timer_frequency(apic);
1648 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1649 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1650 apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1655 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1657 ktime_t now = ktime_get();
1662 * Synchronize both deadlines to the same time source or
1663 * differences in the periods (caused by differences in the
1664 * underlying clocks or numerical approximation errors) will
1665 * cause the two to drift apart over time as the errors
1668 apic->lapic_timer.target_expiration =
1669 ktime_add_ns(apic->lapic_timer.target_expiration,
1670 apic->lapic_timer.period);
1671 delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1672 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1673 nsec_to_cycles(apic->vcpu, delta);
1676 static void start_sw_period(struct kvm_lapic *apic)
1678 if (!apic->lapic_timer.period)
1681 if (ktime_after(ktime_get(),
1682 apic->lapic_timer.target_expiration)) {
1683 apic_timer_expired(apic);
1685 if (apic_lvtt_oneshot(apic))
1688 advance_periodic_target_expiration(apic);
1691 hrtimer_start(&apic->lapic_timer.timer,
1692 apic->lapic_timer.target_expiration,
1696 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1698 if (!lapic_in_kernel(vcpu))
1701 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1703 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1705 static void cancel_hv_timer(struct kvm_lapic *apic)
1707 WARN_ON(preemptible());
1708 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1709 kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1710 apic->lapic_timer.hv_timer_in_use = false;
1713 static bool start_hv_timer(struct kvm_lapic *apic)
1715 struct kvm_timer *ktimer = &apic->lapic_timer;
1716 struct kvm_vcpu *vcpu = apic->vcpu;
1719 WARN_ON(preemptible());
1720 if (!kvm_x86_ops->set_hv_timer)
1723 if (!ktimer->tscdeadline)
1726 if (kvm_x86_ops->set_hv_timer(vcpu, ktimer->tscdeadline, &expired))
1729 ktimer->hv_timer_in_use = true;
1730 hrtimer_cancel(&ktimer->timer);
1733 * To simplify handling the periodic timer, leave the hv timer running
1734 * even if the deadline timer has expired, i.e. rely on the resulting
1735 * VM-Exit to recompute the periodic timer's target expiration.
1737 if (!apic_lvtt_period(apic)) {
1739 * Cancel the hv timer if the sw timer fired while the hv timer
1740 * was being programmed, or if the hv timer itself expired.
1742 if (atomic_read(&ktimer->pending)) {
1743 cancel_hv_timer(apic);
1744 } else if (expired) {
1745 apic_timer_expired(apic);
1746 cancel_hv_timer(apic);
1750 trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use);
1755 static void start_sw_timer(struct kvm_lapic *apic)
1757 struct kvm_timer *ktimer = &apic->lapic_timer;
1759 WARN_ON(preemptible());
1760 if (apic->lapic_timer.hv_timer_in_use)
1761 cancel_hv_timer(apic);
1762 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1765 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1766 start_sw_period(apic);
1767 else if (apic_lvtt_tscdeadline(apic))
1768 start_sw_tscdeadline(apic);
1769 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1772 static void restart_apic_timer(struct kvm_lapic *apic)
1776 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending))
1779 if (!start_hv_timer(apic))
1780 start_sw_timer(apic);
1785 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1787 struct kvm_lapic *apic = vcpu->arch.apic;
1790 /* If the preempt notifier has already run, it also called apic_timer_expired */
1791 if (!apic->lapic_timer.hv_timer_in_use)
1793 WARN_ON(swait_active(&vcpu->wq));
1794 cancel_hv_timer(apic);
1795 apic_timer_expired(apic);
1797 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1798 advance_periodic_target_expiration(apic);
1799 restart_apic_timer(apic);
1804 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1806 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1808 restart_apic_timer(vcpu->arch.apic);
1810 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1812 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1814 struct kvm_lapic *apic = vcpu->arch.apic;
1817 /* Possibly the TSC deadline timer is not enabled yet */
1818 if (apic->lapic_timer.hv_timer_in_use)
1819 start_sw_timer(apic);
1822 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1824 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1826 struct kvm_lapic *apic = vcpu->arch.apic;
1828 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1829 restart_apic_timer(apic);
1832 static void start_apic_timer(struct kvm_lapic *apic)
1834 atomic_set(&apic->lapic_timer.pending, 0);
1836 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1837 && !set_target_expiration(apic))
1840 restart_apic_timer(apic);
1843 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1845 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1847 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1848 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1849 if (lvt0_in_nmi_mode) {
1850 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1852 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1856 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1860 trace_kvm_apic_write(reg, val);
1863 case APIC_ID: /* Local APIC ID */
1864 if (!apic_x2apic_mode(apic))
1865 kvm_apic_set_xapic_id(apic, val >> 24);
1871 report_tpr_access(apic, true);
1872 apic_set_tpr(apic, val & 0xff);
1880 if (!apic_x2apic_mode(apic))
1881 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1887 if (!apic_x2apic_mode(apic)) {
1888 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1889 recalculate_apic_map(apic->vcpu->kvm);
1896 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1897 mask |= APIC_SPIV_DIRECTED_EOI;
1898 apic_set_spiv(apic, val & mask);
1899 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1903 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1904 lvt_val = kvm_lapic_get_reg(apic,
1905 APIC_LVTT + 0x10 * i);
1906 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1907 lvt_val | APIC_LVT_MASKED);
1909 apic_update_lvtt(apic);
1910 atomic_set(&apic->lapic_timer.pending, 0);
1916 /* No delay here, so we always clear the pending bit */
1917 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1918 apic_send_ipi(apic);
1922 if (!apic_x2apic_mode(apic))
1924 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1928 apic_manage_nmi_watchdog(apic, val);
1934 /* TODO: Check vector */
1935 if (!kvm_apic_sw_enabled(apic))
1936 val |= APIC_LVT_MASKED;
1938 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1939 kvm_lapic_set_reg(apic, reg, val);
1944 if (!kvm_apic_sw_enabled(apic))
1945 val |= APIC_LVT_MASKED;
1946 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1947 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1948 apic_update_lvtt(apic);
1952 if (apic_lvtt_tscdeadline(apic))
1955 hrtimer_cancel(&apic->lapic_timer.timer);
1956 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1957 start_apic_timer(apic);
1961 uint32_t old_divisor = apic->divide_count;
1963 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1964 update_divide_count(apic);
1965 if (apic->divide_count != old_divisor &&
1966 apic->lapic_timer.period) {
1967 hrtimer_cancel(&apic->lapic_timer.timer);
1968 update_target_expiration(apic, old_divisor);
1969 restart_apic_timer(apic);
1974 if (apic_x2apic_mode(apic) && val != 0)
1979 if (apic_x2apic_mode(apic)) {
1980 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1991 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1993 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1994 gpa_t address, int len, const void *data)
1996 struct kvm_lapic *apic = to_lapic(this);
1997 unsigned int offset = address - apic->base_address;
2000 if (!apic_mmio_in_range(apic, address))
2003 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
2004 if (!kvm_check_has_quirk(vcpu->kvm,
2005 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
2012 * APIC register must be aligned on 128-bits boundary.
2013 * 32/64/128 bits registers must be accessed thru 32 bits.
2016 if (len != 4 || (offset & 0xf))
2021 kvm_lapic_reg_write(apic, offset & 0xff0, val);
2026 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
2028 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
2030 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
2032 /* emulate APIC access in a trap manner */
2033 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
2037 /* hw has done the conditional check and inst decode */
2040 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
2042 /* TODO: optimize to just emulate side effect w/o one more write */
2043 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
2045 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2047 void kvm_free_lapic(struct kvm_vcpu *vcpu)
2049 struct kvm_lapic *apic = vcpu->arch.apic;
2051 if (!vcpu->arch.apic)
2054 hrtimer_cancel(&apic->lapic_timer.timer);
2056 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2057 static_key_slow_dec_deferred(&apic_hw_disabled);
2059 if (!apic->sw_enabled)
2060 static_key_slow_dec_deferred(&apic_sw_disabled);
2063 free_page((unsigned long)apic->regs);
2069 *----------------------------------------------------------------------
2071 *----------------------------------------------------------------------
2073 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2075 struct kvm_lapic *apic = vcpu->arch.apic;
2077 if (!lapic_in_kernel(vcpu) ||
2078 !apic_lvtt_tscdeadline(apic))
2081 return apic->lapic_timer.tscdeadline;
2084 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2086 struct kvm_lapic *apic = vcpu->arch.apic;
2088 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
2089 apic_lvtt_period(apic))
2092 hrtimer_cancel(&apic->lapic_timer.timer);
2093 apic->lapic_timer.tscdeadline = data;
2094 start_apic_timer(apic);
2097 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2099 struct kvm_lapic *apic = vcpu->arch.apic;
2101 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
2102 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
2105 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2109 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2111 return (tpr & 0xf0) >> 4;
2114 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2116 u64 old_value = vcpu->arch.apic_base;
2117 struct kvm_lapic *apic = vcpu->arch.apic;
2120 value |= MSR_IA32_APICBASE_BSP;
2122 vcpu->arch.apic_base = value;
2124 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2125 kvm_update_cpuid(vcpu);
2130 /* update jump label if enable bit changes */
2131 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2132 if (value & MSR_IA32_APICBASE_ENABLE) {
2133 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2134 static_key_slow_dec_deferred(&apic_hw_disabled);
2136 static_key_slow_inc(&apic_hw_disabled.key);
2137 recalculate_apic_map(vcpu->kvm);
2141 if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2142 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2144 if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2145 kvm_x86_ops->set_virtual_apic_mode(vcpu);
2147 apic->base_address = apic->vcpu->arch.apic_base &
2148 MSR_IA32_APICBASE_BASE;
2150 if ((value & MSR_IA32_APICBASE_ENABLE) &&
2151 apic->base_address != APIC_DEFAULT_PHYS_BASE)
2152 pr_warn_once("APIC base relocation is unsupported by KVM");
2155 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2157 struct kvm_lapic *apic = vcpu->arch.apic;
2163 /* Stop the timer in case it's a reset to an active apic */
2164 hrtimer_cancel(&apic->lapic_timer.timer);
2167 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2168 MSR_IA32_APICBASE_ENABLE);
2169 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2171 kvm_apic_set_version(apic->vcpu);
2173 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2174 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2175 apic_update_lvtt(apic);
2176 if (kvm_vcpu_is_reset_bsp(vcpu) &&
2177 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2178 kvm_lapic_set_reg(apic, APIC_LVT0,
2179 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2180 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2182 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
2183 apic_set_spiv(apic, 0xff);
2184 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2185 if (!apic_x2apic_mode(apic))
2186 kvm_apic_set_ldr(apic, 0);
2187 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2188 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2189 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2190 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2191 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2192 for (i = 0; i < 8; i++) {
2193 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2194 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2195 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2197 apic->irr_pending = vcpu->arch.apicv_active;
2198 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
2199 apic->highest_isr_cache = -1;
2200 update_divide_count(apic);
2201 atomic_set(&apic->lapic_timer.pending, 0);
2202 if (kvm_vcpu_is_bsp(vcpu))
2203 kvm_lapic_set_base(vcpu,
2204 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2205 vcpu->arch.pv_eoi.msr_val = 0;
2206 apic_update_ppr(apic);
2207 if (vcpu->arch.apicv_active) {
2208 kvm_x86_ops->apicv_post_state_restore(vcpu);
2209 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2210 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2213 vcpu->arch.apic_arb_prio = 0;
2214 vcpu->arch.apic_attention = 0;
2218 *----------------------------------------------------------------------
2220 *----------------------------------------------------------------------
2223 static bool lapic_is_periodic(struct kvm_lapic *apic)
2225 return apic_lvtt_period(apic);
2228 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2230 struct kvm_lapic *apic = vcpu->arch.apic;
2232 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2233 return atomic_read(&apic->lapic_timer.pending);
2238 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2240 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2241 int vector, mode, trig_mode;
2243 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2244 vector = reg & APIC_VECTOR_MASK;
2245 mode = reg & APIC_MODE_MASK;
2246 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2247 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2253 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2255 struct kvm_lapic *apic = vcpu->arch.apic;
2258 kvm_apic_local_deliver(apic, APIC_LVT0);
2261 static const struct kvm_io_device_ops apic_mmio_ops = {
2262 .read = apic_mmio_read,
2263 .write = apic_mmio_write,
2266 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2268 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2269 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2271 apic_timer_expired(apic);
2273 if (lapic_is_periodic(apic)) {
2274 advance_periodic_target_expiration(apic);
2275 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2276 return HRTIMER_RESTART;
2278 return HRTIMER_NORESTART;
2281 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns)
2283 struct kvm_lapic *apic;
2285 ASSERT(vcpu != NULL);
2287 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT);
2291 vcpu->arch.apic = apic;
2293 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
2295 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2297 goto nomem_free_apic;
2301 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2303 apic->lapic_timer.timer.function = apic_timer_fn;
2304 if (timer_advance_ns == -1) {
2305 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_ADJUST_INIT;
2306 apic->lapic_timer.timer_advance_adjust_done = false;
2308 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
2309 apic->lapic_timer.timer_advance_adjust_done = true;
2314 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2315 * thinking that APIC state has changed.
2317 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2318 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2319 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2324 vcpu->arch.apic = NULL;
2329 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2331 struct kvm_lapic *apic = vcpu->arch.apic;
2334 if (!kvm_apic_hw_enabled(apic))
2337 __apic_update_ppr(apic, &ppr);
2338 return apic_has_interrupt_for_ppr(apic, ppr);
2341 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2343 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2346 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2348 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2349 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2354 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2356 struct kvm_lapic *apic = vcpu->arch.apic;
2358 if (atomic_read(&apic->lapic_timer.pending) > 0) {
2359 kvm_apic_inject_pending_timer_irqs(apic);
2360 atomic_set(&apic->lapic_timer.pending, 0);
2364 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2366 int vector = kvm_apic_has_interrupt(vcpu);
2367 struct kvm_lapic *apic = vcpu->arch.apic;
2374 * We get here even with APIC virtualization enabled, if doing
2375 * nested virtualization and L1 runs with the "acknowledge interrupt
2376 * on exit" mode. Then we cannot inject the interrupt via RVI,
2377 * because the process would deliver it through the IDT.
2380 apic_clear_irr(vector, apic);
2381 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2383 * For auto-EOI interrupts, there might be another pending
2384 * interrupt above PPR, so check whether to raise another
2387 apic_update_ppr(apic);
2390 * For normal interrupts, PPR has been raised and there cannot
2391 * be a higher-priority pending interrupt---except if there was
2392 * a concurrent interrupt injection, but that would have
2393 * triggered KVM_REQ_EVENT already.
2395 apic_set_isr(vector, apic);
2396 __apic_update_ppr(apic, &ppr);
2402 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2403 struct kvm_lapic_state *s, bool set)
2405 if (apic_x2apic_mode(vcpu->arch.apic)) {
2406 u32 *id = (u32 *)(s->regs + APIC_ID);
2407 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2409 if (vcpu->kvm->arch.x2apic_format) {
2410 if (*id != vcpu->vcpu_id)
2419 /* In x2APIC mode, the LDR is fixed and based on the id */
2421 *ldr = kvm_apic_calc_x2apic_ldr(*id);
2427 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2429 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2430 return kvm_apic_state_fixup(vcpu, s, false);
2433 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2435 struct kvm_lapic *apic = vcpu->arch.apic;
2439 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2440 /* set SPIV separately to get count of SW disabled APICs right */
2441 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2443 r = kvm_apic_state_fixup(vcpu, s, true);
2446 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
2448 recalculate_apic_map(vcpu->kvm);
2449 kvm_apic_set_version(vcpu);
2451 apic_update_ppr(apic);
2452 hrtimer_cancel(&apic->lapic_timer.timer);
2453 apic_update_lvtt(apic);
2454 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2455 update_divide_count(apic);
2456 start_apic_timer(apic);
2457 apic->irr_pending = true;
2458 apic->isr_count = vcpu->arch.apicv_active ?
2459 1 : count_vectors(apic->regs + APIC_ISR);
2460 apic->highest_isr_cache = -1;
2461 if (vcpu->arch.apicv_active) {
2462 kvm_x86_ops->apicv_post_state_restore(vcpu);
2463 kvm_x86_ops->hwapic_irr_update(vcpu,
2464 apic_find_highest_irr(apic));
2465 kvm_x86_ops->hwapic_isr_update(vcpu,
2466 apic_find_highest_isr(apic));
2468 kvm_make_request(KVM_REQ_EVENT, vcpu);
2469 if (ioapic_in_kernel(vcpu->kvm))
2470 kvm_rtc_eoi_tracking_restore_one(vcpu);
2472 vcpu->arch.apic_arb_prio = 0;
2477 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2479 struct hrtimer *timer;
2481 if (!lapic_in_kernel(vcpu) ||
2482 kvm_can_post_timer_interrupt(vcpu))
2485 timer = &vcpu->arch.apic->lapic_timer.timer;
2486 if (hrtimer_cancel(timer))
2487 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
2491 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2493 * Detect whether guest triggered PV EOI since the
2494 * last entry. If yes, set EOI on guests's behalf.
2495 * Clear PV EOI in guest memory in any case.
2497 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2498 struct kvm_lapic *apic)
2503 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2504 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2506 * KVM_APIC_PV_EOI_PENDING is unset:
2507 * -> host disabled PV EOI.
2508 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2509 * -> host enabled PV EOI, guest did not execute EOI yet.
2510 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2511 * -> host enabled PV EOI, guest executed EOI.
2513 BUG_ON(!pv_eoi_enabled(vcpu));
2514 pending = pv_eoi_get_pending(vcpu);
2516 * Clear pending bit in any case: it will be set again on vmentry.
2517 * While this might not be ideal from performance point of view,
2518 * this makes sure pv eoi is only enabled when we know it's safe.
2520 pv_eoi_clr_pending(vcpu);
2523 vector = apic_set_eoi(apic);
2524 trace_kvm_pv_eoi(apic, vector);
2527 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2531 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2532 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2534 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2537 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2541 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2545 * apic_sync_pv_eoi_to_guest - called before vmentry
2547 * Detect whether it's safe to enable PV EOI and
2550 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2551 struct kvm_lapic *apic)
2553 if (!pv_eoi_enabled(vcpu) ||
2554 /* IRR set or many bits in ISR: could be nested. */
2555 apic->irr_pending ||
2556 /* Cache not set: could be safe but we don't bother. */
2557 apic->highest_isr_cache == -1 ||
2558 /* Need EOI to update ioapic. */
2559 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2561 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2562 * so we need not do anything here.
2567 pv_eoi_set_pending(apic->vcpu);
2570 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2573 int max_irr, max_isr;
2574 struct kvm_lapic *apic = vcpu->arch.apic;
2576 apic_sync_pv_eoi_to_guest(vcpu, apic);
2578 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2581 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2582 max_irr = apic_find_highest_irr(apic);
2585 max_isr = apic_find_highest_isr(apic);
2588 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2590 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2594 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2597 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2598 &vcpu->arch.apic->vapic_cache,
2599 vapic_addr, sizeof(u32)))
2601 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2603 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2606 vcpu->arch.apic->vapic_addr = vapic_addr;
2610 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2612 struct kvm_lapic *apic = vcpu->arch.apic;
2613 u32 reg = (msr - APIC_BASE_MSR) << 4;
2615 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2618 if (reg == APIC_ICR2)
2621 /* if this is ICR write vector before command */
2622 if (reg == APIC_ICR)
2623 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2624 return kvm_lapic_reg_write(apic, reg, (u32)data);
2627 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2629 struct kvm_lapic *apic = vcpu->arch.apic;
2630 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2632 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2635 if (reg == APIC_DFR || reg == APIC_ICR2)
2638 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2640 if (reg == APIC_ICR)
2641 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2643 *data = (((u64)high) << 32) | low;
2648 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2650 struct kvm_lapic *apic = vcpu->arch.apic;
2652 if (!lapic_in_kernel(vcpu))
2655 /* if this is ICR write vector before command */
2656 if (reg == APIC_ICR)
2657 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2658 return kvm_lapic_reg_write(apic, reg, (u32)data);
2661 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2663 struct kvm_lapic *apic = vcpu->arch.apic;
2666 if (!lapic_in_kernel(vcpu))
2669 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2671 if (reg == APIC_ICR)
2672 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2674 *data = (((u64)high) << 32) | low;
2679 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
2681 u64 addr = data & ~KVM_MSR_ENABLED;
2682 struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2683 unsigned long new_len;
2685 if (!IS_ALIGNED(addr, 4))
2688 vcpu->arch.pv_eoi.msr_val = data;
2689 if (!pv_eoi_enabled(vcpu))
2692 if (addr == ghc->gpa && len <= ghc->len)
2697 return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
2700 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2702 struct kvm_lapic *apic = vcpu->arch.apic;
2706 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2710 * INITs are latched while in SMM. Because an SMM CPU cannot
2711 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2712 * and delay processing of INIT until the next RSM.
2715 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2716 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2717 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2721 pe = xchg(&apic->pending_events, 0);
2722 if (test_bit(KVM_APIC_INIT, &pe)) {
2723 kvm_vcpu_reset(vcpu, true);
2724 if (kvm_vcpu_is_bsp(apic->vcpu))
2725 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2727 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2729 if (test_bit(KVM_APIC_SIPI, &pe) &&
2730 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2731 /* evaluate pending_events before reading the vector */
2733 sipi_vector = apic->sipi_vector;
2734 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2735 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2739 void kvm_lapic_init(void)
2741 /* do not patch jump label more than once per second */
2742 jump_label_rate_limit(&apic_hw_disabled, HZ);
2743 jump_label_rate_limit(&apic_sw_disabled, HZ);
2746 void kvm_lapic_exit(void)
2748 static_key_deferred_flush(&apic_hw_disabled);
2749 static_key_deferred_flush(&apic_sw_disabled);