1 // SPDX-License-Identifier: GPL-2.0-only
4 * Local APIC virtualization
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2007 Novell
8 * Copyright (C) 2007 Intel
9 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
12 * Dor Laor <dor.laor@qumranet.com>
13 * Gregory Haskins <ghaskins@novell.com>
14 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
16 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
19 #include <linux/kvm_host.h>
20 #include <linux/kvm.h>
22 #include <linux/highmem.h>
23 #include <linux/smp.h>
24 #include <linux/hrtimer.h>
26 #include <linux/export.h>
27 #include <linux/math64.h>
28 #include <linux/slab.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/delay.h>
35 #include <linux/atomic.h>
36 #include <linux/jump_label.h>
37 #include "kvm_cache_regs.h"
46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48 #define mod_64(x, y) ((x) % (y))
56 /* 14 is the version for Xeon and Pentium 8.4.8*/
57 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
58 #define LAPIC_MMIO_LENGTH (1 << 12)
59 /* followed define is not in apicdef.h */
60 #define MAX_APIC_VECTOR 256
61 #define APIC_VECTORS_PER_REG 32
63 static bool lapic_timer_advance_dynamic __read_mostly;
64 #define LAPIC_TIMER_ADVANCE_ADJUST_MIN 100 /* clock cycles */
65 #define LAPIC_TIMER_ADVANCE_ADJUST_MAX 10000 /* clock cycles */
66 #define LAPIC_TIMER_ADVANCE_NS_INIT 1000
67 #define LAPIC_TIMER_ADVANCE_NS_MAX 5000
68 /* step-by-step approximation to mitigate fluctuation */
69 #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
71 static inline int apic_test_vector(int vec, void *bitmap)
73 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
76 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
78 struct kvm_lapic *apic = vcpu->arch.apic;
80 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
81 apic_test_vector(vector, apic->regs + APIC_IRR);
84 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
86 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
89 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
91 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
94 __read_mostly DEFINE_STATIC_KEY_DEFERRED_FALSE(apic_hw_disabled, HZ);
95 __read_mostly DEFINE_STATIC_KEY_DEFERRED_FALSE(apic_sw_disabled, HZ);
97 static inline int apic_enabled(struct kvm_lapic *apic)
99 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
103 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
106 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
107 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
109 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
111 return apic->vcpu->vcpu_id;
114 static bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu)
116 return pi_inject_timer && kvm_vcpu_apicv_active(vcpu);
119 bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu)
121 return kvm_x86_ops.set_hv_timer
122 && !(kvm_mwait_in_guest(vcpu->kvm) ||
123 kvm_can_post_timer_interrupt(vcpu));
125 EXPORT_SYMBOL_GPL(kvm_can_use_hv_timer);
127 static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu)
129 return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE;
132 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
133 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
135 case KVM_APIC_MODE_X2APIC: {
136 u32 offset = (dest_id >> 16) * 16;
137 u32 max_apic_id = map->max_apic_id;
139 if (offset <= max_apic_id) {
140 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
142 offset = array_index_nospec(offset, map->max_apic_id + 1);
143 *cluster = &map->phys_map[offset];
144 *mask = dest_id & (0xffff >> (16 - cluster_size));
151 case KVM_APIC_MODE_XAPIC_FLAT:
152 *cluster = map->xapic_flat_map;
153 *mask = dest_id & 0xff;
155 case KVM_APIC_MODE_XAPIC_CLUSTER:
156 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
157 *mask = dest_id & 0xf;
165 static void kvm_apic_map_free(struct rcu_head *rcu)
167 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
173 * CLEAN -> DIRTY and UPDATE_IN_PROGRESS -> DIRTY changes happen without a lock.
175 * DIRTY -> UPDATE_IN_PROGRESS and UPDATE_IN_PROGRESS -> CLEAN happen with
176 * apic_map_lock_held.
184 void kvm_recalculate_apic_map(struct kvm *kvm)
186 struct kvm_apic_map *new, *old = NULL;
187 struct kvm_vcpu *vcpu;
189 u32 max_id = 255; /* enough space for any xAPIC ID */
191 /* Read kvm->arch.apic_map_dirty before kvm->arch.apic_map. */
192 if (atomic_read_acquire(&kvm->arch.apic_map_dirty) == CLEAN)
195 WARN_ONCE(!irqchip_in_kernel(kvm),
196 "Dirty APIC map without an in-kernel local APIC");
198 mutex_lock(&kvm->arch.apic_map_lock);
200 * Read kvm->arch.apic_map_dirty before kvm->arch.apic_map
201 * (if clean) or the APIC registers (if dirty).
203 if (atomic_cmpxchg_acquire(&kvm->arch.apic_map_dirty,
204 DIRTY, UPDATE_IN_PROGRESS) == CLEAN) {
205 /* Someone else has updated the map. */
206 mutex_unlock(&kvm->arch.apic_map_lock);
210 kvm_for_each_vcpu(i, vcpu, kvm)
211 if (kvm_apic_present(vcpu))
212 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
214 new = kvzalloc(sizeof(struct kvm_apic_map) +
215 sizeof(struct kvm_lapic *) * ((u64)max_id + 1),
221 new->max_apic_id = max_id;
223 kvm_for_each_vcpu(i, vcpu, kvm) {
224 struct kvm_lapic *apic = vcpu->arch.apic;
225 struct kvm_lapic **cluster;
231 if (!kvm_apic_present(vcpu))
234 xapic_id = kvm_xapic_id(apic);
235 x2apic_id = kvm_x2apic_id(apic);
237 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
238 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
239 x2apic_id <= new->max_apic_id)
240 new->phys_map[x2apic_id] = apic;
242 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
243 * prevent them from masking VCPUs with APIC ID <= 0xff.
245 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
246 new->phys_map[xapic_id] = apic;
248 if (!kvm_apic_sw_enabled(apic))
251 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
253 if (apic_x2apic_mode(apic)) {
254 new->mode |= KVM_APIC_MODE_X2APIC;
256 ldr = GET_APIC_LOGICAL_ID(ldr);
257 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
258 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
260 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
263 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
267 cluster[ffs(mask) - 1] = apic;
270 old = rcu_dereference_protected(kvm->arch.apic_map,
271 lockdep_is_held(&kvm->arch.apic_map_lock));
272 rcu_assign_pointer(kvm->arch.apic_map, new);
274 * Write kvm->arch.apic_map before clearing apic->apic_map_dirty.
275 * If another update has come in, leave it DIRTY.
277 atomic_cmpxchg_release(&kvm->arch.apic_map_dirty,
278 UPDATE_IN_PROGRESS, CLEAN);
279 mutex_unlock(&kvm->arch.apic_map_lock);
282 call_rcu(&old->rcu, kvm_apic_map_free);
284 kvm_make_scan_ioapic_request(kvm);
287 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
289 bool enabled = val & APIC_SPIV_APIC_ENABLED;
291 kvm_lapic_set_reg(apic, APIC_SPIV, val);
293 if (enabled != apic->sw_enabled) {
294 apic->sw_enabled = enabled;
296 static_branch_slow_dec_deferred(&apic_sw_disabled);
298 static_branch_inc(&apic_sw_disabled.key);
300 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
303 /* Check if there are APF page ready requests pending */
305 kvm_make_request(KVM_REQ_APF_READY, apic->vcpu);
308 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
310 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
311 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
314 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
316 kvm_lapic_set_reg(apic, APIC_LDR, id);
317 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
320 static inline void kvm_apic_set_dfr(struct kvm_lapic *apic, u32 val)
322 kvm_lapic_set_reg(apic, APIC_DFR, val);
323 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
326 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
328 return ((id >> 4) << 16) | (1 << (id & 0xf));
331 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
333 u32 ldr = kvm_apic_calc_x2apic_ldr(id);
335 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
337 kvm_lapic_set_reg(apic, APIC_ID, id);
338 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
339 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
342 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
344 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
347 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
349 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
352 static inline int apic_lvtt_period(struct kvm_lapic *apic)
354 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
357 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
359 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
362 static inline int apic_lvt_nmi_mode(u32 lvt_val)
364 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
367 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
369 struct kvm_lapic *apic = vcpu->arch.apic;
370 u32 v = APIC_VERSION;
372 if (!lapic_in_kernel(vcpu))
376 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
377 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
378 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
379 * version first and level-triggered interrupts never get EOIed in
382 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) &&
383 !ioapic_in_kernel(vcpu->kvm))
384 v |= APIC_LVR_DIRECTED_EOI;
385 kvm_lapic_set_reg(apic, APIC_LVR, v);
388 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
389 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
390 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
391 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
392 LINT_MASK, LINT_MASK, /* LVT0-1 */
393 LVT_MASK /* LVTERR */
396 static int find_highest_vector(void *bitmap)
401 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
402 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
403 reg = bitmap + REG_POS(vec);
405 return __fls(*reg) + vec;
411 static u8 count_vectors(void *bitmap)
417 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
418 reg = bitmap + REG_POS(vec);
419 count += hweight32(*reg);
425 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
428 u32 pir_val, irr_val, prev_irr_val;
431 max_updated_irr = -1;
434 for (i = vec = 0; i <= 7; i++, vec += 32) {
435 pir_val = READ_ONCE(pir[i]);
436 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
438 prev_irr_val = irr_val;
439 irr_val |= xchg(&pir[i], 0);
440 *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
441 if (prev_irr_val != irr_val) {
443 __fls(irr_val ^ prev_irr_val) + vec;
447 *max_irr = __fls(irr_val) + vec;
450 return ((max_updated_irr != -1) &&
451 (max_updated_irr == *max_irr));
453 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
455 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
457 struct kvm_lapic *apic = vcpu->arch.apic;
459 return __kvm_apic_update_irr(pir, apic->regs, max_irr);
461 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
463 static inline int apic_search_irr(struct kvm_lapic *apic)
465 return find_highest_vector(apic->regs + APIC_IRR);
468 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
473 * Note that irr_pending is just a hint. It will be always
474 * true with virtual interrupt delivery enabled.
476 if (!apic->irr_pending)
479 result = apic_search_irr(apic);
480 ASSERT(result == -1 || result >= 16);
485 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
487 struct kvm_vcpu *vcpu;
491 if (unlikely(vcpu->arch.apicv_active)) {
492 /* need to update RVI */
493 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
494 static_call(kvm_x86_hwapic_irr_update)(vcpu,
495 apic_find_highest_irr(apic));
497 apic->irr_pending = false;
498 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
499 if (apic_search_irr(apic) != -1)
500 apic->irr_pending = true;
504 void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec)
506 apic_clear_irr(vec, vcpu->arch.apic);
508 EXPORT_SYMBOL_GPL(kvm_apic_clear_irr);
510 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
512 struct kvm_vcpu *vcpu;
514 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
520 * With APIC virtualization enabled, all caching is disabled
521 * because the processor can modify ISR under the hood. Instead
524 if (unlikely(vcpu->arch.apicv_active))
525 static_call(kvm_x86_hwapic_isr_update)(vcpu, vec);
528 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
530 * ISR (in service register) bit is set when injecting an interrupt.
531 * The highest vector is injected. Thus the latest bit set matches
532 * the highest bit in ISR.
534 apic->highest_isr_cache = vec;
538 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
543 * Note that isr_count is always 1, and highest_isr_cache
544 * is always -1, with APIC virtualization enabled.
546 if (!apic->isr_count)
548 if (likely(apic->highest_isr_cache != -1))
549 return apic->highest_isr_cache;
551 result = find_highest_vector(apic->regs + APIC_ISR);
552 ASSERT(result == -1 || result >= 16);
557 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
559 struct kvm_vcpu *vcpu;
560 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
566 * We do get here for APIC virtualization enabled if the guest
567 * uses the Hyper-V APIC enlightenment. In this case we may need
568 * to trigger a new interrupt delivery by writing the SVI field;
569 * on the other hand isr_count and highest_isr_cache are unused
570 * and must be left alone.
572 if (unlikely(vcpu->arch.apicv_active))
573 static_call(kvm_x86_hwapic_isr_update)(vcpu,
574 apic_find_highest_isr(apic));
577 BUG_ON(apic->isr_count < 0);
578 apic->highest_isr_cache = -1;
582 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
584 /* This may race with setting of irr in __apic_accept_irq() and
585 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
586 * will cause vmexit immediately and the value will be recalculated
587 * on the next vmentry.
589 return apic_find_highest_irr(vcpu->arch.apic);
591 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
593 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
594 int vector, int level, int trig_mode,
595 struct dest_map *dest_map);
597 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
598 struct dest_map *dest_map)
600 struct kvm_lapic *apic = vcpu->arch.apic;
602 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
603 irq->level, irq->trig_mode, dest_map);
606 static int __pv_send_ipi(unsigned long *ipi_bitmap, struct kvm_apic_map *map,
607 struct kvm_lapic_irq *irq, u32 min)
610 struct kvm_vcpu *vcpu;
612 if (min > map->max_apic_id)
615 for_each_set_bit(i, ipi_bitmap,
616 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
617 if (map->phys_map[min + i]) {
618 vcpu = map->phys_map[min + i]->vcpu;
619 count += kvm_apic_set_irq(vcpu, irq, NULL);
626 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
627 unsigned long ipi_bitmap_high, u32 min,
628 unsigned long icr, int op_64_bit)
630 struct kvm_apic_map *map;
631 struct kvm_lapic_irq irq = {0};
632 int cluster_size = op_64_bit ? 64 : 32;
635 if (icr & (APIC_DEST_MASK | APIC_SHORT_MASK))
638 irq.vector = icr & APIC_VECTOR_MASK;
639 irq.delivery_mode = icr & APIC_MODE_MASK;
640 irq.level = (icr & APIC_INT_ASSERT) != 0;
641 irq.trig_mode = icr & APIC_INT_LEVELTRIG;
644 map = rcu_dereference(kvm->arch.apic_map);
648 count = __pv_send_ipi(&ipi_bitmap_low, map, &irq, min);
650 count += __pv_send_ipi(&ipi_bitmap_high, map, &irq, min);
657 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
660 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
664 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
667 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
671 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
673 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
676 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
678 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0)
681 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
684 static bool pv_eoi_test_and_clr_pending(struct kvm_vcpu *vcpu)
688 if (pv_eoi_get_user(vcpu, &val) < 0)
691 val &= KVM_PV_EOI_ENABLED;
693 if (val && pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0)
697 * Clear pending bit in any case: it will be set again on vmentry.
698 * While this might not be ideal from performance point of view,
699 * this makes sure pv eoi is only enabled when we know it's safe.
701 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
706 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
709 if (kvm_x86_ops.sync_pir_to_irr)
710 highest_irr = static_call(kvm_x86_sync_pir_to_irr)(apic->vcpu);
712 highest_irr = apic_find_highest_irr(apic);
713 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
718 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
720 u32 tpr, isrv, ppr, old_ppr;
723 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
724 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
725 isr = apic_find_highest_isr(apic);
726 isrv = (isr != -1) ? isr : 0;
728 if ((tpr & 0xf0) >= (isrv & 0xf0))
735 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
737 return ppr < old_ppr;
740 static void apic_update_ppr(struct kvm_lapic *apic)
744 if (__apic_update_ppr(apic, &ppr) &&
745 apic_has_interrupt_for_ppr(apic, ppr) != -1)
746 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
749 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
751 apic_update_ppr(vcpu->arch.apic);
753 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
755 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
757 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
758 apic_update_ppr(apic);
761 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
763 return mda == (apic_x2apic_mode(apic) ?
764 X2APIC_BROADCAST : APIC_BROADCAST);
767 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
769 if (kvm_apic_broadcast(apic, mda))
772 if (apic_x2apic_mode(apic))
773 return mda == kvm_x2apic_id(apic);
776 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
777 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
778 * this allows unique addressing of VCPUs with APIC ID over 0xff.
779 * The 0xff condition is needed because writeable xAPIC ID.
781 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
784 return mda == kvm_xapic_id(apic);
787 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
791 if (kvm_apic_broadcast(apic, mda))
794 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
796 if (apic_x2apic_mode(apic))
797 return ((logical_id >> 16) == (mda >> 16))
798 && (logical_id & mda & 0xffff) != 0;
800 logical_id = GET_APIC_LOGICAL_ID(logical_id);
802 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
804 return (logical_id & mda) != 0;
805 case APIC_DFR_CLUSTER:
806 return ((logical_id >> 4) == (mda >> 4))
807 && (logical_id & mda & 0xf) != 0;
813 /* The KVM local APIC implementation has two quirks:
815 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
816 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
817 * KVM doesn't do that aliasing.
819 * - in-kernel IOAPIC messages have to be delivered directly to
820 * x2APIC, because the kernel does not support interrupt remapping.
821 * In order to support broadcast without interrupt remapping, x2APIC
822 * rewrites the destination of non-IPI messages from APIC_BROADCAST
823 * to X2APIC_BROADCAST.
825 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
826 * important when userspace wants to use x2APIC-format MSIs, because
827 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
829 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
830 struct kvm_lapic *source, struct kvm_lapic *target)
832 bool ipi = source != NULL;
834 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
835 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
836 return X2APIC_BROADCAST;
841 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
842 int shorthand, unsigned int dest, int dest_mode)
844 struct kvm_lapic *target = vcpu->arch.apic;
845 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
849 case APIC_DEST_NOSHORT:
850 if (dest_mode == APIC_DEST_PHYSICAL)
851 return kvm_apic_match_physical_addr(target, mda);
853 return kvm_apic_match_logical_addr(target, mda);
855 return target == source;
856 case APIC_DEST_ALLINC:
858 case APIC_DEST_ALLBUT:
859 return target != source;
864 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
866 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
867 const unsigned long *bitmap, u32 bitmap_size)
872 mod = vector % dest_vcpus;
874 for (i = 0; i <= mod; i++) {
875 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
876 BUG_ON(idx == bitmap_size);
882 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
884 if (!kvm->arch.disabled_lapic_found) {
885 kvm->arch.disabled_lapic_found = true;
887 "Disabled LAPIC found during irq injection\n");
891 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
892 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
894 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
895 if ((irq->dest_id == APIC_BROADCAST &&
896 map->mode != KVM_APIC_MODE_X2APIC))
898 if (irq->dest_id == X2APIC_BROADCAST)
901 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
902 if (irq->dest_id == (x2apic_ipi ?
903 X2APIC_BROADCAST : APIC_BROADCAST))
910 /* Return true if the interrupt can be handled by using *bitmap as index mask
911 * for valid destinations in *dst array.
912 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
913 * Note: we may have zero kvm_lapic destinations when we return true, which
914 * means that the interrupt should be dropped. In this case, *bitmap would be
915 * zero and *dst undefined.
917 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
918 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
919 struct kvm_apic_map *map, struct kvm_lapic ***dst,
920 unsigned long *bitmap)
924 if (irq->shorthand == APIC_DEST_SELF && src) {
928 } else if (irq->shorthand)
931 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
934 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
935 if (irq->dest_id > map->max_apic_id) {
938 u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1);
939 *dst = &map->phys_map[dest_id];
946 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
950 if (!kvm_lowest_prio_delivery(irq))
953 if (!kvm_vector_hashing_enabled()) {
955 for_each_set_bit(i, bitmap, 16) {
960 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
961 (*dst)[lowest]->vcpu) < 0)
968 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
971 if (!(*dst)[lowest]) {
972 kvm_apic_disabled_lapic_found(kvm);
978 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
983 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
984 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
986 struct kvm_apic_map *map;
987 unsigned long bitmap;
988 struct kvm_lapic **dst = NULL;
994 if (irq->shorthand == APIC_DEST_SELF) {
995 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
1000 map = rcu_dereference(kvm->arch.apic_map);
1002 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
1005 for_each_set_bit(i, &bitmap, 16) {
1008 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1017 * This routine tries to handle interrupts in posted mode, here is how
1018 * it deals with different cases:
1019 * - For single-destination interrupts, handle it in posted mode
1020 * - Else if vector hashing is enabled and it is a lowest-priority
1021 * interrupt, handle it in posted mode and use the following mechanism
1022 * to find the destination vCPU.
1023 * 1. For lowest-priority interrupts, store all the possible
1024 * destination vCPUs in an array.
1025 * 2. Use "guest vector % max number of destination vCPUs" to find
1026 * the right destination vCPU in the array for the lowest-priority
1028 * - Otherwise, use remapped mode to inject the interrupt.
1030 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
1031 struct kvm_vcpu **dest_vcpu)
1033 struct kvm_apic_map *map;
1034 unsigned long bitmap;
1035 struct kvm_lapic **dst = NULL;
1042 map = rcu_dereference(kvm->arch.apic_map);
1044 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1045 hweight16(bitmap) == 1) {
1046 unsigned long i = find_first_bit(&bitmap, 16);
1049 *dest_vcpu = dst[i]->vcpu;
1059 * Add a pending IRQ into lapic.
1060 * Return 1 if successfully added and 0 if discarded.
1062 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1063 int vector, int level, int trig_mode,
1064 struct dest_map *dest_map)
1067 struct kvm_vcpu *vcpu = apic->vcpu;
1069 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1071 switch (delivery_mode) {
1072 case APIC_DM_LOWEST:
1073 vcpu->arch.apic_arb_prio++;
1076 if (unlikely(trig_mode && !level))
1079 /* FIXME add logic for vcpu on reset */
1080 if (unlikely(!apic_enabled(apic)))
1086 __set_bit(vcpu->vcpu_id, dest_map->map);
1087 dest_map->vectors[vcpu->vcpu_id] = vector;
1090 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1092 kvm_lapic_set_vector(vector,
1093 apic->regs + APIC_TMR);
1095 kvm_lapic_clear_vector(vector,
1096 apic->regs + APIC_TMR);
1099 static_call(kvm_x86_deliver_interrupt)(apic, delivery_mode,
1105 vcpu->arch.pv.pv_unhalted = 1;
1106 kvm_make_request(KVM_REQ_EVENT, vcpu);
1107 kvm_vcpu_kick(vcpu);
1112 kvm_make_request(KVM_REQ_SMI, vcpu);
1113 kvm_vcpu_kick(vcpu);
1118 kvm_inject_nmi(vcpu);
1119 kvm_vcpu_kick(vcpu);
1123 if (!trig_mode || level) {
1125 /* assumes that there are only KVM_APIC_INIT/SIPI */
1126 apic->pending_events = (1UL << KVM_APIC_INIT);
1127 kvm_make_request(KVM_REQ_EVENT, vcpu);
1128 kvm_vcpu_kick(vcpu);
1132 case APIC_DM_STARTUP:
1134 apic->sipi_vector = vector;
1135 /* make sure sipi_vector is visible for the receiver */
1137 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1138 kvm_make_request(KVM_REQ_EVENT, vcpu);
1139 kvm_vcpu_kick(vcpu);
1142 case APIC_DM_EXTINT:
1144 * Should only be called by kvm_apic_local_deliver() with LVT0,
1145 * before NMI watchdog was enabled. Already handled by
1146 * kvm_apic_accept_pic_intr().
1151 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1159 * This routine identifies the destination vcpus mask meant to receive the
1160 * IOAPIC interrupts. It either uses kvm_apic_map_get_dest_lapic() to find
1161 * out the destination vcpus array and set the bitmap or it traverses to
1162 * each available vcpu to identify the same.
1164 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
1165 unsigned long *vcpu_bitmap)
1167 struct kvm_lapic **dest_vcpu = NULL;
1168 struct kvm_lapic *src = NULL;
1169 struct kvm_apic_map *map;
1170 struct kvm_vcpu *vcpu;
1171 unsigned long bitmap, i;
1176 map = rcu_dereference(kvm->arch.apic_map);
1178 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dest_vcpu,
1181 for_each_set_bit(i, &bitmap, 16) {
1184 vcpu_idx = dest_vcpu[i]->vcpu->vcpu_idx;
1185 __set_bit(vcpu_idx, vcpu_bitmap);
1188 kvm_for_each_vcpu(i, vcpu, kvm) {
1189 if (!kvm_apic_present(vcpu))
1191 if (!kvm_apic_match_dest(vcpu, NULL,
1196 __set_bit(i, vcpu_bitmap);
1202 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1204 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1207 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1209 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1212 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1216 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1217 if (!kvm_ioapic_handles_vector(apic, vector))
1220 /* Request a KVM exit to inform the userspace IOAPIC. */
1221 if (irqchip_split(apic->vcpu->kvm)) {
1222 apic->vcpu->arch.pending_ioapic_eoi = vector;
1223 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1227 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1228 trigger_mode = IOAPIC_LEVEL_TRIG;
1230 trigger_mode = IOAPIC_EDGE_TRIG;
1232 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1235 static int apic_set_eoi(struct kvm_lapic *apic)
1237 int vector = apic_find_highest_isr(apic);
1239 trace_kvm_eoi(apic, vector);
1242 * Not every write EOI will has corresponding ISR,
1243 * one example is when Kernel check timer on setup_IO_APIC
1248 apic_clear_isr(vector, apic);
1249 apic_update_ppr(apic);
1251 if (to_hv_vcpu(apic->vcpu) &&
1252 test_bit(vector, to_hv_synic(apic->vcpu)->vec_bitmap))
1253 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1255 kvm_ioapic_send_eoi(apic, vector);
1256 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1261 * this interface assumes a trap-like exit, which has already finished
1262 * desired side effect including vISR and vPPR update.
1264 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1266 struct kvm_lapic *apic = vcpu->arch.apic;
1268 trace_kvm_eoi(apic, vector);
1270 kvm_ioapic_send_eoi(apic, vector);
1271 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1273 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1275 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high)
1277 struct kvm_lapic_irq irq;
1279 irq.vector = icr_low & APIC_VECTOR_MASK;
1280 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1281 irq.dest_mode = icr_low & APIC_DEST_MASK;
1282 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1283 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1284 irq.shorthand = icr_low & APIC_SHORT_MASK;
1285 irq.msi_redir_hint = false;
1286 if (apic_x2apic_mode(apic))
1287 irq.dest_id = icr_high;
1289 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1291 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1293 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1296 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1298 ktime_t remaining, now;
1302 ASSERT(apic != NULL);
1304 /* if initial count is 0, current count should also be 0 */
1305 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1306 apic->lapic_timer.period == 0)
1310 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1311 if (ktime_to_ns(remaining) < 0)
1314 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1315 tmcct = div64_u64(ns,
1316 (APIC_BUS_CYCLE_NS * apic->divide_count));
1321 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1323 struct kvm_vcpu *vcpu = apic->vcpu;
1324 struct kvm_run *run = vcpu->run;
1326 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1327 run->tpr_access.rip = kvm_rip_read(vcpu);
1328 run->tpr_access.is_write = write;
1331 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1333 if (apic->vcpu->arch.tpr_access_reporting)
1334 __report_tpr_access(apic, write);
1337 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1341 if (offset >= LAPIC_MMIO_LENGTH)
1348 case APIC_TMCCT: /* Timer CCR */
1349 if (apic_lvtt_tscdeadline(apic))
1352 val = apic_get_tmcct(apic);
1355 apic_update_ppr(apic);
1356 val = kvm_lapic_get_reg(apic, offset);
1359 report_tpr_access(apic, false);
1362 val = kvm_lapic_get_reg(apic, offset);
1369 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1371 return container_of(dev, struct kvm_lapic, dev);
1374 #define APIC_REG_MASK(reg) (1ull << ((reg) >> 4))
1375 #define APIC_REGS_MASK(first, count) \
1376 (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1378 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1381 unsigned char alignment = offset & 0xf;
1383 /* this bitmask has a bit cleared for each reserved register */
1384 u64 valid_reg_mask =
1385 APIC_REG_MASK(APIC_ID) |
1386 APIC_REG_MASK(APIC_LVR) |
1387 APIC_REG_MASK(APIC_TASKPRI) |
1388 APIC_REG_MASK(APIC_PROCPRI) |
1389 APIC_REG_MASK(APIC_LDR) |
1390 APIC_REG_MASK(APIC_DFR) |
1391 APIC_REG_MASK(APIC_SPIV) |
1392 APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) |
1393 APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) |
1394 APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) |
1395 APIC_REG_MASK(APIC_ESR) |
1396 APIC_REG_MASK(APIC_ICR) |
1397 APIC_REG_MASK(APIC_ICR2) |
1398 APIC_REG_MASK(APIC_LVTT) |
1399 APIC_REG_MASK(APIC_LVTTHMR) |
1400 APIC_REG_MASK(APIC_LVTPC) |
1401 APIC_REG_MASK(APIC_LVT0) |
1402 APIC_REG_MASK(APIC_LVT1) |
1403 APIC_REG_MASK(APIC_LVTERR) |
1404 APIC_REG_MASK(APIC_TMICT) |
1405 APIC_REG_MASK(APIC_TMCCT) |
1406 APIC_REG_MASK(APIC_TDCR);
1408 /* ARBPRI is not valid on x2APIC */
1409 if (!apic_x2apic_mode(apic))
1410 valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI);
1412 if (alignment + len > 4)
1415 if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset)))
1418 result = __apic_read(apic, offset & ~0xf);
1420 trace_kvm_apic_read(offset, result);
1426 memcpy(data, (char *)&result + alignment, len);
1429 printk(KERN_ERR "Local APIC read with len = %x, "
1430 "should be 1,2, or 4 instead\n", len);
1435 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1437 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1439 return addr >= apic->base_address &&
1440 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1443 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1444 gpa_t address, int len, void *data)
1446 struct kvm_lapic *apic = to_lapic(this);
1447 u32 offset = address - apic->base_address;
1449 if (!apic_mmio_in_range(apic, address))
1452 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1453 if (!kvm_check_has_quirk(vcpu->kvm,
1454 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1457 memset(data, 0xff, len);
1461 kvm_lapic_reg_read(apic, offset, len, data);
1466 static void update_divide_count(struct kvm_lapic *apic)
1468 u32 tmp1, tmp2, tdcr;
1470 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1472 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1473 apic->divide_count = 0x1 << (tmp2 & 0x7);
1476 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1479 * Do not allow the guest to program periodic timers with small
1480 * interval, since the hrtimers are not throttled by the host
1483 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1484 s64 min_period = min_timer_period_us * 1000LL;
1486 if (apic->lapic_timer.period < min_period) {
1487 pr_info_ratelimited(
1488 "kvm: vcpu %i: requested %lld ns "
1489 "lapic timer period limited to %lld ns\n",
1490 apic->vcpu->vcpu_id,
1491 apic->lapic_timer.period, min_period);
1492 apic->lapic_timer.period = min_period;
1497 static void cancel_hv_timer(struct kvm_lapic *apic);
1499 static void cancel_apic_timer(struct kvm_lapic *apic)
1501 hrtimer_cancel(&apic->lapic_timer.timer);
1503 if (apic->lapic_timer.hv_timer_in_use)
1504 cancel_hv_timer(apic);
1508 static void apic_update_lvtt(struct kvm_lapic *apic)
1510 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1511 apic->lapic_timer.timer_mode_mask;
1513 if (apic->lapic_timer.timer_mode != timer_mode) {
1514 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1515 APIC_LVT_TIMER_TSCDEADLINE)) {
1516 cancel_apic_timer(apic);
1517 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1518 apic->lapic_timer.period = 0;
1519 apic->lapic_timer.tscdeadline = 0;
1521 apic->lapic_timer.timer_mode = timer_mode;
1522 limit_periodic_timer_frequency(apic);
1527 * On APICv, this test will cause a busy wait
1528 * during a higher-priority task.
1531 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1533 struct kvm_lapic *apic = vcpu->arch.apic;
1534 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1536 if (kvm_apic_hw_enabled(apic)) {
1537 int vec = reg & APIC_VECTOR_MASK;
1538 void *bitmap = apic->regs + APIC_ISR;
1540 if (vcpu->arch.apicv_active)
1541 bitmap = apic->regs + APIC_IRR;
1543 if (apic_test_vector(vec, bitmap))
1549 static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles)
1551 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;
1554 * If the guest TSC is running at a different ratio than the host, then
1555 * convert the delay to nanoseconds to achieve an accurate delay. Note
1556 * that __delay() uses delay_tsc whenever the hardware has TSC, thus
1557 * always for VMX enabled hardware.
1559 if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) {
1560 __delay(min(guest_cycles,
1561 nsec_to_cycles(vcpu, timer_advance_ns)));
1563 u64 delay_ns = guest_cycles * 1000000ULL;
1564 do_div(delay_ns, vcpu->arch.virtual_tsc_khz);
1565 ndelay(min_t(u32, delay_ns, timer_advance_ns));
1569 static inline void adjust_lapic_timer_advance(struct kvm_vcpu *vcpu,
1570 s64 advance_expire_delta)
1572 struct kvm_lapic *apic = vcpu->arch.apic;
1573 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
1576 /* Do not adjust for tiny fluctuations or large random spikes. */
1577 if (abs(advance_expire_delta) > LAPIC_TIMER_ADVANCE_ADJUST_MAX ||
1578 abs(advance_expire_delta) < LAPIC_TIMER_ADVANCE_ADJUST_MIN)
1582 if (advance_expire_delta < 0) {
1583 ns = -advance_expire_delta * 1000000ULL;
1584 do_div(ns, vcpu->arch.virtual_tsc_khz);
1585 timer_advance_ns -= ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
1588 ns = advance_expire_delta * 1000000ULL;
1589 do_div(ns, vcpu->arch.virtual_tsc_khz);
1590 timer_advance_ns += ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
1593 if (unlikely(timer_advance_ns > LAPIC_TIMER_ADVANCE_NS_MAX))
1594 timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
1595 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
1598 static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1600 struct kvm_lapic *apic = vcpu->arch.apic;
1601 u64 guest_tsc, tsc_deadline;
1603 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1604 apic->lapic_timer.expired_tscdeadline = 0;
1605 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1606 apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline;
1608 if (lapic_timer_advance_dynamic) {
1609 adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta);
1611 * If the timer fired early, reread the TSC to account for the
1612 * overhead of the above adjustment to avoid waiting longer
1613 * than is necessary.
1615 if (guest_tsc < tsc_deadline)
1616 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1619 if (guest_tsc < tsc_deadline)
1620 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
1623 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1625 if (lapic_in_kernel(vcpu) &&
1626 vcpu->arch.apic->lapic_timer.expired_tscdeadline &&
1627 vcpu->arch.apic->lapic_timer.timer_advance_ns &&
1628 lapic_timer_int_injected(vcpu))
1629 __kvm_wait_lapic_expire(vcpu);
1631 EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire);
1633 static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic)
1635 struct kvm_timer *ktimer = &apic->lapic_timer;
1637 kvm_apic_local_deliver(apic, APIC_LVTT);
1638 if (apic_lvtt_tscdeadline(apic)) {
1639 ktimer->tscdeadline = 0;
1640 } else if (apic_lvtt_oneshot(apic)) {
1641 ktimer->tscdeadline = 0;
1642 ktimer->target_expiration = 0;
1646 static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn)
1648 struct kvm_vcpu *vcpu = apic->vcpu;
1649 struct kvm_timer *ktimer = &apic->lapic_timer;
1651 if (atomic_read(&apic->lapic_timer.pending))
1654 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
1655 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1657 if (!from_timer_fn && vcpu->arch.apicv_active) {
1658 WARN_ON(kvm_get_running_vcpu() != vcpu);
1659 kvm_apic_inject_pending_timer_irqs(apic);
1663 if (kvm_use_posted_timer_interrupt(apic->vcpu)) {
1665 * Ensure the guest's timer has truly expired before posting an
1666 * interrupt. Open code the relevant checks to avoid querying
1667 * lapic_timer_int_injected(), which will be false since the
1668 * interrupt isn't yet injected. Waiting until after injecting
1669 * is not an option since that won't help a posted interrupt.
1671 if (vcpu->arch.apic->lapic_timer.expired_tscdeadline &&
1672 vcpu->arch.apic->lapic_timer.timer_advance_ns)
1673 __kvm_wait_lapic_expire(vcpu);
1674 kvm_apic_inject_pending_timer_irqs(apic);
1678 atomic_inc(&apic->lapic_timer.pending);
1679 kvm_make_request(KVM_REQ_UNBLOCK, vcpu);
1681 kvm_vcpu_kick(vcpu);
1684 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1686 struct kvm_timer *ktimer = &apic->lapic_timer;
1687 u64 guest_tsc, tscdeadline = ktimer->tscdeadline;
1690 struct kvm_vcpu *vcpu = apic->vcpu;
1691 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1692 unsigned long flags;
1695 if (unlikely(!tscdeadline || !this_tsc_khz))
1698 local_irq_save(flags);
1701 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1703 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1704 do_div(ns, this_tsc_khz);
1706 if (likely(tscdeadline > guest_tsc) &&
1707 likely(ns > apic->lapic_timer.timer_advance_ns)) {
1708 expire = ktime_add_ns(now, ns);
1709 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns);
1710 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD);
1712 apic_timer_expired(apic, false);
1714 local_irq_restore(flags);
1717 static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict)
1719 return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count;
1722 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1724 ktime_t now, remaining;
1725 u64 ns_remaining_old, ns_remaining_new;
1727 apic->lapic_timer.period =
1728 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));
1729 limit_periodic_timer_frequency(apic);
1732 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1733 if (ktime_to_ns(remaining) < 0)
1736 ns_remaining_old = ktime_to_ns(remaining);
1737 ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1738 apic->divide_count, old_divisor);
1740 apic->lapic_timer.tscdeadline +=
1741 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1742 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1743 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1746 static bool set_target_expiration(struct kvm_lapic *apic, u32 count_reg)
1753 apic->lapic_timer.period =
1754 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));
1756 if (!apic->lapic_timer.period) {
1757 apic->lapic_timer.tscdeadline = 0;
1761 limit_periodic_timer_frequency(apic);
1762 deadline = apic->lapic_timer.period;
1764 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1765 if (unlikely(count_reg != APIC_TMICT)) {
1766 deadline = tmict_to_ns(apic,
1767 kvm_lapic_get_reg(apic, count_reg));
1768 if (unlikely(deadline <= 0))
1769 deadline = apic->lapic_timer.period;
1770 else if (unlikely(deadline > apic->lapic_timer.period)) {
1771 pr_info_ratelimited(
1772 "kvm: vcpu %i: requested lapic timer restore with "
1773 "starting count register %#x=%u (%lld ns) > initial count (%lld ns). "
1774 "Using initial count to start timer.\n",
1775 apic->vcpu->vcpu_id,
1777 kvm_lapic_get_reg(apic, count_reg),
1778 deadline, apic->lapic_timer.period);
1779 kvm_lapic_set_reg(apic, count_reg, 0);
1780 deadline = apic->lapic_timer.period;
1785 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1786 nsec_to_cycles(apic->vcpu, deadline);
1787 apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline);
1792 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1794 ktime_t now = ktime_get();
1799 * Synchronize both deadlines to the same time source or
1800 * differences in the periods (caused by differences in the
1801 * underlying clocks or numerical approximation errors) will
1802 * cause the two to drift apart over time as the errors
1805 apic->lapic_timer.target_expiration =
1806 ktime_add_ns(apic->lapic_timer.target_expiration,
1807 apic->lapic_timer.period);
1808 delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1809 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1810 nsec_to_cycles(apic->vcpu, delta);
1813 static void start_sw_period(struct kvm_lapic *apic)
1815 if (!apic->lapic_timer.period)
1818 if (ktime_after(ktime_get(),
1819 apic->lapic_timer.target_expiration)) {
1820 apic_timer_expired(apic, false);
1822 if (apic_lvtt_oneshot(apic))
1825 advance_periodic_target_expiration(apic);
1828 hrtimer_start(&apic->lapic_timer.timer,
1829 apic->lapic_timer.target_expiration,
1830 HRTIMER_MODE_ABS_HARD);
1833 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1835 if (!lapic_in_kernel(vcpu))
1838 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1840 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1842 static void cancel_hv_timer(struct kvm_lapic *apic)
1844 WARN_ON(preemptible());
1845 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1846 static_call(kvm_x86_cancel_hv_timer)(apic->vcpu);
1847 apic->lapic_timer.hv_timer_in_use = false;
1850 static bool start_hv_timer(struct kvm_lapic *apic)
1852 struct kvm_timer *ktimer = &apic->lapic_timer;
1853 struct kvm_vcpu *vcpu = apic->vcpu;
1856 WARN_ON(preemptible());
1857 if (!kvm_can_use_hv_timer(vcpu))
1860 if (!ktimer->tscdeadline)
1863 if (static_call(kvm_x86_set_hv_timer)(vcpu, ktimer->tscdeadline, &expired))
1866 ktimer->hv_timer_in_use = true;
1867 hrtimer_cancel(&ktimer->timer);
1870 * To simplify handling the periodic timer, leave the hv timer running
1871 * even if the deadline timer has expired, i.e. rely on the resulting
1872 * VM-Exit to recompute the periodic timer's target expiration.
1874 if (!apic_lvtt_period(apic)) {
1876 * Cancel the hv timer if the sw timer fired while the hv timer
1877 * was being programmed, or if the hv timer itself expired.
1879 if (atomic_read(&ktimer->pending)) {
1880 cancel_hv_timer(apic);
1881 } else if (expired) {
1882 apic_timer_expired(apic, false);
1883 cancel_hv_timer(apic);
1887 trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use);
1892 static void start_sw_timer(struct kvm_lapic *apic)
1894 struct kvm_timer *ktimer = &apic->lapic_timer;
1896 WARN_ON(preemptible());
1897 if (apic->lapic_timer.hv_timer_in_use)
1898 cancel_hv_timer(apic);
1899 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1902 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1903 start_sw_period(apic);
1904 else if (apic_lvtt_tscdeadline(apic))
1905 start_sw_tscdeadline(apic);
1906 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1909 static void restart_apic_timer(struct kvm_lapic *apic)
1913 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending))
1916 if (!start_hv_timer(apic))
1917 start_sw_timer(apic);
1922 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1924 struct kvm_lapic *apic = vcpu->arch.apic;
1927 /* If the preempt notifier has already run, it also called apic_timer_expired */
1928 if (!apic->lapic_timer.hv_timer_in_use)
1930 WARN_ON(kvm_vcpu_is_blocking(vcpu));
1931 apic_timer_expired(apic, false);
1932 cancel_hv_timer(apic);
1934 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1935 advance_periodic_target_expiration(apic);
1936 restart_apic_timer(apic);
1941 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1943 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1945 restart_apic_timer(vcpu->arch.apic);
1948 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1950 struct kvm_lapic *apic = vcpu->arch.apic;
1953 /* Possibly the TSC deadline timer is not enabled yet */
1954 if (apic->lapic_timer.hv_timer_in_use)
1955 start_sw_timer(apic);
1959 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1961 struct kvm_lapic *apic = vcpu->arch.apic;
1963 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1964 restart_apic_timer(apic);
1967 static void __start_apic_timer(struct kvm_lapic *apic, u32 count_reg)
1969 atomic_set(&apic->lapic_timer.pending, 0);
1971 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1972 && !set_target_expiration(apic, count_reg))
1975 restart_apic_timer(apic);
1978 static void start_apic_timer(struct kvm_lapic *apic)
1980 __start_apic_timer(apic, APIC_TMICT);
1983 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1985 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1987 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1988 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1989 if (lvt0_in_nmi_mode) {
1990 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1992 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1996 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
2000 trace_kvm_apic_write(reg, val);
2003 case APIC_ID: /* Local APIC ID */
2004 if (!apic_x2apic_mode(apic))
2005 kvm_apic_set_xapic_id(apic, val >> 24);
2011 report_tpr_access(apic, true);
2012 apic_set_tpr(apic, val & 0xff);
2020 if (!apic_x2apic_mode(apic))
2021 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
2027 if (!apic_x2apic_mode(apic))
2028 kvm_apic_set_dfr(apic, val | 0x0FFFFFFF);
2035 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
2036 mask |= APIC_SPIV_DIRECTED_EOI;
2037 apic_set_spiv(apic, val & mask);
2038 if (!(val & APIC_SPIV_APIC_ENABLED)) {
2042 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
2043 lvt_val = kvm_lapic_get_reg(apic,
2044 APIC_LVTT + 0x10 * i);
2045 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
2046 lvt_val | APIC_LVT_MASKED);
2048 apic_update_lvtt(apic);
2049 atomic_set(&apic->lapic_timer.pending, 0);
2055 /* No delay here, so we always clear the pending bit */
2057 kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2));
2058 kvm_lapic_set_reg(apic, APIC_ICR, val);
2062 if (!apic_x2apic_mode(apic))
2064 kvm_lapic_set_reg(apic, APIC_ICR2, val);
2068 apic_manage_nmi_watchdog(apic, val);
2074 /* TODO: Check vector */
2078 if (!kvm_apic_sw_enabled(apic))
2079 val |= APIC_LVT_MASKED;
2080 size = ARRAY_SIZE(apic_lvt_mask);
2081 index = array_index_nospec(
2082 (reg - APIC_LVTT) >> 4, size);
2083 val &= apic_lvt_mask[index];
2084 kvm_lapic_set_reg(apic, reg, val);
2089 if (!kvm_apic_sw_enabled(apic))
2090 val |= APIC_LVT_MASKED;
2091 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
2092 kvm_lapic_set_reg(apic, APIC_LVTT, val);
2093 apic_update_lvtt(apic);
2097 if (apic_lvtt_tscdeadline(apic))
2100 cancel_apic_timer(apic);
2101 kvm_lapic_set_reg(apic, APIC_TMICT, val);
2102 start_apic_timer(apic);
2106 uint32_t old_divisor = apic->divide_count;
2108 kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb);
2109 update_divide_count(apic);
2110 if (apic->divide_count != old_divisor &&
2111 apic->lapic_timer.period) {
2112 hrtimer_cancel(&apic->lapic_timer.timer);
2113 update_target_expiration(apic, old_divisor);
2114 restart_apic_timer(apic);
2119 if (apic_x2apic_mode(apic) && val != 0)
2124 if (apic_x2apic_mode(apic)) {
2125 kvm_lapic_reg_write(apic, APIC_ICR,
2126 APIC_DEST_SELF | (val & APIC_VECTOR_MASK));
2135 kvm_recalculate_apic_map(apic->vcpu->kvm);
2139 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
2141 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
2142 gpa_t address, int len, const void *data)
2144 struct kvm_lapic *apic = to_lapic(this);
2145 unsigned int offset = address - apic->base_address;
2148 if (!apic_mmio_in_range(apic, address))
2151 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
2152 if (!kvm_check_has_quirk(vcpu->kvm,
2153 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
2160 * APIC register must be aligned on 128-bits boundary.
2161 * 32/64/128 bits registers must be accessed thru 32 bits.
2164 if (len != 4 || (offset & 0xf))
2169 kvm_lapic_reg_write(apic, offset & 0xff0, val);
2174 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
2176 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
2178 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
2180 /* emulate APIC access in a trap manner */
2181 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
2185 /* hw has done the conditional check and inst decode */
2188 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
2190 /* TODO: optimize to just emulate side effect w/o one more write */
2191 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
2193 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2195 void kvm_free_lapic(struct kvm_vcpu *vcpu)
2197 struct kvm_lapic *apic = vcpu->arch.apic;
2199 if (!vcpu->arch.apic)
2202 hrtimer_cancel(&apic->lapic_timer.timer);
2204 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2205 static_branch_slow_dec_deferred(&apic_hw_disabled);
2207 if (!apic->sw_enabled)
2208 static_branch_slow_dec_deferred(&apic_sw_disabled);
2211 free_page((unsigned long)apic->regs);
2217 *----------------------------------------------------------------------
2219 *----------------------------------------------------------------------
2221 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2223 struct kvm_lapic *apic = vcpu->arch.apic;
2225 if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic))
2228 return apic->lapic_timer.tscdeadline;
2231 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2233 struct kvm_lapic *apic = vcpu->arch.apic;
2235 if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic))
2238 hrtimer_cancel(&apic->lapic_timer.timer);
2239 apic->lapic_timer.tscdeadline = data;
2240 start_apic_timer(apic);
2243 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2245 struct kvm_lapic *apic = vcpu->arch.apic;
2247 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
2248 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
2251 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2255 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2257 return (tpr & 0xf0) >> 4;
2260 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2262 u64 old_value = vcpu->arch.apic_base;
2263 struct kvm_lapic *apic = vcpu->arch.apic;
2265 vcpu->arch.apic_base = value;
2267 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2268 kvm_update_cpuid_runtime(vcpu);
2273 /* update jump label if enable bit changes */
2274 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2275 if (value & MSR_IA32_APICBASE_ENABLE) {
2276 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2277 static_branch_slow_dec_deferred(&apic_hw_disabled);
2278 /* Check if there are APF page ready requests pending */
2279 kvm_make_request(KVM_REQ_APF_READY, vcpu);
2281 static_branch_inc(&apic_hw_disabled.key);
2282 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
2286 if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2287 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2289 if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2290 static_call(kvm_x86_set_virtual_apic_mode)(vcpu);
2292 apic->base_address = apic->vcpu->arch.apic_base &
2293 MSR_IA32_APICBASE_BASE;
2295 if ((value & MSR_IA32_APICBASE_ENABLE) &&
2296 apic->base_address != APIC_DEFAULT_PHYS_BASE)
2297 pr_warn_once("APIC base relocation is unsupported by KVM");
2300 void kvm_apic_update_apicv(struct kvm_vcpu *vcpu)
2302 struct kvm_lapic *apic = vcpu->arch.apic;
2304 if (vcpu->arch.apicv_active) {
2305 /* irr_pending is always true when apicv is activated. */
2306 apic->irr_pending = true;
2307 apic->isr_count = 1;
2310 * Don't clear irr_pending, searching the IRR can race with
2311 * updates from the CPU as APICv is still active from hardware's
2312 * perspective. The flag will be cleared as appropriate when
2313 * KVM injects the interrupt.
2315 apic->isr_count = count_vectors(apic->regs + APIC_ISR);
2318 EXPORT_SYMBOL_GPL(kvm_apic_update_apicv);
2320 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2322 struct kvm_lapic *apic = vcpu->arch.apic;
2327 msr_val = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
2328 if (kvm_vcpu_is_reset_bsp(vcpu))
2329 msr_val |= MSR_IA32_APICBASE_BSP;
2330 kvm_lapic_set_base(vcpu, msr_val);
2336 /* Stop the timer in case it's a reset to an active apic */
2337 hrtimer_cancel(&apic->lapic_timer.timer);
2339 /* The xAPIC ID is set at RESET even if the APIC was already enabled. */
2341 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2342 kvm_apic_set_version(apic->vcpu);
2344 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2345 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2346 apic_update_lvtt(apic);
2347 if (kvm_vcpu_is_reset_bsp(vcpu) &&
2348 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2349 kvm_lapic_set_reg(apic, APIC_LVT0,
2350 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2351 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2353 kvm_apic_set_dfr(apic, 0xffffffffU);
2354 apic_set_spiv(apic, 0xff);
2355 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2356 if (!apic_x2apic_mode(apic))
2357 kvm_apic_set_ldr(apic, 0);
2358 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2359 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2360 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2361 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2362 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2363 for (i = 0; i < 8; i++) {
2364 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2365 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2366 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2368 kvm_apic_update_apicv(vcpu);
2369 apic->highest_isr_cache = -1;
2370 update_divide_count(apic);
2371 atomic_set(&apic->lapic_timer.pending, 0);
2373 vcpu->arch.pv_eoi.msr_val = 0;
2374 apic_update_ppr(apic);
2375 if (vcpu->arch.apicv_active) {
2376 static_call(kvm_x86_apicv_post_state_restore)(vcpu);
2377 static_call(kvm_x86_hwapic_irr_update)(vcpu, -1);
2378 static_call(kvm_x86_hwapic_isr_update)(vcpu, -1);
2381 vcpu->arch.apic_arb_prio = 0;
2382 vcpu->arch.apic_attention = 0;
2384 kvm_recalculate_apic_map(vcpu->kvm);
2388 *----------------------------------------------------------------------
2390 *----------------------------------------------------------------------
2393 static bool lapic_is_periodic(struct kvm_lapic *apic)
2395 return apic_lvtt_period(apic);
2398 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2400 struct kvm_lapic *apic = vcpu->arch.apic;
2402 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2403 return atomic_read(&apic->lapic_timer.pending);
2408 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2410 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2411 int vector, mode, trig_mode;
2413 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2414 vector = reg & APIC_VECTOR_MASK;
2415 mode = reg & APIC_MODE_MASK;
2416 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2417 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2423 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2425 struct kvm_lapic *apic = vcpu->arch.apic;
2428 kvm_apic_local_deliver(apic, APIC_LVT0);
2431 static const struct kvm_io_device_ops apic_mmio_ops = {
2432 .read = apic_mmio_read,
2433 .write = apic_mmio_write,
2436 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2438 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2439 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2441 apic_timer_expired(apic, true);
2443 if (lapic_is_periodic(apic)) {
2444 advance_periodic_target_expiration(apic);
2445 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2446 return HRTIMER_RESTART;
2448 return HRTIMER_NORESTART;
2451 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns)
2453 struct kvm_lapic *apic;
2455 ASSERT(vcpu != NULL);
2457 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT);
2461 vcpu->arch.apic = apic;
2463 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
2465 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2467 goto nomem_free_apic;
2471 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2472 HRTIMER_MODE_ABS_HARD);
2473 apic->lapic_timer.timer.function = apic_timer_fn;
2474 if (timer_advance_ns == -1) {
2475 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
2476 lapic_timer_advance_dynamic = true;
2478 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
2479 lapic_timer_advance_dynamic = false;
2483 * Stuff the APIC ENABLE bit in lieu of temporarily incrementing
2484 * apic_hw_disabled; the full RESET value is set by kvm_lapic_reset().
2486 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2487 static_branch_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2488 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2493 vcpu->arch.apic = NULL;
2498 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2500 struct kvm_lapic *apic = vcpu->arch.apic;
2503 if (!kvm_apic_present(vcpu))
2506 __apic_update_ppr(apic, &ppr);
2507 return apic_has_interrupt_for_ppr(apic, ppr);
2509 EXPORT_SYMBOL_GPL(kvm_apic_has_interrupt);
2511 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2513 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2515 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2517 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2518 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2523 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2525 struct kvm_lapic *apic = vcpu->arch.apic;
2527 if (atomic_read(&apic->lapic_timer.pending) > 0) {
2528 kvm_apic_inject_pending_timer_irqs(apic);
2529 atomic_set(&apic->lapic_timer.pending, 0);
2533 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2535 int vector = kvm_apic_has_interrupt(vcpu);
2536 struct kvm_lapic *apic = vcpu->arch.apic;
2543 * We get here even with APIC virtualization enabled, if doing
2544 * nested virtualization and L1 runs with the "acknowledge interrupt
2545 * on exit" mode. Then we cannot inject the interrupt via RVI,
2546 * because the process would deliver it through the IDT.
2549 apic_clear_irr(vector, apic);
2550 if (to_hv_vcpu(vcpu) && test_bit(vector, to_hv_synic(vcpu)->auto_eoi_bitmap)) {
2552 * For auto-EOI interrupts, there might be another pending
2553 * interrupt above PPR, so check whether to raise another
2556 apic_update_ppr(apic);
2559 * For normal interrupts, PPR has been raised and there cannot
2560 * be a higher-priority pending interrupt---except if there was
2561 * a concurrent interrupt injection, but that would have
2562 * triggered KVM_REQ_EVENT already.
2564 apic_set_isr(vector, apic);
2565 __apic_update_ppr(apic, &ppr);
2571 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2572 struct kvm_lapic_state *s, bool set)
2574 if (apic_x2apic_mode(vcpu->arch.apic)) {
2575 u32 *id = (u32 *)(s->regs + APIC_ID);
2576 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2578 if (vcpu->kvm->arch.x2apic_format) {
2579 if (*id != vcpu->vcpu_id)
2588 /* In x2APIC mode, the LDR is fixed and based on the id */
2590 *ldr = kvm_apic_calc_x2apic_ldr(*id);
2596 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2598 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2601 * Get calculated timer current count for remaining timer period (if
2602 * any) and store it in the returned register set.
2604 __kvm_lapic_set_reg(s->regs, APIC_TMCCT,
2605 __apic_read(vcpu->arch.apic, APIC_TMCCT));
2607 return kvm_apic_state_fixup(vcpu, s, false);
2610 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2612 struct kvm_lapic *apic = vcpu->arch.apic;
2615 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2616 /* set SPIV separately to get count of SW disabled APICs right */
2617 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2619 r = kvm_apic_state_fixup(vcpu, s, true);
2621 kvm_recalculate_apic_map(vcpu->kvm);
2624 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
2626 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
2627 kvm_recalculate_apic_map(vcpu->kvm);
2628 kvm_apic_set_version(vcpu);
2630 apic_update_ppr(apic);
2631 cancel_apic_timer(apic);
2632 apic->lapic_timer.expired_tscdeadline = 0;
2633 apic_update_lvtt(apic);
2634 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2635 update_divide_count(apic);
2636 __start_apic_timer(apic, APIC_TMCCT);
2637 kvm_lapic_set_reg(apic, APIC_TMCCT, 0);
2638 kvm_apic_update_apicv(vcpu);
2639 apic->highest_isr_cache = -1;
2640 if (vcpu->arch.apicv_active) {
2641 static_call(kvm_x86_apicv_post_state_restore)(vcpu);
2642 static_call(kvm_x86_hwapic_irr_update)(vcpu,
2643 apic_find_highest_irr(apic));
2644 static_call(kvm_x86_hwapic_isr_update)(vcpu,
2645 apic_find_highest_isr(apic));
2647 kvm_make_request(KVM_REQ_EVENT, vcpu);
2648 if (ioapic_in_kernel(vcpu->kvm))
2649 kvm_rtc_eoi_tracking_restore_one(vcpu);
2651 vcpu->arch.apic_arb_prio = 0;
2656 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2658 struct hrtimer *timer;
2660 if (!lapic_in_kernel(vcpu) ||
2661 kvm_can_post_timer_interrupt(vcpu))
2664 timer = &vcpu->arch.apic->lapic_timer.timer;
2665 if (hrtimer_cancel(timer))
2666 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_HARD);
2670 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2672 * Detect whether guest triggered PV EOI since the
2673 * last entry. If yes, set EOI on guests's behalf.
2674 * Clear PV EOI in guest memory in any case.
2676 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2677 struct kvm_lapic *apic)
2681 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2682 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2684 * KVM_APIC_PV_EOI_PENDING is unset:
2685 * -> host disabled PV EOI.
2686 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2687 * -> host enabled PV EOI, guest did not execute EOI yet.
2688 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2689 * -> host enabled PV EOI, guest executed EOI.
2691 BUG_ON(!pv_eoi_enabled(vcpu));
2693 if (pv_eoi_test_and_clr_pending(vcpu))
2695 vector = apic_set_eoi(apic);
2696 trace_kvm_pv_eoi(apic, vector);
2699 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2703 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2704 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2706 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2709 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2713 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2717 * apic_sync_pv_eoi_to_guest - called before vmentry
2719 * Detect whether it's safe to enable PV EOI and
2722 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2723 struct kvm_lapic *apic)
2725 if (!pv_eoi_enabled(vcpu) ||
2726 /* IRR set or many bits in ISR: could be nested. */
2727 apic->irr_pending ||
2728 /* Cache not set: could be safe but we don't bother. */
2729 apic->highest_isr_cache == -1 ||
2730 /* Need EOI to update ioapic. */
2731 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2733 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2734 * so we need not do anything here.
2739 pv_eoi_set_pending(apic->vcpu);
2742 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2745 int max_irr, max_isr;
2746 struct kvm_lapic *apic = vcpu->arch.apic;
2748 apic_sync_pv_eoi_to_guest(vcpu, apic);
2750 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2753 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2754 max_irr = apic_find_highest_irr(apic);
2757 max_isr = apic_find_highest_isr(apic);
2760 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2762 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2766 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2769 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2770 &vcpu->arch.apic->vapic_cache,
2771 vapic_addr, sizeof(u32)))
2773 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2775 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2778 vcpu->arch.apic->vapic_addr = vapic_addr;
2782 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2784 struct kvm_lapic *apic = vcpu->arch.apic;
2785 u32 reg = (msr - APIC_BASE_MSR) << 4;
2787 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2790 if (reg == APIC_ICR2)
2793 /* if this is ICR write vector before command */
2794 if (reg == APIC_ICR)
2795 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2796 return kvm_lapic_reg_write(apic, reg, (u32)data);
2799 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2801 struct kvm_lapic *apic = vcpu->arch.apic;
2802 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2804 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2807 if (reg == APIC_DFR || reg == APIC_ICR2)
2810 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2812 if (reg == APIC_ICR)
2813 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2815 *data = (((u64)high) << 32) | low;
2820 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2822 struct kvm_lapic *apic = vcpu->arch.apic;
2824 if (!lapic_in_kernel(vcpu))
2827 /* if this is ICR write vector before command */
2828 if (reg == APIC_ICR)
2829 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2830 return kvm_lapic_reg_write(apic, reg, (u32)data);
2833 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2835 struct kvm_lapic *apic = vcpu->arch.apic;
2838 if (!lapic_in_kernel(vcpu))
2841 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2843 if (reg == APIC_ICR)
2844 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2846 *data = (((u64)high) << 32) | low;
2851 int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
2853 u64 addr = data & ~KVM_MSR_ENABLED;
2854 struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2855 unsigned long new_len;
2858 if (!IS_ALIGNED(addr, 4))
2861 if (data & KVM_MSR_ENABLED) {
2862 if (addr == ghc->gpa && len <= ghc->len)
2867 ret = kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
2872 vcpu->arch.pv_eoi.msr_val = data;
2877 int kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2879 struct kvm_lapic *apic = vcpu->arch.apic;
2884 if (!lapic_in_kernel(vcpu))
2888 * Read pending events before calling the check_events
2891 pe = smp_load_acquire(&apic->pending_events);
2895 if (is_guest_mode(vcpu)) {
2896 r = kvm_check_nested_events(vcpu);
2898 return r == -EBUSY ? 0 : r;
2900 * If an event has happened and caused a vmexit,
2901 * we know INITs are latched and therefore
2902 * we will not incorrectly deliver an APIC
2903 * event instead of a vmexit.
2908 * INITs are latched while CPU is in specific states
2909 * (SMM, VMX root mode, SVM with GIF=0).
2910 * Because a CPU cannot be in these states immediately
2911 * after it has processed an INIT signal (and thus in
2912 * KVM_MP_STATE_INIT_RECEIVED state), just eat SIPIs
2913 * and leave the INIT pending.
2915 if (kvm_vcpu_latch_init(vcpu)) {
2916 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2917 if (test_bit(KVM_APIC_SIPI, &pe))
2918 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2922 if (test_bit(KVM_APIC_INIT, &pe)) {
2923 clear_bit(KVM_APIC_INIT, &apic->pending_events);
2924 kvm_vcpu_reset(vcpu, true);
2925 if (kvm_vcpu_is_bsp(apic->vcpu))
2926 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2928 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2930 if (test_bit(KVM_APIC_SIPI, &pe)) {
2931 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2932 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2933 /* evaluate pending_events before reading the vector */
2935 sipi_vector = apic->sipi_vector;
2936 kvm_x86_ops.vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2937 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2943 void kvm_lapic_exit(void)
2945 static_key_deferred_flush(&apic_hw_disabled);
2946 WARN_ON(static_branch_unlikely(&apic_hw_disabled.key));
2947 static_key_deferred_flush(&apic_sw_disabled);
2948 WARN_ON(static_branch_unlikely(&apic_sw_disabled.key));