1 // SPDX-License-Identifier: GPL-2.0-only
4 * Local APIC virtualization
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2007 Novell
8 * Copyright (C) 2007 Intel
9 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
12 * Dor Laor <dor.laor@qumranet.com>
13 * Gregory Haskins <ghaskins@novell.com>
14 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
16 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
19 #include <linux/kvm_host.h>
20 #include <linux/kvm.h>
22 #include <linux/highmem.h>
23 #include <linux/smp.h>
24 #include <linux/hrtimer.h>
26 #include <linux/export.h>
27 #include <linux/math64.h>
28 #include <linux/slab.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/delay.h>
35 #include <linux/atomic.h>
36 #include <linux/jump_label.h>
37 #include "kvm_cache_regs.h"
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #define mod_64(x, y) ((x) % (y))
55 /* 14 is the version for Xeon and Pentium 8.4.8*/
56 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
57 #define LAPIC_MMIO_LENGTH (1 << 12)
58 /* followed define is not in apicdef.h */
59 #define MAX_APIC_VECTOR 256
60 #define APIC_VECTORS_PER_REG 32
62 #define APIC_BROADCAST 0xFF
63 #define X2APIC_BROADCAST 0xFFFFFFFFul
65 static bool lapic_timer_advance_dynamic __read_mostly;
66 #define LAPIC_TIMER_ADVANCE_ADJUST_MIN 100 /* clock cycles */
67 #define LAPIC_TIMER_ADVANCE_ADJUST_MAX 10000 /* clock cycles */
68 #define LAPIC_TIMER_ADVANCE_NS_INIT 1000
69 #define LAPIC_TIMER_ADVANCE_NS_MAX 5000
70 /* step-by-step approximation to mitigate fluctuation */
71 #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
73 static inline int apic_test_vector(int vec, void *bitmap)
75 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
78 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
80 struct kvm_lapic *apic = vcpu->arch.apic;
82 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
83 apic_test_vector(vector, apic->regs + APIC_IRR);
86 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
88 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
91 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
93 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
96 struct static_key_deferred apic_hw_disabled __read_mostly;
97 struct static_key_deferred apic_sw_disabled __read_mostly;
99 static inline int apic_enabled(struct kvm_lapic *apic)
101 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
105 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
108 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
109 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
111 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
113 return apic->vcpu->vcpu_id;
116 bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu)
118 return pi_inject_timer && kvm_vcpu_apicv_active(vcpu);
120 EXPORT_SYMBOL_GPL(kvm_can_post_timer_interrupt);
122 static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu)
124 return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE;
127 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
128 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
130 case KVM_APIC_MODE_X2APIC: {
131 u32 offset = (dest_id >> 16) * 16;
132 u32 max_apic_id = map->max_apic_id;
134 if (offset <= max_apic_id) {
135 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
137 offset = array_index_nospec(offset, map->max_apic_id + 1);
138 *cluster = &map->phys_map[offset];
139 *mask = dest_id & (0xffff >> (16 - cluster_size));
146 case KVM_APIC_MODE_XAPIC_FLAT:
147 *cluster = map->xapic_flat_map;
148 *mask = dest_id & 0xff;
150 case KVM_APIC_MODE_XAPIC_CLUSTER:
151 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
152 *mask = dest_id & 0xf;
160 static void kvm_apic_map_free(struct rcu_head *rcu)
162 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
167 static void recalculate_apic_map(struct kvm *kvm)
169 struct kvm_apic_map *new, *old = NULL;
170 struct kvm_vcpu *vcpu;
172 u32 max_id = 255; /* enough space for any xAPIC ID */
174 mutex_lock(&kvm->arch.apic_map_lock);
176 kvm_for_each_vcpu(i, vcpu, kvm)
177 if (kvm_apic_present(vcpu))
178 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
180 new = kvzalloc(sizeof(struct kvm_apic_map) +
181 sizeof(struct kvm_lapic *) * ((u64)max_id + 1),
187 new->max_apic_id = max_id;
189 kvm_for_each_vcpu(i, vcpu, kvm) {
190 struct kvm_lapic *apic = vcpu->arch.apic;
191 struct kvm_lapic **cluster;
197 if (!kvm_apic_present(vcpu))
200 xapic_id = kvm_xapic_id(apic);
201 x2apic_id = kvm_x2apic_id(apic);
203 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
204 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
205 x2apic_id <= new->max_apic_id)
206 new->phys_map[x2apic_id] = apic;
208 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
209 * prevent them from masking VCPUs with APIC ID <= 0xff.
211 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
212 new->phys_map[xapic_id] = apic;
214 if (!kvm_apic_sw_enabled(apic))
217 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
219 if (apic_x2apic_mode(apic)) {
220 new->mode |= KVM_APIC_MODE_X2APIC;
222 ldr = GET_APIC_LOGICAL_ID(ldr);
223 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
224 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
226 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
229 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
233 cluster[ffs(mask) - 1] = apic;
236 old = rcu_dereference_protected(kvm->arch.apic_map,
237 lockdep_is_held(&kvm->arch.apic_map_lock));
238 rcu_assign_pointer(kvm->arch.apic_map, new);
239 mutex_unlock(&kvm->arch.apic_map_lock);
242 call_rcu(&old->rcu, kvm_apic_map_free);
244 kvm_make_scan_ioapic_request(kvm);
247 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
249 bool enabled = val & APIC_SPIV_APIC_ENABLED;
251 kvm_lapic_set_reg(apic, APIC_SPIV, val);
253 if (enabled != apic->sw_enabled) {
254 apic->sw_enabled = enabled;
256 static_key_slow_dec_deferred(&apic_sw_disabled);
258 static_key_slow_inc(&apic_sw_disabled.key);
260 recalculate_apic_map(apic->vcpu->kvm);
264 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
266 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
267 recalculate_apic_map(apic->vcpu->kvm);
270 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
272 kvm_lapic_set_reg(apic, APIC_LDR, id);
273 recalculate_apic_map(apic->vcpu->kvm);
276 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
278 return ((id >> 4) << 16) | (1 << (id & 0xf));
281 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
283 u32 ldr = kvm_apic_calc_x2apic_ldr(id);
285 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
287 kvm_lapic_set_reg(apic, APIC_ID, id);
288 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
289 recalculate_apic_map(apic->vcpu->kvm);
292 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
294 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
297 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
299 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
302 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
304 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
307 static inline int apic_lvtt_period(struct kvm_lapic *apic)
309 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
312 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
314 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
317 static inline int apic_lvt_nmi_mode(u32 lvt_val)
319 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
322 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
324 struct kvm_lapic *apic = vcpu->arch.apic;
325 struct kvm_cpuid_entry2 *feat;
326 u32 v = APIC_VERSION;
328 if (!lapic_in_kernel(vcpu))
332 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
333 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
334 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
335 * version first and level-triggered interrupts never get EOIed in
338 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
339 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
340 !ioapic_in_kernel(vcpu->kvm))
341 v |= APIC_LVR_DIRECTED_EOI;
342 kvm_lapic_set_reg(apic, APIC_LVR, v);
345 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
346 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
347 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
348 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
349 LINT_MASK, LINT_MASK, /* LVT0-1 */
350 LVT_MASK /* LVTERR */
353 static int find_highest_vector(void *bitmap)
358 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
359 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
360 reg = bitmap + REG_POS(vec);
362 return __fls(*reg) + vec;
368 static u8 count_vectors(void *bitmap)
374 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
375 reg = bitmap + REG_POS(vec);
376 count += hweight32(*reg);
382 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
385 u32 pir_val, irr_val, prev_irr_val;
388 max_updated_irr = -1;
391 for (i = vec = 0; i <= 7; i++, vec += 32) {
392 pir_val = READ_ONCE(pir[i]);
393 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
395 prev_irr_val = irr_val;
396 irr_val |= xchg(&pir[i], 0);
397 *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
398 if (prev_irr_val != irr_val) {
400 __fls(irr_val ^ prev_irr_val) + vec;
404 *max_irr = __fls(irr_val) + vec;
407 return ((max_updated_irr != -1) &&
408 (max_updated_irr == *max_irr));
410 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
412 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
414 struct kvm_lapic *apic = vcpu->arch.apic;
416 return __kvm_apic_update_irr(pir, apic->regs, max_irr);
418 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
420 static inline int apic_search_irr(struct kvm_lapic *apic)
422 return find_highest_vector(apic->regs + APIC_IRR);
425 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
430 * Note that irr_pending is just a hint. It will be always
431 * true with virtual interrupt delivery enabled.
433 if (!apic->irr_pending)
436 result = apic_search_irr(apic);
437 ASSERT(result == -1 || result >= 16);
442 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
444 struct kvm_vcpu *vcpu;
448 if (unlikely(vcpu->arch.apicv_active)) {
449 /* need to update RVI */
450 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
451 kvm_x86_ops->hwapic_irr_update(vcpu,
452 apic_find_highest_irr(apic));
454 apic->irr_pending = false;
455 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
456 if (apic_search_irr(apic) != -1)
457 apic->irr_pending = true;
461 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
463 struct kvm_vcpu *vcpu;
465 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
471 * With APIC virtualization enabled, all caching is disabled
472 * because the processor can modify ISR under the hood. Instead
475 if (unlikely(vcpu->arch.apicv_active))
476 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
479 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
481 * ISR (in service register) bit is set when injecting an interrupt.
482 * The highest vector is injected. Thus the latest bit set matches
483 * the highest bit in ISR.
485 apic->highest_isr_cache = vec;
489 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
494 * Note that isr_count is always 1, and highest_isr_cache
495 * is always -1, with APIC virtualization enabled.
497 if (!apic->isr_count)
499 if (likely(apic->highest_isr_cache != -1))
500 return apic->highest_isr_cache;
502 result = find_highest_vector(apic->regs + APIC_ISR);
503 ASSERT(result == -1 || result >= 16);
508 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
510 struct kvm_vcpu *vcpu;
511 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
517 * We do get here for APIC virtualization enabled if the guest
518 * uses the Hyper-V APIC enlightenment. In this case we may need
519 * to trigger a new interrupt delivery by writing the SVI field;
520 * on the other hand isr_count and highest_isr_cache are unused
521 * and must be left alone.
523 if (unlikely(vcpu->arch.apicv_active))
524 kvm_x86_ops->hwapic_isr_update(vcpu,
525 apic_find_highest_isr(apic));
528 BUG_ON(apic->isr_count < 0);
529 apic->highest_isr_cache = -1;
533 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
535 /* This may race with setting of irr in __apic_accept_irq() and
536 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
537 * will cause vmexit immediately and the value will be recalculated
538 * on the next vmentry.
540 return apic_find_highest_irr(vcpu->arch.apic);
542 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
544 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
545 int vector, int level, int trig_mode,
546 struct dest_map *dest_map);
548 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
549 struct dest_map *dest_map)
551 struct kvm_lapic *apic = vcpu->arch.apic;
553 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
554 irq->level, irq->trig_mode, dest_map);
557 static int __pv_send_ipi(unsigned long *ipi_bitmap, struct kvm_apic_map *map,
558 struct kvm_lapic_irq *irq, u32 min)
561 struct kvm_vcpu *vcpu;
563 if (min > map->max_apic_id)
566 for_each_set_bit(i, ipi_bitmap,
567 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
568 if (map->phys_map[min + i]) {
569 vcpu = map->phys_map[min + i]->vcpu;
570 count += kvm_apic_set_irq(vcpu, irq, NULL);
577 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
578 unsigned long ipi_bitmap_high, u32 min,
579 unsigned long icr, int op_64_bit)
581 struct kvm_apic_map *map;
582 struct kvm_lapic_irq irq = {0};
583 int cluster_size = op_64_bit ? 64 : 32;
586 if (icr & (APIC_DEST_MASK | APIC_SHORT_MASK))
589 irq.vector = icr & APIC_VECTOR_MASK;
590 irq.delivery_mode = icr & APIC_MODE_MASK;
591 irq.level = (icr & APIC_INT_ASSERT) != 0;
592 irq.trig_mode = icr & APIC_INT_LEVELTRIG;
595 map = rcu_dereference(kvm->arch.apic_map);
599 count = __pv_send_ipi(&ipi_bitmap_low, map, &irq, min);
601 count += __pv_send_ipi(&ipi_bitmap_high, map, &irq, min);
608 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
611 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
615 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
618 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
622 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
624 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
627 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
630 if (pv_eoi_get_user(vcpu, &val) < 0) {
631 printk(KERN_WARNING "Can't read EOI MSR value: 0x%llx\n",
632 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
638 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
640 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
641 printk(KERN_WARNING "Can't set EOI MSR value: 0x%llx\n",
642 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
645 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
648 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
650 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
651 printk(KERN_WARNING "Can't clear EOI MSR value: 0x%llx\n",
652 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
655 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
658 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
661 if (apic->vcpu->arch.apicv_active)
662 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
664 highest_irr = apic_find_highest_irr(apic);
665 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
670 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
672 u32 tpr, isrv, ppr, old_ppr;
675 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
676 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
677 isr = apic_find_highest_isr(apic);
678 isrv = (isr != -1) ? isr : 0;
680 if ((tpr & 0xf0) >= (isrv & 0xf0))
687 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
689 return ppr < old_ppr;
692 static void apic_update_ppr(struct kvm_lapic *apic)
696 if (__apic_update_ppr(apic, &ppr) &&
697 apic_has_interrupt_for_ppr(apic, ppr) != -1)
698 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
701 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
703 apic_update_ppr(vcpu->arch.apic);
705 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
707 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
709 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
710 apic_update_ppr(apic);
713 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
715 return mda == (apic_x2apic_mode(apic) ?
716 X2APIC_BROADCAST : APIC_BROADCAST);
719 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
721 if (kvm_apic_broadcast(apic, mda))
724 if (apic_x2apic_mode(apic))
725 return mda == kvm_x2apic_id(apic);
728 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
729 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
730 * this allows unique addressing of VCPUs with APIC ID over 0xff.
731 * The 0xff condition is needed because writeable xAPIC ID.
733 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
736 return mda == kvm_xapic_id(apic);
739 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
743 if (kvm_apic_broadcast(apic, mda))
746 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
748 if (apic_x2apic_mode(apic))
749 return ((logical_id >> 16) == (mda >> 16))
750 && (logical_id & mda & 0xffff) != 0;
752 logical_id = GET_APIC_LOGICAL_ID(logical_id);
754 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
756 return (logical_id & mda) != 0;
757 case APIC_DFR_CLUSTER:
758 return ((logical_id >> 4) == (mda >> 4))
759 && (logical_id & mda & 0xf) != 0;
765 /* The KVM local APIC implementation has two quirks:
767 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
768 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
769 * KVM doesn't do that aliasing.
771 * - in-kernel IOAPIC messages have to be delivered directly to
772 * x2APIC, because the kernel does not support interrupt remapping.
773 * In order to support broadcast without interrupt remapping, x2APIC
774 * rewrites the destination of non-IPI messages from APIC_BROADCAST
775 * to X2APIC_BROADCAST.
777 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
778 * important when userspace wants to use x2APIC-format MSIs, because
779 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
781 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
782 struct kvm_lapic *source, struct kvm_lapic *target)
784 bool ipi = source != NULL;
786 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
787 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
788 return X2APIC_BROADCAST;
793 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
794 int shorthand, unsigned int dest, int dest_mode)
796 struct kvm_lapic *target = vcpu->arch.apic;
797 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
801 case APIC_DEST_NOSHORT:
802 if (dest_mode == APIC_DEST_PHYSICAL)
803 return kvm_apic_match_physical_addr(target, mda);
805 return kvm_apic_match_logical_addr(target, mda);
807 return target == source;
808 case APIC_DEST_ALLINC:
810 case APIC_DEST_ALLBUT:
811 return target != source;
816 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
818 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
819 const unsigned long *bitmap, u32 bitmap_size)
824 mod = vector % dest_vcpus;
826 for (i = 0; i <= mod; i++) {
827 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
828 BUG_ON(idx == bitmap_size);
834 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
836 if (!kvm->arch.disabled_lapic_found) {
837 kvm->arch.disabled_lapic_found = true;
839 "Disabled LAPIC found during irq injection\n");
843 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
844 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
846 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
847 if ((irq->dest_id == APIC_BROADCAST &&
848 map->mode != KVM_APIC_MODE_X2APIC))
850 if (irq->dest_id == X2APIC_BROADCAST)
853 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
854 if (irq->dest_id == (x2apic_ipi ?
855 X2APIC_BROADCAST : APIC_BROADCAST))
862 /* Return true if the interrupt can be handled by using *bitmap as index mask
863 * for valid destinations in *dst array.
864 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
865 * Note: we may have zero kvm_lapic destinations when we return true, which
866 * means that the interrupt should be dropped. In this case, *bitmap would be
867 * zero and *dst undefined.
869 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
870 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
871 struct kvm_apic_map *map, struct kvm_lapic ***dst,
872 unsigned long *bitmap)
876 if (irq->shorthand == APIC_DEST_SELF && src) {
880 } else if (irq->shorthand)
883 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
886 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
887 if (irq->dest_id > map->max_apic_id) {
890 u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1);
891 *dst = &map->phys_map[dest_id];
898 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
902 if (!kvm_lowest_prio_delivery(irq))
905 if (!kvm_vector_hashing_enabled()) {
907 for_each_set_bit(i, bitmap, 16) {
912 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
913 (*dst)[lowest]->vcpu) < 0)
920 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
923 if (!(*dst)[lowest]) {
924 kvm_apic_disabled_lapic_found(kvm);
930 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
935 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
936 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
938 struct kvm_apic_map *map;
939 unsigned long bitmap;
940 struct kvm_lapic **dst = NULL;
946 if (irq->shorthand == APIC_DEST_SELF) {
947 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
952 map = rcu_dereference(kvm->arch.apic_map);
954 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
957 for_each_set_bit(i, &bitmap, 16) {
960 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
969 * This routine tries to handle interrupts in posted mode, here is how
970 * it deals with different cases:
971 * - For single-destination interrupts, handle it in posted mode
972 * - Else if vector hashing is enabled and it is a lowest-priority
973 * interrupt, handle it in posted mode and use the following mechanism
974 * to find the destination vCPU.
975 * 1. For lowest-priority interrupts, store all the possible
976 * destination vCPUs in an array.
977 * 2. Use "guest vector % max number of destination vCPUs" to find
978 * the right destination vCPU in the array for the lowest-priority
980 * - Otherwise, use remapped mode to inject the interrupt.
982 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
983 struct kvm_vcpu **dest_vcpu)
985 struct kvm_apic_map *map;
986 unsigned long bitmap;
987 struct kvm_lapic **dst = NULL;
994 map = rcu_dereference(kvm->arch.apic_map);
996 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
997 hweight16(bitmap) == 1) {
998 unsigned long i = find_first_bit(&bitmap, 16);
1001 *dest_vcpu = dst[i]->vcpu;
1011 * Add a pending IRQ into lapic.
1012 * Return 1 if successfully added and 0 if discarded.
1014 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1015 int vector, int level, int trig_mode,
1016 struct dest_map *dest_map)
1019 struct kvm_vcpu *vcpu = apic->vcpu;
1021 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1023 switch (delivery_mode) {
1024 case APIC_DM_LOWEST:
1025 vcpu->arch.apic_arb_prio++;
1028 if (unlikely(trig_mode && !level))
1031 /* FIXME add logic for vcpu on reset */
1032 if (unlikely(!apic_enabled(apic)))
1038 __set_bit(vcpu->vcpu_id, dest_map->map);
1039 dest_map->vectors[vcpu->vcpu_id] = vector;
1042 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1044 kvm_lapic_set_vector(vector,
1045 apic->regs + APIC_TMR);
1047 kvm_lapic_clear_vector(vector,
1048 apic->regs + APIC_TMR);
1051 if (kvm_x86_ops->deliver_posted_interrupt(vcpu, vector)) {
1052 kvm_lapic_set_irr(vector, apic);
1053 kvm_make_request(KVM_REQ_EVENT, vcpu);
1054 kvm_vcpu_kick(vcpu);
1060 vcpu->arch.pv.pv_unhalted = 1;
1061 kvm_make_request(KVM_REQ_EVENT, vcpu);
1062 kvm_vcpu_kick(vcpu);
1067 kvm_make_request(KVM_REQ_SMI, vcpu);
1068 kvm_vcpu_kick(vcpu);
1073 kvm_inject_nmi(vcpu);
1074 kvm_vcpu_kick(vcpu);
1078 if (!trig_mode || level) {
1080 /* assumes that there are only KVM_APIC_INIT/SIPI */
1081 apic->pending_events = (1UL << KVM_APIC_INIT);
1082 kvm_make_request(KVM_REQ_EVENT, vcpu);
1083 kvm_vcpu_kick(vcpu);
1087 case APIC_DM_STARTUP:
1089 apic->sipi_vector = vector;
1090 /* make sure sipi_vector is visible for the receiver */
1092 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1093 kvm_make_request(KVM_REQ_EVENT, vcpu);
1094 kvm_vcpu_kick(vcpu);
1097 case APIC_DM_EXTINT:
1099 * Should only be called by kvm_apic_local_deliver() with LVT0,
1100 * before NMI watchdog was enabled. Already handled by
1101 * kvm_apic_accept_pic_intr().
1106 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1114 * This routine identifies the destination vcpus mask meant to receive the
1115 * IOAPIC interrupts. It either uses kvm_apic_map_get_dest_lapic() to find
1116 * out the destination vcpus array and set the bitmap or it traverses to
1117 * each available vcpu to identify the same.
1119 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
1120 unsigned long *vcpu_bitmap)
1122 struct kvm_lapic **dest_vcpu = NULL;
1123 struct kvm_lapic *src = NULL;
1124 struct kvm_apic_map *map;
1125 struct kvm_vcpu *vcpu;
1126 unsigned long bitmap;
1131 map = rcu_dereference(kvm->arch.apic_map);
1133 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dest_vcpu,
1136 for_each_set_bit(i, &bitmap, 16) {
1139 vcpu_idx = dest_vcpu[i]->vcpu->vcpu_idx;
1140 __set_bit(vcpu_idx, vcpu_bitmap);
1143 kvm_for_each_vcpu(i, vcpu, kvm) {
1144 if (!kvm_apic_present(vcpu))
1146 if (!kvm_apic_match_dest(vcpu, NULL,
1151 __set_bit(i, vcpu_bitmap);
1157 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1159 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1162 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1164 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1167 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1171 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1172 if (!kvm_ioapic_handles_vector(apic, vector))
1175 /* Request a KVM exit to inform the userspace IOAPIC. */
1176 if (irqchip_split(apic->vcpu->kvm)) {
1177 apic->vcpu->arch.pending_ioapic_eoi = vector;
1178 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1182 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1183 trigger_mode = IOAPIC_LEVEL_TRIG;
1185 trigger_mode = IOAPIC_EDGE_TRIG;
1187 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1190 static int apic_set_eoi(struct kvm_lapic *apic)
1192 int vector = apic_find_highest_isr(apic);
1194 trace_kvm_eoi(apic, vector);
1197 * Not every write EOI will has corresponding ISR,
1198 * one example is when Kernel check timer on setup_IO_APIC
1203 apic_clear_isr(vector, apic);
1204 apic_update_ppr(apic);
1206 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1207 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1209 kvm_ioapic_send_eoi(apic, vector);
1210 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1215 * this interface assumes a trap-like exit, which has already finished
1216 * desired side effect including vISR and vPPR update.
1218 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1220 struct kvm_lapic *apic = vcpu->arch.apic;
1222 trace_kvm_eoi(apic, vector);
1224 kvm_ioapic_send_eoi(apic, vector);
1225 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1227 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1229 static void apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high)
1231 struct kvm_lapic_irq irq;
1233 irq.vector = icr_low & APIC_VECTOR_MASK;
1234 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1235 irq.dest_mode = icr_low & APIC_DEST_MASK;
1236 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1237 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1238 irq.shorthand = icr_low & APIC_SHORT_MASK;
1239 irq.msi_redir_hint = false;
1240 if (apic_x2apic_mode(apic))
1241 irq.dest_id = icr_high;
1243 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1245 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1247 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1250 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1252 ktime_t remaining, now;
1256 ASSERT(apic != NULL);
1258 /* if initial count is 0, current count should also be 0 */
1259 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1260 apic->lapic_timer.period == 0)
1264 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1265 if (ktime_to_ns(remaining) < 0)
1268 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1269 tmcct = div64_u64(ns,
1270 (APIC_BUS_CYCLE_NS * apic->divide_count));
1275 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1277 struct kvm_vcpu *vcpu = apic->vcpu;
1278 struct kvm_run *run = vcpu->run;
1280 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1281 run->tpr_access.rip = kvm_rip_read(vcpu);
1282 run->tpr_access.is_write = write;
1285 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1287 if (apic->vcpu->arch.tpr_access_reporting)
1288 __report_tpr_access(apic, write);
1291 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1295 if (offset >= LAPIC_MMIO_LENGTH)
1302 case APIC_TMCCT: /* Timer CCR */
1303 if (apic_lvtt_tscdeadline(apic))
1306 val = apic_get_tmcct(apic);
1309 apic_update_ppr(apic);
1310 val = kvm_lapic_get_reg(apic, offset);
1313 report_tpr_access(apic, false);
1316 val = kvm_lapic_get_reg(apic, offset);
1323 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1325 return container_of(dev, struct kvm_lapic, dev);
1328 #define APIC_REG_MASK(reg) (1ull << ((reg) >> 4))
1329 #define APIC_REGS_MASK(first, count) \
1330 (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1332 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1335 unsigned char alignment = offset & 0xf;
1337 /* this bitmask has a bit cleared for each reserved register */
1338 u64 valid_reg_mask =
1339 APIC_REG_MASK(APIC_ID) |
1340 APIC_REG_MASK(APIC_LVR) |
1341 APIC_REG_MASK(APIC_TASKPRI) |
1342 APIC_REG_MASK(APIC_PROCPRI) |
1343 APIC_REG_MASK(APIC_LDR) |
1344 APIC_REG_MASK(APIC_DFR) |
1345 APIC_REG_MASK(APIC_SPIV) |
1346 APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) |
1347 APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) |
1348 APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) |
1349 APIC_REG_MASK(APIC_ESR) |
1350 APIC_REG_MASK(APIC_ICR) |
1351 APIC_REG_MASK(APIC_ICR2) |
1352 APIC_REG_MASK(APIC_LVTT) |
1353 APIC_REG_MASK(APIC_LVTTHMR) |
1354 APIC_REG_MASK(APIC_LVTPC) |
1355 APIC_REG_MASK(APIC_LVT0) |
1356 APIC_REG_MASK(APIC_LVT1) |
1357 APIC_REG_MASK(APIC_LVTERR) |
1358 APIC_REG_MASK(APIC_TMICT) |
1359 APIC_REG_MASK(APIC_TMCCT) |
1360 APIC_REG_MASK(APIC_TDCR);
1362 /* ARBPRI is not valid on x2APIC */
1363 if (!apic_x2apic_mode(apic))
1364 valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI);
1366 if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset)))
1369 result = __apic_read(apic, offset & ~0xf);
1371 trace_kvm_apic_read(offset, result);
1377 memcpy(data, (char *)&result + alignment, len);
1380 printk(KERN_ERR "Local APIC read with len = %x, "
1381 "should be 1,2, or 4 instead\n", len);
1386 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1388 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1390 return addr >= apic->base_address &&
1391 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1394 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1395 gpa_t address, int len, void *data)
1397 struct kvm_lapic *apic = to_lapic(this);
1398 u32 offset = address - apic->base_address;
1400 if (!apic_mmio_in_range(apic, address))
1403 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1404 if (!kvm_check_has_quirk(vcpu->kvm,
1405 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1408 memset(data, 0xff, len);
1412 kvm_lapic_reg_read(apic, offset, len, data);
1417 static void update_divide_count(struct kvm_lapic *apic)
1419 u32 tmp1, tmp2, tdcr;
1421 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1423 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1424 apic->divide_count = 0x1 << (tmp2 & 0x7);
1427 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1430 * Do not allow the guest to program periodic timers with small
1431 * interval, since the hrtimers are not throttled by the host
1434 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1435 s64 min_period = min_timer_period_us * 1000LL;
1437 if (apic->lapic_timer.period < min_period) {
1438 pr_info_ratelimited(
1439 "kvm: vcpu %i: requested %lld ns "
1440 "lapic timer period limited to %lld ns\n",
1441 apic->vcpu->vcpu_id,
1442 apic->lapic_timer.period, min_period);
1443 apic->lapic_timer.period = min_period;
1448 static void cancel_hv_timer(struct kvm_lapic *apic);
1450 static void apic_update_lvtt(struct kvm_lapic *apic)
1452 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1453 apic->lapic_timer.timer_mode_mask;
1455 if (apic->lapic_timer.timer_mode != timer_mode) {
1456 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1457 APIC_LVT_TIMER_TSCDEADLINE)) {
1458 hrtimer_cancel(&apic->lapic_timer.timer);
1460 if (apic->lapic_timer.hv_timer_in_use)
1461 cancel_hv_timer(apic);
1463 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1464 apic->lapic_timer.period = 0;
1465 apic->lapic_timer.tscdeadline = 0;
1467 apic->lapic_timer.timer_mode = timer_mode;
1468 limit_periodic_timer_frequency(apic);
1473 * On APICv, this test will cause a busy wait
1474 * during a higher-priority task.
1477 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1479 struct kvm_lapic *apic = vcpu->arch.apic;
1480 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1482 if (kvm_apic_hw_enabled(apic)) {
1483 int vec = reg & APIC_VECTOR_MASK;
1484 void *bitmap = apic->regs + APIC_ISR;
1486 if (vcpu->arch.apicv_active)
1487 bitmap = apic->regs + APIC_IRR;
1489 if (apic_test_vector(vec, bitmap))
1495 static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles)
1497 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;
1500 * If the guest TSC is running at a different ratio than the host, then
1501 * convert the delay to nanoseconds to achieve an accurate delay. Note
1502 * that __delay() uses delay_tsc whenever the hardware has TSC, thus
1503 * always for VMX enabled hardware.
1505 if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) {
1506 __delay(min(guest_cycles,
1507 nsec_to_cycles(vcpu, timer_advance_ns)));
1509 u64 delay_ns = guest_cycles * 1000000ULL;
1510 do_div(delay_ns, vcpu->arch.virtual_tsc_khz);
1511 ndelay(min_t(u32, delay_ns, timer_advance_ns));
1515 static inline void adjust_lapic_timer_advance(struct kvm_vcpu *vcpu,
1516 s64 advance_expire_delta)
1518 struct kvm_lapic *apic = vcpu->arch.apic;
1519 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
1522 /* Do not adjust for tiny fluctuations or large random spikes. */
1523 if (abs(advance_expire_delta) > LAPIC_TIMER_ADVANCE_ADJUST_MAX ||
1524 abs(advance_expire_delta) < LAPIC_TIMER_ADVANCE_ADJUST_MIN)
1528 if (advance_expire_delta < 0) {
1529 ns = -advance_expire_delta * 1000000ULL;
1530 do_div(ns, vcpu->arch.virtual_tsc_khz);
1531 timer_advance_ns -= ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
1534 ns = advance_expire_delta * 1000000ULL;
1535 do_div(ns, vcpu->arch.virtual_tsc_khz);
1536 timer_advance_ns += ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
1539 if (unlikely(timer_advance_ns > LAPIC_TIMER_ADVANCE_NS_MAX))
1540 timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
1541 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
1544 static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1546 struct kvm_lapic *apic = vcpu->arch.apic;
1547 u64 guest_tsc, tsc_deadline;
1549 if (apic->lapic_timer.expired_tscdeadline == 0)
1552 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1553 apic->lapic_timer.expired_tscdeadline = 0;
1554 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1555 apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline;
1557 if (guest_tsc < tsc_deadline)
1558 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
1560 if (lapic_timer_advance_dynamic)
1561 adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta);
1564 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1566 if (lapic_timer_int_injected(vcpu))
1567 __kvm_wait_lapic_expire(vcpu);
1569 EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire);
1571 static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic)
1573 struct kvm_timer *ktimer = &apic->lapic_timer;
1575 kvm_apic_local_deliver(apic, APIC_LVTT);
1576 if (apic_lvtt_tscdeadline(apic)) {
1577 ktimer->tscdeadline = 0;
1578 } else if (apic_lvtt_oneshot(apic)) {
1579 ktimer->tscdeadline = 0;
1580 ktimer->target_expiration = 0;
1584 static void apic_timer_expired(struct kvm_lapic *apic)
1586 struct kvm_vcpu *vcpu = apic->vcpu;
1587 struct kvm_timer *ktimer = &apic->lapic_timer;
1589 if (atomic_read(&apic->lapic_timer.pending))
1592 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
1593 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1595 if (kvm_use_posted_timer_interrupt(apic->vcpu)) {
1596 if (apic->lapic_timer.timer_advance_ns)
1597 __kvm_wait_lapic_expire(vcpu);
1598 kvm_apic_inject_pending_timer_irqs(apic);
1602 atomic_inc(&apic->lapic_timer.pending);
1603 kvm_set_pending_timer(vcpu);
1606 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1608 struct kvm_timer *ktimer = &apic->lapic_timer;
1609 u64 guest_tsc, tscdeadline = ktimer->tscdeadline;
1612 struct kvm_vcpu *vcpu = apic->vcpu;
1613 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1614 unsigned long flags;
1617 if (unlikely(!tscdeadline || !this_tsc_khz))
1620 local_irq_save(flags);
1623 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1625 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1626 do_div(ns, this_tsc_khz);
1628 if (likely(tscdeadline > guest_tsc) &&
1629 likely(ns > apic->lapic_timer.timer_advance_ns)) {
1630 expire = ktime_add_ns(now, ns);
1631 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns);
1632 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD);
1634 apic_timer_expired(apic);
1636 local_irq_restore(flags);
1639 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1641 ktime_t now, remaining;
1642 u64 ns_remaining_old, ns_remaining_new;
1644 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1645 * APIC_BUS_CYCLE_NS * apic->divide_count;
1646 limit_periodic_timer_frequency(apic);
1649 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1650 if (ktime_to_ns(remaining) < 0)
1653 ns_remaining_old = ktime_to_ns(remaining);
1654 ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1655 apic->divide_count, old_divisor);
1657 apic->lapic_timer.tscdeadline +=
1658 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1659 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1660 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1663 static bool set_target_expiration(struct kvm_lapic *apic)
1669 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1670 * APIC_BUS_CYCLE_NS * apic->divide_count;
1672 if (!apic->lapic_timer.period) {
1673 apic->lapic_timer.tscdeadline = 0;
1677 limit_periodic_timer_frequency(apic);
1679 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1680 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1681 apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1686 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1688 ktime_t now = ktime_get();
1693 * Synchronize both deadlines to the same time source or
1694 * differences in the periods (caused by differences in the
1695 * underlying clocks or numerical approximation errors) will
1696 * cause the two to drift apart over time as the errors
1699 apic->lapic_timer.target_expiration =
1700 ktime_add_ns(apic->lapic_timer.target_expiration,
1701 apic->lapic_timer.period);
1702 delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1703 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1704 nsec_to_cycles(apic->vcpu, delta);
1707 static void start_sw_period(struct kvm_lapic *apic)
1709 if (!apic->lapic_timer.period)
1712 if (ktime_after(ktime_get(),
1713 apic->lapic_timer.target_expiration)) {
1714 apic_timer_expired(apic);
1716 if (apic_lvtt_oneshot(apic))
1719 advance_periodic_target_expiration(apic);
1722 hrtimer_start(&apic->lapic_timer.timer,
1723 apic->lapic_timer.target_expiration,
1724 HRTIMER_MODE_ABS_HARD);
1727 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1729 if (!lapic_in_kernel(vcpu))
1732 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1734 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1736 static void cancel_hv_timer(struct kvm_lapic *apic)
1738 WARN_ON(preemptible());
1739 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1740 kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1741 apic->lapic_timer.hv_timer_in_use = false;
1744 static bool start_hv_timer(struct kvm_lapic *apic)
1746 struct kvm_timer *ktimer = &apic->lapic_timer;
1747 struct kvm_vcpu *vcpu = apic->vcpu;
1750 WARN_ON(preemptible());
1751 if (!kvm_x86_ops->set_hv_timer)
1754 if (!ktimer->tscdeadline)
1757 if (kvm_x86_ops->set_hv_timer(vcpu, ktimer->tscdeadline, &expired))
1760 ktimer->hv_timer_in_use = true;
1761 hrtimer_cancel(&ktimer->timer);
1764 * To simplify handling the periodic timer, leave the hv timer running
1765 * even if the deadline timer has expired, i.e. rely on the resulting
1766 * VM-Exit to recompute the periodic timer's target expiration.
1768 if (!apic_lvtt_period(apic)) {
1770 * Cancel the hv timer if the sw timer fired while the hv timer
1771 * was being programmed, or if the hv timer itself expired.
1773 if (atomic_read(&ktimer->pending)) {
1774 cancel_hv_timer(apic);
1775 } else if (expired) {
1776 apic_timer_expired(apic);
1777 cancel_hv_timer(apic);
1781 trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use);
1786 static void start_sw_timer(struct kvm_lapic *apic)
1788 struct kvm_timer *ktimer = &apic->lapic_timer;
1790 WARN_ON(preemptible());
1791 if (apic->lapic_timer.hv_timer_in_use)
1792 cancel_hv_timer(apic);
1793 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1796 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1797 start_sw_period(apic);
1798 else if (apic_lvtt_tscdeadline(apic))
1799 start_sw_tscdeadline(apic);
1800 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1803 static void restart_apic_timer(struct kvm_lapic *apic)
1807 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending))
1810 if (!start_hv_timer(apic))
1811 start_sw_timer(apic);
1816 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1818 struct kvm_lapic *apic = vcpu->arch.apic;
1821 /* If the preempt notifier has already run, it also called apic_timer_expired */
1822 if (!apic->lapic_timer.hv_timer_in_use)
1824 WARN_ON(swait_active(&vcpu->wq));
1825 cancel_hv_timer(apic);
1826 apic_timer_expired(apic);
1828 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1829 advance_periodic_target_expiration(apic);
1830 restart_apic_timer(apic);
1835 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1837 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1839 restart_apic_timer(vcpu->arch.apic);
1841 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1843 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1845 struct kvm_lapic *apic = vcpu->arch.apic;
1848 /* Possibly the TSC deadline timer is not enabled yet */
1849 if (apic->lapic_timer.hv_timer_in_use)
1850 start_sw_timer(apic);
1853 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1855 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1857 struct kvm_lapic *apic = vcpu->arch.apic;
1859 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1860 restart_apic_timer(apic);
1863 static void start_apic_timer(struct kvm_lapic *apic)
1865 atomic_set(&apic->lapic_timer.pending, 0);
1867 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1868 && !set_target_expiration(apic))
1871 restart_apic_timer(apic);
1874 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1876 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1878 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1879 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1880 if (lvt0_in_nmi_mode) {
1881 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1883 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1887 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1891 trace_kvm_apic_write(reg, val);
1894 case APIC_ID: /* Local APIC ID */
1895 if (!apic_x2apic_mode(apic))
1896 kvm_apic_set_xapic_id(apic, val >> 24);
1902 report_tpr_access(apic, true);
1903 apic_set_tpr(apic, val & 0xff);
1911 if (!apic_x2apic_mode(apic))
1912 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1918 if (!apic_x2apic_mode(apic)) {
1919 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1920 recalculate_apic_map(apic->vcpu->kvm);
1927 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1928 mask |= APIC_SPIV_DIRECTED_EOI;
1929 apic_set_spiv(apic, val & mask);
1930 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1934 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1935 lvt_val = kvm_lapic_get_reg(apic,
1936 APIC_LVTT + 0x10 * i);
1937 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1938 lvt_val | APIC_LVT_MASKED);
1940 apic_update_lvtt(apic);
1941 atomic_set(&apic->lapic_timer.pending, 0);
1947 /* No delay here, so we always clear the pending bit */
1949 apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2));
1950 kvm_lapic_set_reg(apic, APIC_ICR, val);
1954 if (!apic_x2apic_mode(apic))
1956 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1960 apic_manage_nmi_watchdog(apic, val);
1966 /* TODO: Check vector */
1970 if (!kvm_apic_sw_enabled(apic))
1971 val |= APIC_LVT_MASKED;
1972 size = ARRAY_SIZE(apic_lvt_mask);
1973 index = array_index_nospec(
1974 (reg - APIC_LVTT) >> 4, size);
1975 val &= apic_lvt_mask[index];
1976 kvm_lapic_set_reg(apic, reg, val);
1981 if (!kvm_apic_sw_enabled(apic))
1982 val |= APIC_LVT_MASKED;
1983 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1984 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1985 apic_update_lvtt(apic);
1989 if (apic_lvtt_tscdeadline(apic))
1992 hrtimer_cancel(&apic->lapic_timer.timer);
1993 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1994 start_apic_timer(apic);
1998 uint32_t old_divisor = apic->divide_count;
2000 kvm_lapic_set_reg(apic, APIC_TDCR, val);
2001 update_divide_count(apic);
2002 if (apic->divide_count != old_divisor &&
2003 apic->lapic_timer.period) {
2004 hrtimer_cancel(&apic->lapic_timer.timer);
2005 update_target_expiration(apic, old_divisor);
2006 restart_apic_timer(apic);
2011 if (apic_x2apic_mode(apic) && val != 0)
2016 if (apic_x2apic_mode(apic)) {
2017 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
2028 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
2030 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
2031 gpa_t address, int len, const void *data)
2033 struct kvm_lapic *apic = to_lapic(this);
2034 unsigned int offset = address - apic->base_address;
2037 if (!apic_mmio_in_range(apic, address))
2040 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
2041 if (!kvm_check_has_quirk(vcpu->kvm,
2042 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
2049 * APIC register must be aligned on 128-bits boundary.
2050 * 32/64/128 bits registers must be accessed thru 32 bits.
2053 if (len != 4 || (offset & 0xf))
2058 kvm_lapic_reg_write(apic, offset & 0xff0, val);
2063 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
2065 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
2067 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
2069 /* emulate APIC access in a trap manner */
2070 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
2074 /* hw has done the conditional check and inst decode */
2077 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
2079 /* TODO: optimize to just emulate side effect w/o one more write */
2080 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
2082 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2084 void kvm_free_lapic(struct kvm_vcpu *vcpu)
2086 struct kvm_lapic *apic = vcpu->arch.apic;
2088 if (!vcpu->arch.apic)
2091 hrtimer_cancel(&apic->lapic_timer.timer);
2093 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2094 static_key_slow_dec_deferred(&apic_hw_disabled);
2096 if (!apic->sw_enabled)
2097 static_key_slow_dec_deferred(&apic_sw_disabled);
2100 free_page((unsigned long)apic->regs);
2106 *----------------------------------------------------------------------
2108 *----------------------------------------------------------------------
2110 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2112 struct kvm_lapic *apic = vcpu->arch.apic;
2114 if (!lapic_in_kernel(vcpu) ||
2115 !apic_lvtt_tscdeadline(apic))
2118 return apic->lapic_timer.tscdeadline;
2121 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2123 struct kvm_lapic *apic = vcpu->arch.apic;
2125 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
2126 apic_lvtt_period(apic))
2129 hrtimer_cancel(&apic->lapic_timer.timer);
2130 apic->lapic_timer.tscdeadline = data;
2131 start_apic_timer(apic);
2134 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2136 struct kvm_lapic *apic = vcpu->arch.apic;
2138 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
2139 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
2142 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2146 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2148 return (tpr & 0xf0) >> 4;
2151 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2153 u64 old_value = vcpu->arch.apic_base;
2154 struct kvm_lapic *apic = vcpu->arch.apic;
2157 value |= MSR_IA32_APICBASE_BSP;
2159 vcpu->arch.apic_base = value;
2161 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2162 kvm_update_cpuid(vcpu);
2167 /* update jump label if enable bit changes */
2168 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2169 if (value & MSR_IA32_APICBASE_ENABLE) {
2170 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2171 static_key_slow_dec_deferred(&apic_hw_disabled);
2173 static_key_slow_inc(&apic_hw_disabled.key);
2174 recalculate_apic_map(vcpu->kvm);
2178 if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2179 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2181 if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2182 kvm_x86_ops->set_virtual_apic_mode(vcpu);
2184 apic->base_address = apic->vcpu->arch.apic_base &
2185 MSR_IA32_APICBASE_BASE;
2187 if ((value & MSR_IA32_APICBASE_ENABLE) &&
2188 apic->base_address != APIC_DEFAULT_PHYS_BASE)
2189 pr_warn_once("APIC base relocation is unsupported by KVM");
2192 void kvm_apic_update_apicv(struct kvm_vcpu *vcpu)
2194 struct kvm_lapic *apic = vcpu->arch.apic;
2196 if (vcpu->arch.apicv_active) {
2197 /* irr_pending is always true when apicv is activated. */
2198 apic->irr_pending = true;
2199 apic->isr_count = 1;
2201 apic->irr_pending = (apic_search_irr(apic) != -1);
2202 apic->isr_count = count_vectors(apic->regs + APIC_ISR);
2205 EXPORT_SYMBOL_GPL(kvm_apic_update_apicv);
2207 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2209 struct kvm_lapic *apic = vcpu->arch.apic;
2215 /* Stop the timer in case it's a reset to an active apic */
2216 hrtimer_cancel(&apic->lapic_timer.timer);
2219 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2220 MSR_IA32_APICBASE_ENABLE);
2221 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2223 kvm_apic_set_version(apic->vcpu);
2225 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2226 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2227 apic_update_lvtt(apic);
2228 if (kvm_vcpu_is_reset_bsp(vcpu) &&
2229 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2230 kvm_lapic_set_reg(apic, APIC_LVT0,
2231 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2232 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2234 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
2235 apic_set_spiv(apic, 0xff);
2236 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2237 if (!apic_x2apic_mode(apic))
2238 kvm_apic_set_ldr(apic, 0);
2239 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2240 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2241 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2242 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2243 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2244 for (i = 0; i < 8; i++) {
2245 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2246 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2247 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2249 kvm_apic_update_apicv(vcpu);
2250 apic->highest_isr_cache = -1;
2251 update_divide_count(apic);
2252 atomic_set(&apic->lapic_timer.pending, 0);
2253 if (kvm_vcpu_is_bsp(vcpu))
2254 kvm_lapic_set_base(vcpu,
2255 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2256 vcpu->arch.pv_eoi.msr_val = 0;
2257 apic_update_ppr(apic);
2258 if (vcpu->arch.apicv_active) {
2259 kvm_x86_ops->apicv_post_state_restore(vcpu);
2260 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2261 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2264 vcpu->arch.apic_arb_prio = 0;
2265 vcpu->arch.apic_attention = 0;
2269 *----------------------------------------------------------------------
2271 *----------------------------------------------------------------------
2274 static bool lapic_is_periodic(struct kvm_lapic *apic)
2276 return apic_lvtt_period(apic);
2279 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2281 struct kvm_lapic *apic = vcpu->arch.apic;
2283 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2284 return atomic_read(&apic->lapic_timer.pending);
2289 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2291 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2292 int vector, mode, trig_mode;
2294 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2295 vector = reg & APIC_VECTOR_MASK;
2296 mode = reg & APIC_MODE_MASK;
2297 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2298 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2304 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2306 struct kvm_lapic *apic = vcpu->arch.apic;
2309 kvm_apic_local_deliver(apic, APIC_LVT0);
2312 static const struct kvm_io_device_ops apic_mmio_ops = {
2313 .read = apic_mmio_read,
2314 .write = apic_mmio_write,
2317 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2319 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2320 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2322 apic_timer_expired(apic);
2324 if (lapic_is_periodic(apic)) {
2325 advance_periodic_target_expiration(apic);
2326 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2327 return HRTIMER_RESTART;
2329 return HRTIMER_NORESTART;
2332 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns)
2334 struct kvm_lapic *apic;
2336 ASSERT(vcpu != NULL);
2338 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT);
2342 vcpu->arch.apic = apic;
2344 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
2346 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2348 goto nomem_free_apic;
2352 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2353 HRTIMER_MODE_ABS_HARD);
2354 apic->lapic_timer.timer.function = apic_timer_fn;
2355 if (timer_advance_ns == -1) {
2356 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
2357 lapic_timer_advance_dynamic = true;
2359 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
2360 lapic_timer_advance_dynamic = false;
2364 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2365 * thinking that APIC state has changed.
2367 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2368 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2369 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2374 vcpu->arch.apic = NULL;
2379 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2381 struct kvm_lapic *apic = vcpu->arch.apic;
2384 if (!kvm_apic_hw_enabled(apic))
2387 __apic_update_ppr(apic, &ppr);
2388 return apic_has_interrupt_for_ppr(apic, ppr);
2391 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2393 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2395 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2397 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2398 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2403 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2405 struct kvm_lapic *apic = vcpu->arch.apic;
2407 if (atomic_read(&apic->lapic_timer.pending) > 0) {
2408 kvm_apic_inject_pending_timer_irqs(apic);
2409 atomic_set(&apic->lapic_timer.pending, 0);
2413 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2415 int vector = kvm_apic_has_interrupt(vcpu);
2416 struct kvm_lapic *apic = vcpu->arch.apic;
2423 * We get here even with APIC virtualization enabled, if doing
2424 * nested virtualization and L1 runs with the "acknowledge interrupt
2425 * on exit" mode. Then we cannot inject the interrupt via RVI,
2426 * because the process would deliver it through the IDT.
2429 apic_clear_irr(vector, apic);
2430 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2432 * For auto-EOI interrupts, there might be another pending
2433 * interrupt above PPR, so check whether to raise another
2436 apic_update_ppr(apic);
2439 * For normal interrupts, PPR has been raised and there cannot
2440 * be a higher-priority pending interrupt---except if there was
2441 * a concurrent interrupt injection, but that would have
2442 * triggered KVM_REQ_EVENT already.
2444 apic_set_isr(vector, apic);
2445 __apic_update_ppr(apic, &ppr);
2451 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2452 struct kvm_lapic_state *s, bool set)
2454 if (apic_x2apic_mode(vcpu->arch.apic)) {
2455 u32 *id = (u32 *)(s->regs + APIC_ID);
2456 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2458 if (vcpu->kvm->arch.x2apic_format) {
2459 if (*id != vcpu->vcpu_id)
2468 /* In x2APIC mode, the LDR is fixed and based on the id */
2470 *ldr = kvm_apic_calc_x2apic_ldr(*id);
2476 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2478 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2479 return kvm_apic_state_fixup(vcpu, s, false);
2482 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2484 struct kvm_lapic *apic = vcpu->arch.apic;
2488 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2489 /* set SPIV separately to get count of SW disabled APICs right */
2490 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2492 r = kvm_apic_state_fixup(vcpu, s, true);
2495 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
2497 recalculate_apic_map(vcpu->kvm);
2498 kvm_apic_set_version(vcpu);
2500 apic_update_ppr(apic);
2501 hrtimer_cancel(&apic->lapic_timer.timer);
2502 apic_update_lvtt(apic);
2503 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2504 update_divide_count(apic);
2505 start_apic_timer(apic);
2506 kvm_apic_update_apicv(vcpu);
2507 apic->highest_isr_cache = -1;
2508 if (vcpu->arch.apicv_active) {
2509 kvm_x86_ops->apicv_post_state_restore(vcpu);
2510 kvm_x86_ops->hwapic_irr_update(vcpu,
2511 apic_find_highest_irr(apic));
2512 kvm_x86_ops->hwapic_isr_update(vcpu,
2513 apic_find_highest_isr(apic));
2515 kvm_make_request(KVM_REQ_EVENT, vcpu);
2516 if (ioapic_in_kernel(vcpu->kvm))
2517 kvm_rtc_eoi_tracking_restore_one(vcpu);
2519 vcpu->arch.apic_arb_prio = 0;
2524 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2526 struct hrtimer *timer;
2528 if (!lapic_in_kernel(vcpu) ||
2529 kvm_can_post_timer_interrupt(vcpu))
2532 timer = &vcpu->arch.apic->lapic_timer.timer;
2533 if (hrtimer_cancel(timer))
2534 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_HARD);
2538 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2540 * Detect whether guest triggered PV EOI since the
2541 * last entry. If yes, set EOI on guests's behalf.
2542 * Clear PV EOI in guest memory in any case.
2544 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2545 struct kvm_lapic *apic)
2550 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2551 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2553 * KVM_APIC_PV_EOI_PENDING is unset:
2554 * -> host disabled PV EOI.
2555 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2556 * -> host enabled PV EOI, guest did not execute EOI yet.
2557 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2558 * -> host enabled PV EOI, guest executed EOI.
2560 BUG_ON(!pv_eoi_enabled(vcpu));
2561 pending = pv_eoi_get_pending(vcpu);
2563 * Clear pending bit in any case: it will be set again on vmentry.
2564 * While this might not be ideal from performance point of view,
2565 * this makes sure pv eoi is only enabled when we know it's safe.
2567 pv_eoi_clr_pending(vcpu);
2570 vector = apic_set_eoi(apic);
2571 trace_kvm_pv_eoi(apic, vector);
2574 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2578 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2579 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2581 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2584 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2588 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2592 * apic_sync_pv_eoi_to_guest - called before vmentry
2594 * Detect whether it's safe to enable PV EOI and
2597 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2598 struct kvm_lapic *apic)
2600 if (!pv_eoi_enabled(vcpu) ||
2601 /* IRR set or many bits in ISR: could be nested. */
2602 apic->irr_pending ||
2603 /* Cache not set: could be safe but we don't bother. */
2604 apic->highest_isr_cache == -1 ||
2605 /* Need EOI to update ioapic. */
2606 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2608 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2609 * so we need not do anything here.
2614 pv_eoi_set_pending(apic->vcpu);
2617 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2620 int max_irr, max_isr;
2621 struct kvm_lapic *apic = vcpu->arch.apic;
2623 apic_sync_pv_eoi_to_guest(vcpu, apic);
2625 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2628 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2629 max_irr = apic_find_highest_irr(apic);
2632 max_isr = apic_find_highest_isr(apic);
2635 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2637 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2641 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2644 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2645 &vcpu->arch.apic->vapic_cache,
2646 vapic_addr, sizeof(u32)))
2648 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2650 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2653 vcpu->arch.apic->vapic_addr = vapic_addr;
2657 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2659 struct kvm_lapic *apic = vcpu->arch.apic;
2660 u32 reg = (msr - APIC_BASE_MSR) << 4;
2662 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2665 if (reg == APIC_ICR2)
2668 /* if this is ICR write vector before command */
2669 if (reg == APIC_ICR)
2670 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2671 return kvm_lapic_reg_write(apic, reg, (u32)data);
2674 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2676 struct kvm_lapic *apic = vcpu->arch.apic;
2677 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2679 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2682 if (reg == APIC_DFR || reg == APIC_ICR2)
2685 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2687 if (reg == APIC_ICR)
2688 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2690 *data = (((u64)high) << 32) | low;
2695 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2697 struct kvm_lapic *apic = vcpu->arch.apic;
2699 if (!lapic_in_kernel(vcpu))
2702 /* if this is ICR write vector before command */
2703 if (reg == APIC_ICR)
2704 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2705 return kvm_lapic_reg_write(apic, reg, (u32)data);
2708 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2710 struct kvm_lapic *apic = vcpu->arch.apic;
2713 if (!lapic_in_kernel(vcpu))
2716 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2718 if (reg == APIC_ICR)
2719 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2721 *data = (((u64)high) << 32) | low;
2726 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
2728 u64 addr = data & ~KVM_MSR_ENABLED;
2729 struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2730 unsigned long new_len;
2732 if (!IS_ALIGNED(addr, 4))
2735 vcpu->arch.pv_eoi.msr_val = data;
2736 if (!pv_eoi_enabled(vcpu))
2739 if (addr == ghc->gpa && len <= ghc->len)
2744 return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
2747 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2749 struct kvm_lapic *apic = vcpu->arch.apic;
2753 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2757 * INITs are latched while CPU is in specific states
2758 * (SMM, VMX non-root mode, SVM with GIF=0).
2759 * Because a CPU cannot be in these states immediately
2760 * after it has processed an INIT signal (and thus in
2761 * KVM_MP_STATE_INIT_RECEIVED state), just eat SIPIs
2762 * and leave the INIT pending.
2764 if (kvm_vcpu_latch_init(vcpu)) {
2765 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2766 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2767 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2771 pe = xchg(&apic->pending_events, 0);
2772 if (test_bit(KVM_APIC_INIT, &pe)) {
2773 kvm_vcpu_reset(vcpu, true);
2774 if (kvm_vcpu_is_bsp(apic->vcpu))
2775 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2777 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2779 if (test_bit(KVM_APIC_SIPI, &pe) &&
2780 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2781 /* evaluate pending_events before reading the vector */
2783 sipi_vector = apic->sipi_vector;
2784 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2785 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2789 void kvm_lapic_init(void)
2791 /* do not patch jump label more than once per second */
2792 jump_label_rate_limit(&apic_hw_disabled, HZ);
2793 jump_label_rate_limit(&apic_sw_disabled, HZ);
2796 void kvm_lapic_exit(void)
2798 static_key_deferred_flush(&apic_hw_disabled);
2799 static_key_deferred_flush(&apic_sw_disabled);