arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/export.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44 #include "hyperv.h"
  45
  46 #ifndef CONFIG_X86_64
  47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  48 #else
  49 #define mod_64(x, y) ((x) % (y))
  50 #endif
  51
  52 #define PRId64 "d"
  53 #define PRIx64 "llx"
  54 #define PRIu64 "u"
  55 #define PRIo64 "o"
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...)
  59
  60 /* 14 is the version for Xeon and Pentium 8.4.8*/
  61 #define APIC_VERSION                    (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
  62 #define LAPIC_MMIO_LENGTH               (1 << 12)
  63 /* followed define is not in apicdef.h */
  64 #define APIC_SHORT_MASK                 0xc0000
  65 #define APIC_DEST_NOSHORT               0x0
  66 #define APIC_DEST_MASK                  0x800
  67 #define MAX_APIC_VECTOR                 256
  68 #define APIC_VECTORS_PER_REG            32
  69
  70 #define APIC_BROADCAST                  0xFF
  71 #define X2APIC_BROADCAST                0xFFFFFFFFul
  72
  73 static inline int apic_test_vector(int vec, void *bitmap)
  74 {
  75         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  76 }
  77
  78 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  79 {
  80         struct kvm_lapic *apic = vcpu->arch.apic;
  81
  82         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  83                 apic_test_vector(vector, apic->regs + APIC_IRR);
  84 }
  85
  86 static inline void apic_clear_vector(int vec, void *bitmap)
  87 {
  88         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  89 }
  90
  91 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
  92 {
  93         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  94 }
  95
  96 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
  97 {
  98         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 struct static_key_deferred apic_hw_disabled __read_mostly;
 102 struct static_key_deferred apic_sw_disabled __read_mostly;
 103
 104 static inline int apic_enabled(struct kvm_lapic *apic)
 105 {
 106         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 107 }
 108
 109 #define LVT_MASK        \
 110         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 111
 112 #define LINT_MASK       \
 113         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 114          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 115
 116 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
 117 {
 118         return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
 119 }
 120
 121 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
 122 {
 123         return apic->vcpu->vcpu_id;
 124 }
 125
 126 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
 127                 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
 128         switch (map->mode) {
 129         case KVM_APIC_MODE_X2APIC: {
 130                 u32 offset = (dest_id >> 16) * 16;
 131                 u32 max_apic_id = map->max_apic_id;
 132
 133                 if (offset <= max_apic_id) {
 134                         u8 cluster_size = min(max_apic_id - offset + 1, 16U);
 135
 136                         *cluster = &map->phys_map[offset];
 137                         *mask = dest_id & (0xffff >> (16 - cluster_size));
 138                 } else {
 139                         *mask = 0;
 140                 }
 141
 142                 return true;
 143                 }
 144         case KVM_APIC_MODE_XAPIC_FLAT:
 145                 *cluster = map->xapic_flat_map;
 146                 *mask = dest_id & 0xff;
 147                 return true;
 148         case KVM_APIC_MODE_XAPIC_CLUSTER:
 149                 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
 150                 *mask = dest_id & 0xf;
 151                 return true;
 152         default:
 153                 /* Not optimized. */
 154                 return false;
 155         }
 156 }
 157
 158 static void kvm_apic_map_free(struct rcu_head *rcu)
 159 {
 160         struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
 161
 162         kvfree(map);
 163 }
 164
 165 static void recalculate_apic_map(struct kvm *kvm)
 166 {
 167         struct kvm_apic_map *new, *old = NULL;
 168         struct kvm_vcpu *vcpu;
 169         int i;
 170         u32 max_id = 255; /* enough space for any xAPIC ID */
 171
 172         mutex_lock(&kvm->arch.apic_map_lock);
 173
 174         kvm_for_each_vcpu(i, vcpu, kvm)
 175                 if (kvm_apic_present(vcpu))
 176                         max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
 177
 178         new = kvzalloc(sizeof(struct kvm_apic_map) +
 179                            sizeof(struct kvm_lapic *) * ((u64)max_id + 1), GFP_KERNEL);
 180
 181         if (!new)
 182                 goto out;
 183
 184         new->max_apic_id = max_id;
 185
 186         kvm_for_each_vcpu(i, vcpu, kvm) {
 187                 struct kvm_lapic *apic = vcpu->arch.apic;
 188                 struct kvm_lapic **cluster;
 189                 u16 mask;
 190                 u32 ldr;
 191                 u8 xapic_id;
 192                 u32 x2apic_id;
 193
 194                 if (!kvm_apic_present(vcpu))
 195                         continue;
 196
 197                 xapic_id = kvm_xapic_id(apic);
 198                 x2apic_id = kvm_x2apic_id(apic);
 199
 200                 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
 201                 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
 202                                 x2apic_id <= new->max_apic_id)
 203                         new->phys_map[x2apic_id] = apic;
 204                 /*
 205                  * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
 206                  * prevent them from masking VCPUs with APIC ID <= 0xff.
 207                  */
 208                 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
 209                         new->phys_map[xapic_id] = apic;
 210
 211                 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
 212
 213                 if (apic_x2apic_mode(apic)) {
 214                         new->mode |= KVM_APIC_MODE_X2APIC;
 215                 } else if (ldr) {
 216                         ldr = GET_APIC_LOGICAL_ID(ldr);
 217                         if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
 218                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
 219                         else
 220                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
 221                 }
 222
 223                 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
 224                         continue;
 225
 226                 if (mask)
 227                         cluster[ffs(mask) - 1] = apic;
 228         }
 229 out:
 230         old = rcu_dereference_protected(kvm->arch.apic_map,
 231                         lockdep_is_held(&kvm->arch.apic_map_lock));
 232         rcu_assign_pointer(kvm->arch.apic_map, new);
 233         mutex_unlock(&kvm->arch.apic_map_lock);
 234
 235         if (old)
 236                 call_rcu(&old->rcu, kvm_apic_map_free);
 237
 238         kvm_make_scan_ioapic_request(kvm);
 239 }
 240
 241 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 242 {
 243         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 244
 245         kvm_lapic_set_reg(apic, APIC_SPIV, val);
 246
 247         if (enabled != apic->sw_enabled) {
 248                 apic->sw_enabled = enabled;
 249                 if (enabled) {
 250                         static_key_slow_dec_deferred(&apic_sw_disabled);
 251                         recalculate_apic_map(apic->vcpu->kvm);
 252                 } else
 253                         static_key_slow_inc(&apic_sw_disabled.key);
 254         }
 255 }
 256
 257 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
 258 {
 259         kvm_lapic_set_reg(apic, APIC_ID, id << 24);
 260         recalculate_apic_map(apic->vcpu->kvm);
 261 }
 262
 263 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 264 {
 265         kvm_lapic_set_reg(apic, APIC_LDR, id);
 266         recalculate_apic_map(apic->vcpu->kvm);
 267 }
 268
 269 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
 270 {
 271         return ((id >> 4) << 16) | (1 << (id & 0xf));
 272 }
 273
 274 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
 275 {
 276         u32 ldr = kvm_apic_calc_x2apic_ldr(id);
 277
 278         WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
 279
 280         kvm_lapic_set_reg(apic, APIC_ID, id);
 281         kvm_lapic_set_reg(apic, APIC_LDR, ldr);
 282         recalculate_apic_map(apic->vcpu->kvm);
 283 }
 284
 285 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 286 {
 287         return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 288 }
 289
 290 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 291 {
 292         return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 293 }
 294
 295 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 296 {
 297         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 298 }
 299
 300 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 301 {
 302         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 303 }
 304
 305 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 306 {
 307         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 308 }
 309
 310 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 311 {
 312         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 313 }
 314
 315 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 316 {
 317         struct kvm_lapic *apic = vcpu->arch.apic;
 318         struct kvm_cpuid_entry2 *feat;
 319         u32 v = APIC_VERSION;
 320
 321         if (!lapic_in_kernel(vcpu))
 322                 return;
 323
 324         /*
 325          * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
 326          * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
 327          * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
 328          * version first and level-triggered interrupts never get EOIed in
 329          * IOAPIC.
 330          */
 331         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 332         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
 333             !ioapic_in_kernel(vcpu->kvm))
 334                 v |= APIC_LVR_DIRECTED_EOI;
 335         kvm_lapic_set_reg(apic, APIC_LVR, v);
 336 }
 337
 338 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
 339         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 340         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 341         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 342         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 343         LVT_MASK                /* LVTERR */
 344 };
 345
 346 static int find_highest_vector(void *bitmap)
 347 {
 348         int vec;
 349         u32 *reg;
 350
 351         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 352              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 353                 reg = bitmap + REG_POS(vec);
 354                 if (*reg)
 355                         return __fls(*reg) + vec;
 356         }
 357
 358         return -1;
 359 }
 360
 361 static u8 count_vectors(void *bitmap)
 362 {
 363         int vec;
 364         u32 *reg;
 365         u8 count = 0;
 366
 367         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 368                 reg = bitmap + REG_POS(vec);
 369                 count += hweight32(*reg);
 370         }
 371
 372         return count;
 373 }
 374
 375 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
 376 {
 377         u32 i, vec;
 378         u32 pir_val, irr_val, prev_irr_val;
 379         int max_updated_irr;
 380
 381         max_updated_irr = -1;
 382         *max_irr = -1;
 383
 384         for (i = vec = 0; i <= 7; i++, vec += 32) {
 385                 pir_val = READ_ONCE(pir[i]);
 386                 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
 387                 if (pir_val) {
 388                         prev_irr_val = irr_val;
 389                         irr_val |= xchg(&pir[i], 0);
 390                         *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
 391                         if (prev_irr_val != irr_val) {
 392                                 max_updated_irr =
 393                                         __fls(irr_val ^ prev_irr_val) + vec;
 394                         }
 395                 }
 396                 if (irr_val)
 397                         *max_irr = __fls(irr_val) + vec;
 398         }
 399
 400         return ((max_updated_irr != -1) &&
 401                 (max_updated_irr == *max_irr));
 402 }
 403 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 404
 405 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
 406 {
 407         struct kvm_lapic *apic = vcpu->arch.apic;
 408
 409         return __kvm_apic_update_irr(pir, apic->regs, max_irr);
 410 }
 411 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 412
 413 static inline int apic_search_irr(struct kvm_lapic *apic)
 414 {
 415         return find_highest_vector(apic->regs + APIC_IRR);
 416 }
 417
 418 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 419 {
 420         int result;
 421
 422         /*
 423          * Note that irr_pending is just a hint. It will be always
 424          * true with virtual interrupt delivery enabled.
 425          */
 426         if (!apic->irr_pending)
 427                 return -1;
 428
 429         result = apic_search_irr(apic);
 430         ASSERT(result == -1 || result >= 16);
 431
 432         return result;
 433 }
 434
 435 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 436 {
 437         struct kvm_vcpu *vcpu;
 438
 439         vcpu = apic->vcpu;
 440
 441         if (unlikely(vcpu->arch.apicv_active)) {
 442                 /* need to update RVI */
 443                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 444                 kvm_x86_ops->hwapic_irr_update(vcpu,
 445                                 apic_find_highest_irr(apic));
 446         } else {
 447                 apic->irr_pending = false;
 448                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 449                 if (apic_search_irr(apic) != -1)
 450                         apic->irr_pending = true;
 451         }
 452 }
 453
 454 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 455 {
 456         struct kvm_vcpu *vcpu;
 457
 458         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 459                 return;
 460
 461         vcpu = apic->vcpu;
 462
 463         /*
 464          * With APIC virtualization enabled, all caching is disabled
 465          * because the processor can modify ISR under the hood.  Instead
 466          * just set SVI.
 467          */
 468         if (unlikely(vcpu->arch.apicv_active))
 469                 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
 470         else {
 471                 ++apic->isr_count;
 472                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 473                 /*
 474                  * ISR (in service register) bit is set when injecting an interrupt.
 475                  * The highest vector is injected. Thus the latest bit set matches
 476                  * the highest bit in ISR.
 477                  */
 478                 apic->highest_isr_cache = vec;
 479         }
 480 }
 481
 482 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 483 {
 484         int result;
 485
 486         /*
 487          * Note that isr_count is always 1, and highest_isr_cache
 488          * is always -1, with APIC virtualization enabled.
 489          */
 490         if (!apic->isr_count)
 491                 return -1;
 492         if (likely(apic->highest_isr_cache != -1))
 493                 return apic->highest_isr_cache;
 494
 495         result = find_highest_vector(apic->regs + APIC_ISR);
 496         ASSERT(result == -1 || result >= 16);
 497
 498         return result;
 499 }
 500
 501 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 502 {
 503         struct kvm_vcpu *vcpu;
 504         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 505                 return;
 506
 507         vcpu = apic->vcpu;
 508
 509         /*
 510          * We do get here for APIC virtualization enabled if the guest
 511          * uses the Hyper-V APIC enlightenment.  In this case we may need
 512          * to trigger a new interrupt delivery by writing the SVI field;
 513          * on the other hand isr_count and highest_isr_cache are unused
 514          * and must be left alone.
 515          */
 516         if (unlikely(vcpu->arch.apicv_active))
 517                 kvm_x86_ops->hwapic_isr_update(vcpu,
 518                                                apic_find_highest_isr(apic));
 519         else {
 520                 --apic->isr_count;
 521                 BUG_ON(apic->isr_count < 0);
 522                 apic->highest_isr_cache = -1;
 523         }
 524 }
 525
 526 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 527 {
 528         /* This may race with setting of irr in __apic_accept_irq() and
 529          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 530          * will cause vmexit immediately and the value will be recalculated
 531          * on the next vmentry.
 532          */
 533         return apic_find_highest_irr(vcpu->arch.apic);
 534 }
 535 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 536
 537 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 538                              int vector, int level, int trig_mode,
 539                              struct dest_map *dest_map);
 540
 541 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 542                      struct dest_map *dest_map)
 543 {
 544         struct kvm_lapic *apic = vcpu->arch.apic;
 545
 546         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 547                         irq->level, irq->trig_mode, dest_map);
 548 }
 549
 550 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
 551                     unsigned long ipi_bitmap_high, u32 min,
 552                     unsigned long icr, int op_64_bit)
 553 {
 554         int i;
 555         struct kvm_apic_map *map;
 556         struct kvm_vcpu *vcpu;
 557         struct kvm_lapic_irq irq = {0};
 558         int cluster_size = op_64_bit ? 64 : 32;
 559         int count = 0;
 560
 561         irq.vector = icr & APIC_VECTOR_MASK;
 562         irq.delivery_mode = icr & APIC_MODE_MASK;
 563         irq.level = (icr & APIC_INT_ASSERT) != 0;
 564         irq.trig_mode = icr & APIC_INT_LEVELTRIG;
 565
 566         if (icr & APIC_DEST_MASK)
 567                 return -KVM_EINVAL;
 568         if (icr & APIC_SHORT_MASK)
 569                 return -KVM_EINVAL;
 570
 571         rcu_read_lock();
 572         map = rcu_dereference(kvm->arch.apic_map);
 573
 574         if (min > map->max_apic_id)
 575                 goto out;
 576         /* Bits above cluster_size are masked in the caller.  */
 577         for_each_set_bit(i, &ipi_bitmap_low,
 578                 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
 579                 if (map->phys_map[min + i]) {
 580                         vcpu = map->phys_map[min + i]->vcpu;
 581                         count += kvm_apic_set_irq(vcpu, &irq, NULL);
 582                 }
 583         }
 584
 585         min += cluster_size;
 586
 587         if (min > map->max_apic_id)
 588                 goto out;
 589
 590         for_each_set_bit(i, &ipi_bitmap_high,
 591                 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
 592                 if (map->phys_map[min + i]) {
 593                         vcpu = map->phys_map[min + i]->vcpu;
 594                         count += kvm_apic_set_irq(vcpu, &irq, NULL);
 595                 }
 596         }
 597
 598 out:
 599         rcu_read_unlock();
 600         return count;
 601 }
 602
 603 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 604 {
 605
 606         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 607                                       sizeof(val));
 608 }
 609
 610 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 611 {
 612
 613         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 614                                       sizeof(*val));
 615 }
 616
 617 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 618 {
 619         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 620 }
 621
 622 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 623 {
 624         u8 val;
 625         if (pv_eoi_get_user(vcpu, &val) < 0)
 626                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 627                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 628         return val & 0x1;
 629 }
 630
 631 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 632 {
 633         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 634                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 635                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 636                 return;
 637         }
 638         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 639 }
 640
 641 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 642 {
 643         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 644                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 645                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 646                 return;
 647         }
 648         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 649 }
 650
 651 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
 652 {
 653         int highest_irr;
 654         if (apic->vcpu->arch.apicv_active)
 655                 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 656         else
 657                 highest_irr = apic_find_highest_irr(apic);
 658         if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
 659                 return -1;
 660         return highest_irr;
 661 }
 662
 663 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
 664 {
 665         u32 tpr, isrv, ppr, old_ppr;
 666         int isr;
 667
 668         old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
 669         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
 670         isr = apic_find_highest_isr(apic);
 671         isrv = (isr != -1) ? isr : 0;
 672
 673         if ((tpr & 0xf0) >= (isrv & 0xf0))
 674                 ppr = tpr & 0xff;
 675         else
 676                 ppr = isrv & 0xf0;
 677
 678         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 679                    apic, ppr, isr, isrv);
 680
 681         *new_ppr = ppr;
 682         if (old_ppr != ppr)
 683                 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
 684
 685         return ppr < old_ppr;
 686 }
 687
 688 static void apic_update_ppr(struct kvm_lapic *apic)
 689 {
 690         u32 ppr;
 691
 692         if (__apic_update_ppr(apic, &ppr) &&
 693             apic_has_interrupt_for_ppr(apic, ppr) != -1)
 694                 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 695 }
 696
 697 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
 698 {
 699         apic_update_ppr(vcpu->arch.apic);
 700 }
 701 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
 702
 703 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 704 {
 705         kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
 706         apic_update_ppr(apic);
 707 }
 708
 709 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 710 {
 711         return mda == (apic_x2apic_mode(apic) ?
 712                         X2APIC_BROADCAST : APIC_BROADCAST);
 713 }
 714
 715 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 716 {
 717         if (kvm_apic_broadcast(apic, mda))
 718                 return true;
 719
 720         if (apic_x2apic_mode(apic))
 721                 return mda == kvm_x2apic_id(apic);
 722
 723         /*
 724          * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
 725          * it were in x2APIC mode.  Hotplugged VCPUs start in xAPIC mode and
 726          * this allows unique addressing of VCPUs with APIC ID over 0xff.
 727          * The 0xff condition is needed because writeable xAPIC ID.
 728          */
 729         if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
 730                 return true;
 731
 732         return mda == kvm_xapic_id(apic);
 733 }
 734
 735 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 736 {
 737         u32 logical_id;
 738
 739         if (kvm_apic_broadcast(apic, mda))
 740                 return true;
 741
 742         logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
 743
 744         if (apic_x2apic_mode(apic))
 745                 return ((logical_id >> 16) == (mda >> 16))
 746                        && (logical_id & mda & 0xffff) != 0;
 747
 748         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 749
 750         switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
 751         case APIC_DFR_FLAT:
 752                 return (logical_id & mda) != 0;
 753         case APIC_DFR_CLUSTER:
 754                 return ((logical_id >> 4) == (mda >> 4))
 755                        && (logical_id & mda & 0xf) != 0;
 756         default:
 757                 apic_debug("Bad DFR vcpu %d: %08x\n",
 758                            apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
 759                 return false;
 760         }
 761 }
 762
 763 /* The KVM local APIC implementation has two quirks:
 764  *
 765  *  - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
 766  *    in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
 767  *    KVM doesn't do that aliasing.
 768  *
 769  *  - in-kernel IOAPIC messages have to be delivered directly to
 770  *    x2APIC, because the kernel does not support interrupt remapping.
 771  *    In order to support broadcast without interrupt remapping, x2APIC
 772  *    rewrites the destination of non-IPI messages from APIC_BROADCAST
 773  *    to X2APIC_BROADCAST.
 774  *
 775  * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API.  This is
 776  * important when userspace wants to use x2APIC-format MSIs, because
 777  * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
 778  */
 779 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
 780                 struct kvm_lapic *source, struct kvm_lapic *target)
 781 {
 782         bool ipi = source != NULL;
 783
 784         if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
 785             !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
 786                 return X2APIC_BROADCAST;
 787
 788         return dest_id;
 789 }
 790
 791 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 792                            int short_hand, unsigned int dest, int dest_mode)
 793 {
 794         struct kvm_lapic *target = vcpu->arch.apic;
 795         u32 mda = kvm_apic_mda(vcpu, dest, source, target);
 796
 797         apic_debug("target %p, source %p, dest 0x%x, "
 798                    "dest_mode 0x%x, short_hand 0x%x\n",
 799                    target, source, dest, dest_mode, short_hand);
 800
 801         ASSERT(target);
 802         switch (short_hand) {
 803         case APIC_DEST_NOSHORT:
 804                 if (dest_mode == APIC_DEST_PHYSICAL)
 805                         return kvm_apic_match_physical_addr(target, mda);
 806                 else
 807                         return kvm_apic_match_logical_addr(target, mda);
 808         case APIC_DEST_SELF:
 809                 return target == source;
 810         case APIC_DEST_ALLINC:
 811                 return true;
 812         case APIC_DEST_ALLBUT:
 813                 return target != source;
 814         default:
 815                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 816                            short_hand);
 817                 return false;
 818         }
 819 }
 820 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
 821
 822 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 823                        const unsigned long *bitmap, u32 bitmap_size)
 824 {
 825         u32 mod;
 826         int i, idx = -1;
 827
 828         mod = vector % dest_vcpus;
 829
 830         for (i = 0; i <= mod; i++) {
 831                 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
 832                 BUG_ON(idx == bitmap_size);
 833         }
 834
 835         return idx;
 836 }
 837
 838 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
 839 {
 840         if (!kvm->arch.disabled_lapic_found) {
 841                 kvm->arch.disabled_lapic_found = true;
 842                 printk(KERN_INFO
 843                        "Disabled LAPIC found during irq injection\n");
 844         }
 845 }
 846
 847 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
 848                 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
 849 {
 850         if (kvm->arch.x2apic_broadcast_quirk_disabled) {
 851                 if ((irq->dest_id == APIC_BROADCAST &&
 852                                 map->mode != KVM_APIC_MODE_X2APIC))
 853                         return true;
 854                 if (irq->dest_id == X2APIC_BROADCAST)
 855                         return true;
 856         } else {
 857                 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
 858                 if (irq->dest_id == (x2apic_ipi ?
 859                                      X2APIC_BROADCAST : APIC_BROADCAST))
 860                         return true;
 861         }
 862
 863         return false;
 864 }
 865
 866 /* Return true if the interrupt can be handled by using *bitmap as index mask
 867  * for valid destinations in *dst array.
 868  * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
 869  * Note: we may have zero kvm_lapic destinations when we return true, which
 870  * means that the interrupt should be dropped.  In this case, *bitmap would be
 871  * zero and *dst undefined.
 872  */
 873 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
 874                 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
 875                 struct kvm_apic_map *map, struct kvm_lapic ***dst,
 876                 unsigned long *bitmap)
 877 {
 878         int i, lowest;
 879
 880         if (irq->shorthand == APIC_DEST_SELF && src) {
 881                 *dst = src;
 882                 *bitmap = 1;
 883                 return true;
 884         } else if (irq->shorthand)
 885                 return false;
 886
 887         if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
 888                 return false;
 889
 890         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 891                 if (irq->dest_id > map->max_apic_id) {
 892                         *bitmap = 0;
 893                 } else {
 894                         *dst = &map->phys_map[irq->dest_id];
 895                         *bitmap = 1;
 896                 }
 897                 return true;
 898         }
 899
 900         *bitmap = 0;
 901         if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
 902                                 (u16 *)bitmap))
 903                 return false;
 904
 905         if (!kvm_lowest_prio_delivery(irq))
 906                 return true;
 907
 908         if (!kvm_vector_hashing_enabled()) {
 909                 lowest = -1;
 910                 for_each_set_bit(i, bitmap, 16) {
 911                         if (!(*dst)[i])
 912                                 continue;
 913                         if (lowest < 0)
 914                                 lowest = i;
 915                         else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
 916                                                 (*dst)[lowest]->vcpu) < 0)
 917                                 lowest = i;
 918                 }
 919         } else {
 920                 if (!*bitmap)
 921                         return true;
 922
 923                 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
 924                                 bitmap, 16);
 925
 926                 if (!(*dst)[lowest]) {
 927                         kvm_apic_disabled_lapic_found(kvm);
 928                         *bitmap = 0;
 929                         return true;
 930                 }
 931         }
 932
 933         *bitmap = (lowest >= 0) ? 1 << lowest : 0;
 934
 935         return true;
 936 }
 937
 938 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 939                 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
 940 {
 941         struct kvm_apic_map *map;
 942         unsigned long bitmap;
 943         struct kvm_lapic **dst = NULL;
 944         int i;
 945         bool ret;
 946
 947         *r = -1;
 948
 949         if (irq->shorthand == APIC_DEST_SELF) {
 950                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 951                 return true;
 952         }
 953
 954         rcu_read_lock();
 955         map = rcu_dereference(kvm->arch.apic_map);
 956
 957         ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
 958         if (ret)
 959                 for_each_set_bit(i, &bitmap, 16) {
 960                         if (!dst[i])
 961                                 continue;
 962                         if (*r < 0)
 963                                 *r = 0;
 964                         *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 965                 }
 966
 967         rcu_read_unlock();
 968         return ret;
 969 }
 970
 971 /*
 972  * This routine tries to handler interrupts in posted mode, here is how
 973  * it deals with different cases:
 974  * - For single-destination interrupts, handle it in posted mode
 975  * - Else if vector hashing is enabled and it is a lowest-priority
 976  *   interrupt, handle it in posted mode and use the following mechanism
 977  *   to find the destinaiton vCPU.
 978  *      1. For lowest-priority interrupts, store all the possible
 979  *         destination vCPUs in an array.
 980  *      2. Use "guest vector % max number of destination vCPUs" to find
 981  *         the right destination vCPU in the array for the lowest-priority
 982  *         interrupt.
 983  * - Otherwise, use remapped mode to inject the interrupt.
 984  */
 985 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 986                         struct kvm_vcpu **dest_vcpu)
 987 {
 988         struct kvm_apic_map *map;
 989         unsigned long bitmap;
 990         struct kvm_lapic **dst = NULL;
 991         bool ret = false;
 992
 993         if (irq->shorthand)
 994                 return false;
 995
 996         rcu_read_lock();
 997         map = rcu_dereference(kvm->arch.apic_map);
 998
 999         if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1000                         hweight16(bitmap) == 1) {
1001                 unsigned long i = find_first_bit(&bitmap, 16);
1002
1003                 if (dst[i]) {
1004                         *dest_vcpu = dst[i]->vcpu;
1005                         ret = true;
1006                 }
1007         }
1008
1009         rcu_read_unlock();
1010         return ret;
1011 }
1012
1013 /*
1014  * Add a pending IRQ into lapic.
1015  * Return 1 if successfully added and 0 if discarded.
1016  */
1017 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1018                              int vector, int level, int trig_mode,
1019                              struct dest_map *dest_map)
1020 {
1021         int result = 0;
1022         struct kvm_vcpu *vcpu = apic->vcpu;
1023
1024         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1025                                   trig_mode, vector);
1026         switch (delivery_mode) {
1027         case APIC_DM_LOWEST:
1028                 vcpu->arch.apic_arb_prio++;
1029         case APIC_DM_FIXED:
1030                 if (unlikely(trig_mode && !level))
1031                         break;
1032
1033                 /* FIXME add logic for vcpu on reset */
1034                 if (unlikely(!apic_enabled(apic)))
1035                         break;
1036
1037                 result = 1;
1038
1039                 if (dest_map) {
1040                         __set_bit(vcpu->vcpu_id, dest_map->map);
1041                         dest_map->vectors[vcpu->vcpu_id] = vector;
1042                 }
1043
1044                 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1045                         if (trig_mode)
1046                                 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
1047                         else
1048                                 apic_clear_vector(vector, apic->regs + APIC_TMR);
1049                 }
1050
1051                 if (vcpu->arch.apicv_active)
1052                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
1053                 else {
1054                         kvm_lapic_set_irr(vector, apic);
1055
1056                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1057                         kvm_vcpu_kick(vcpu);
1058                 }
1059                 break;
1060
1061         case APIC_DM_REMRD:
1062                 result = 1;
1063                 vcpu->arch.pv.pv_unhalted = 1;
1064                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1065                 kvm_vcpu_kick(vcpu);
1066                 break;
1067
1068         case APIC_DM_SMI:
1069                 result = 1;
1070                 kvm_make_request(KVM_REQ_SMI, vcpu);
1071                 kvm_vcpu_kick(vcpu);
1072                 break;
1073
1074         case APIC_DM_NMI:
1075                 result = 1;
1076                 kvm_inject_nmi(vcpu);
1077                 kvm_vcpu_kick(vcpu);
1078                 break;
1079
1080         case APIC_DM_INIT:
1081                 if (!trig_mode || level) {
1082                         result = 1;
1083                         /* assumes that there are only KVM_APIC_INIT/SIPI */
1084                         apic->pending_events = (1UL << KVM_APIC_INIT);
1085                         /* make sure pending_events is visible before sending
1086                          * the request */
1087                         smp_wmb();
1088                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1089                         kvm_vcpu_kick(vcpu);
1090                 } else {
1091                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1092                                    vcpu->vcpu_id);
1093                 }
1094                 break;
1095
1096         case APIC_DM_STARTUP:
1097                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1098                            vcpu->vcpu_id, vector);
1099                 result = 1;
1100                 apic->sipi_vector = vector;
1101                 /* make sure sipi_vector is visible for the receiver */
1102                 smp_wmb();
1103                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1104                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1105                 kvm_vcpu_kick(vcpu);
1106                 break;
1107
1108         case APIC_DM_EXTINT:
1109                 /*
1110                  * Should only be called by kvm_apic_local_deliver() with LVT0,
1111                  * before NMI watchdog was enabled. Already handled by
1112                  * kvm_apic_accept_pic_intr().
1113                  */
1114                 break;
1115
1116         default:
1117                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1118                        delivery_mode);
1119                 break;
1120         }
1121         return result;
1122 }
1123
1124 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1125 {
1126         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1127 }
1128
1129 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1130 {
1131         return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1132 }
1133
1134 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1135 {
1136         int trigger_mode;
1137
1138         /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1139         if (!kvm_ioapic_handles_vector(apic, vector))
1140                 return;
1141
1142         /* Request a KVM exit to inform the userspace IOAPIC. */
1143         if (irqchip_split(apic->vcpu->kvm)) {
1144                 apic->vcpu->arch.pending_ioapic_eoi = vector;
1145                 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1146                 return;
1147         }
1148
1149         if (apic_test_vector(vector, apic->regs + APIC_TMR))
1150                 trigger_mode = IOAPIC_LEVEL_TRIG;
1151         else
1152                 trigger_mode = IOAPIC_EDGE_TRIG;
1153
1154         kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1155 }
1156
1157 static int apic_set_eoi(struct kvm_lapic *apic)
1158 {
1159         int vector = apic_find_highest_isr(apic);
1160
1161         trace_kvm_eoi(apic, vector);
1162
1163         /*
1164          * Not every write EOI will has corresponding ISR,
1165          * one example is when Kernel check timer on setup_IO_APIC
1166          */
1167         if (vector == -1)
1168                 return vector;
1169
1170         apic_clear_isr(vector, apic);
1171         apic_update_ppr(apic);
1172
1173         if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1174                 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1175
1176         kvm_ioapic_send_eoi(apic, vector);
1177         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1178         return vector;
1179 }
1180
1181 /*
1182  * this interface assumes a trap-like exit, which has already finished
1183  * desired side effect including vISR and vPPR update.
1184  */
1185 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1186 {
1187         struct kvm_lapic *apic = vcpu->arch.apic;
1188
1189         trace_kvm_eoi(apic, vector);
1190
1191         kvm_ioapic_send_eoi(apic, vector);
1192         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1193 }
1194 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1195
1196 static void apic_send_ipi(struct kvm_lapic *apic)
1197 {
1198         u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1199         u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1200         struct kvm_lapic_irq irq;
1201
1202         irq.vector = icr_low & APIC_VECTOR_MASK;
1203         irq.delivery_mode = icr_low & APIC_MODE_MASK;
1204         irq.dest_mode = icr_low & APIC_DEST_MASK;
1205         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1206         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1207         irq.shorthand = icr_low & APIC_SHORT_MASK;
1208         irq.msi_redir_hint = false;
1209         if (apic_x2apic_mode(apic))
1210                 irq.dest_id = icr_high;
1211         else
1212                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1213
1214         trace_kvm_apic_ipi(icr_low, irq.dest_id);
1215
1216         apic_debug("icr_high 0x%x, icr_low 0x%x, "
1217                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1218                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1219                    "msi_redir_hint 0x%x\n",
1220                    icr_high, icr_low, irq.shorthand, irq.dest_id,
1221                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1222                    irq.vector, irq.msi_redir_hint);
1223
1224         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1225 }
1226
1227 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1228 {
1229         ktime_t remaining, now;
1230         s64 ns;
1231         u32 tmcct;
1232
1233         ASSERT(apic != NULL);
1234
1235         /* if initial count is 0, current count should also be 0 */
1236         if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1237                 apic->lapic_timer.period == 0)
1238                 return 0;
1239
1240         now = ktime_get();
1241         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1242         if (ktime_to_ns(remaining) < 0)
1243                 remaining = 0;
1244
1245         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1246         tmcct = div64_u64(ns,
1247                          (APIC_BUS_CYCLE_NS * apic->divide_count));
1248
1249         return tmcct;
1250 }
1251
1252 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1253 {
1254         struct kvm_vcpu *vcpu = apic->vcpu;
1255         struct kvm_run *run = vcpu->run;
1256
1257         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1258         run->tpr_access.rip = kvm_rip_read(vcpu);
1259         run->tpr_access.is_write = write;
1260 }
1261
1262 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1263 {
1264         if (apic->vcpu->arch.tpr_access_reporting)
1265                 __report_tpr_access(apic, write);
1266 }
1267
1268 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1269 {
1270         u32 val = 0;
1271
1272         if (offset >= LAPIC_MMIO_LENGTH)
1273                 return 0;
1274
1275         switch (offset) {
1276         case APIC_ARBPRI:
1277                 apic_debug("Access APIC ARBPRI register which is for P6\n");
1278                 break;
1279
1280         case APIC_TMCCT:        /* Timer CCR */
1281                 if (apic_lvtt_tscdeadline(apic))
1282                         return 0;
1283
1284                 val = apic_get_tmcct(apic);
1285                 break;
1286         case APIC_PROCPRI:
1287                 apic_update_ppr(apic);
1288                 val = kvm_lapic_get_reg(apic, offset);
1289                 break;
1290         case APIC_TASKPRI:
1291                 report_tpr_access(apic, false);
1292                 /* fall thru */
1293         default:
1294                 val = kvm_lapic_get_reg(apic, offset);
1295                 break;
1296         }
1297
1298         return val;
1299 }
1300
1301 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1302 {
1303         return container_of(dev, struct kvm_lapic, dev);
1304 }
1305
1306 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1307                 void *data)
1308 {
1309         unsigned char alignment = offset & 0xf;
1310         u32 result;
1311         /* this bitmask has a bit cleared for each reserved register */
1312         static const u64 rmask = 0x43ff01ffffffe70cULL;
1313
1314         if ((alignment + len) > 4) {
1315                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1316                            offset, len);
1317                 return 1;
1318         }
1319
1320         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1321                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1322                            offset);
1323                 return 1;
1324         }
1325
1326         result = __apic_read(apic, offset & ~0xf);
1327
1328         trace_kvm_apic_read(offset, result);
1329
1330         switch (len) {
1331         case 1:
1332         case 2:
1333         case 4:
1334                 memcpy(data, (char *)&result + alignment, len);
1335                 break;
1336         default:
1337                 printk(KERN_ERR "Local APIC read with len = %x, "
1338                        "should be 1,2, or 4 instead\n", len);
1339                 break;
1340         }
1341         return 0;
1342 }
1343 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1344
1345 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1346 {
1347         return addr >= apic->base_address &&
1348                 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1349 }
1350
1351 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1352                            gpa_t address, int len, void *data)
1353 {
1354         struct kvm_lapic *apic = to_lapic(this);
1355         u32 offset = address - apic->base_address;
1356
1357         if (!apic_mmio_in_range(apic, address))
1358                 return -EOPNOTSUPP;
1359
1360         if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1361                 if (!kvm_check_has_quirk(vcpu->kvm,
1362                                          KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1363                         return -EOPNOTSUPP;
1364
1365                 memset(data, 0xff, len);
1366                 return 0;
1367         }
1368
1369         kvm_lapic_reg_read(apic, offset, len, data);
1370
1371         return 0;
1372 }
1373
1374 static void update_divide_count(struct kvm_lapic *apic)
1375 {
1376         u32 tmp1, tmp2, tdcr;
1377
1378         tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1379         tmp1 = tdcr & 0xf;
1380         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1381         apic->divide_count = 0x1 << (tmp2 & 0x7);
1382
1383         apic_debug("timer divide count is 0x%x\n",
1384                                    apic->divide_count);
1385 }
1386
1387 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1388 {
1389         /*
1390          * Do not allow the guest to program periodic timers with small
1391          * interval, since the hrtimers are not throttled by the host
1392          * scheduler.
1393          */
1394         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1395                 s64 min_period = min_timer_period_us * 1000LL;
1396
1397                 if (apic->lapic_timer.period < min_period) {
1398                         pr_info_ratelimited(
1399                             "kvm: vcpu %i: requested %lld ns "
1400                             "lapic timer period limited to %lld ns\n",
1401                             apic->vcpu->vcpu_id,
1402                             apic->lapic_timer.period, min_period);
1403                         apic->lapic_timer.period = min_period;
1404                 }
1405         }
1406 }
1407
1408 static void apic_update_lvtt(struct kvm_lapic *apic)
1409 {
1410         u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1411                         apic->lapic_timer.timer_mode_mask;
1412
1413         if (apic->lapic_timer.timer_mode != timer_mode) {
1414                 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1415                                 APIC_LVT_TIMER_TSCDEADLINE)) {
1416                         hrtimer_cancel(&apic->lapic_timer.timer);
1417                         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1418                         apic->lapic_timer.period = 0;
1419                         apic->lapic_timer.tscdeadline = 0;
1420                 }
1421                 apic->lapic_timer.timer_mode = timer_mode;
1422                 limit_periodic_timer_frequency(apic);
1423         }
1424 }
1425
1426 static void apic_timer_expired(struct kvm_lapic *apic)
1427 {
1428         struct kvm_vcpu *vcpu = apic->vcpu;
1429         struct swait_queue_head *q = &vcpu->wq;
1430         struct kvm_timer *ktimer = &apic->lapic_timer;
1431
1432         if (atomic_read(&apic->lapic_timer.pending))
1433                 return;
1434
1435         atomic_inc(&apic->lapic_timer.pending);
1436         kvm_set_pending_timer(vcpu);
1437
1438         /*
1439          * For x86, the atomic_inc() is serialized, thus
1440          * using swait_active() is safe.
1441          */
1442         if (swait_active(q))
1443                 swake_up_one(q);
1444
1445         if (apic_lvtt_tscdeadline(apic))
1446                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1447 }
1448
1449 /*
1450  * On APICv, this test will cause a busy wait
1451  * during a higher-priority task.
1452  */
1453
1454 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1455 {
1456         struct kvm_lapic *apic = vcpu->arch.apic;
1457         u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1458
1459         if (kvm_apic_hw_enabled(apic)) {
1460                 int vec = reg & APIC_VECTOR_MASK;
1461                 void *bitmap = apic->regs + APIC_ISR;
1462
1463                 if (vcpu->arch.apicv_active)
1464                         bitmap = apic->regs + APIC_IRR;
1465
1466                 if (apic_test_vector(vec, bitmap))
1467                         return true;
1468         }
1469         return false;
1470 }
1471
1472 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1473 {
1474         struct kvm_lapic *apic = vcpu->arch.apic;
1475         u64 guest_tsc, tsc_deadline;
1476
1477         if (!lapic_in_kernel(vcpu))
1478                 return;
1479
1480         if (apic->lapic_timer.expired_tscdeadline == 0)
1481                 return;
1482
1483         if (!lapic_timer_int_injected(vcpu))
1484                 return;
1485
1486         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1487         apic->lapic_timer.expired_tscdeadline = 0;
1488         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1489         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1490
1491         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1492         if (guest_tsc < tsc_deadline)
1493                 __delay(min(tsc_deadline - guest_tsc,
1494                         nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
1495 }
1496
1497 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1498 {
1499         u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1500         u64 ns = 0;
1501         ktime_t expire;
1502         struct kvm_vcpu *vcpu = apic->vcpu;
1503         unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1504         unsigned long flags;
1505         ktime_t now;
1506
1507         if (unlikely(!tscdeadline || !this_tsc_khz))
1508                 return;
1509
1510         local_irq_save(flags);
1511
1512         now = ktime_get();
1513         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1514         if (likely(tscdeadline > guest_tsc)) {
1515                 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1516                 do_div(ns, this_tsc_khz);
1517                 expire = ktime_add_ns(now, ns);
1518                 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1519                 hrtimer_start(&apic->lapic_timer.timer,
1520                                 expire, HRTIMER_MODE_ABS_PINNED);
1521         } else
1522                 apic_timer_expired(apic);
1523
1524         local_irq_restore(flags);
1525 }
1526
1527 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1528 {
1529         ktime_t now, remaining;
1530         u64 ns_remaining_old, ns_remaining_new;
1531
1532         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1533                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1534         limit_periodic_timer_frequency(apic);
1535
1536         now = ktime_get();
1537         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1538         if (ktime_to_ns(remaining) < 0)
1539                 remaining = 0;
1540
1541         ns_remaining_old = ktime_to_ns(remaining);
1542         ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1543                                            apic->divide_count, old_divisor);
1544
1545         apic->lapic_timer.tscdeadline +=
1546                 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1547                 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1548         apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1549 }
1550
1551 static bool set_target_expiration(struct kvm_lapic *apic)
1552 {
1553         ktime_t now;
1554         u64 tscl = rdtsc();
1555
1556         now = ktime_get();
1557         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1558                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1559
1560         if (!apic->lapic_timer.period) {
1561                 apic->lapic_timer.tscdeadline = 0;
1562                 return false;
1563         }
1564
1565         limit_periodic_timer_frequency(apic);
1566
1567         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1568                    PRIx64 ", "
1569                    "timer initial count 0x%x, period %lldns, "
1570                    "expire @ 0x%016" PRIx64 ".\n", __func__,
1571                    APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1572                    kvm_lapic_get_reg(apic, APIC_TMICT),
1573                    apic->lapic_timer.period,
1574                    ktime_to_ns(ktime_add_ns(now,
1575                                 apic->lapic_timer.period)));
1576
1577         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1578                 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1579         apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1580
1581         return true;
1582 }
1583
1584 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1585 {
1586         ktime_t now = ktime_get();
1587         u64 tscl = rdtsc();
1588         ktime_t delta;
1589
1590         /*
1591          * Synchronize both deadlines to the same time source or
1592          * differences in the periods (caused by differences in the
1593          * underlying clocks or numerical approximation errors) will
1594          * cause the two to drift apart over time as the errors
1595          * accumulate.
1596          */
1597         apic->lapic_timer.target_expiration =
1598                 ktime_add_ns(apic->lapic_timer.target_expiration,
1599                                 apic->lapic_timer.period);
1600         delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1601         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1602                 nsec_to_cycles(apic->vcpu, delta);
1603 }
1604
1605 static void start_sw_period(struct kvm_lapic *apic)
1606 {
1607         if (!apic->lapic_timer.period)
1608                 return;
1609
1610         if (ktime_after(ktime_get(),
1611                         apic->lapic_timer.target_expiration)) {
1612                 apic_timer_expired(apic);
1613
1614                 if (apic_lvtt_oneshot(apic))
1615                         return;
1616
1617                 advance_periodic_target_expiration(apic);
1618         }
1619
1620         hrtimer_start(&apic->lapic_timer.timer,
1621                 apic->lapic_timer.target_expiration,
1622                 HRTIMER_MODE_ABS_PINNED);
1623 }
1624
1625 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1626 {
1627         if (!lapic_in_kernel(vcpu))
1628                 return false;
1629
1630         return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1631 }
1632 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1633
1634 static void cancel_hv_timer(struct kvm_lapic *apic)
1635 {
1636         WARN_ON(preemptible());
1637         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1638         kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1639         apic->lapic_timer.hv_timer_in_use = false;
1640 }
1641
1642 static bool start_hv_timer(struct kvm_lapic *apic)
1643 {
1644         struct kvm_timer *ktimer = &apic->lapic_timer;
1645         int r;
1646
1647         WARN_ON(preemptible());
1648         if (!kvm_x86_ops->set_hv_timer)
1649                 return false;
1650
1651         if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1652                 return false;
1653
1654         if (!ktimer->tscdeadline)
1655                 return false;
1656
1657         r = kvm_x86_ops->set_hv_timer(apic->vcpu, ktimer->tscdeadline);
1658         if (r < 0)
1659                 return false;
1660
1661         ktimer->hv_timer_in_use = true;
1662         hrtimer_cancel(&ktimer->timer);
1663
1664         /*
1665          * Also recheck ktimer->pending, in case the sw timer triggered in
1666          * the window.  For periodic timer, leave the hv timer running for
1667          * simplicity, and the deadline will be recomputed on the next vmexit.
1668          */
1669         if (!apic_lvtt_period(apic) && (r || atomic_read(&ktimer->pending))) {
1670                 if (r)
1671                         apic_timer_expired(apic);
1672                 return false;
1673         }
1674
1675         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, true);
1676         return true;
1677 }
1678
1679 static void start_sw_timer(struct kvm_lapic *apic)
1680 {
1681         struct kvm_timer *ktimer = &apic->lapic_timer;
1682
1683         WARN_ON(preemptible());
1684         if (apic->lapic_timer.hv_timer_in_use)
1685                 cancel_hv_timer(apic);
1686         if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1687                 return;
1688
1689         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1690                 start_sw_period(apic);
1691         else if (apic_lvtt_tscdeadline(apic))
1692                 start_sw_tscdeadline(apic);
1693         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1694 }
1695
1696 static void restart_apic_timer(struct kvm_lapic *apic)
1697 {
1698         preempt_disable();
1699         if (!start_hv_timer(apic))
1700                 start_sw_timer(apic);
1701         preempt_enable();
1702 }
1703
1704 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1705 {
1706         struct kvm_lapic *apic = vcpu->arch.apic;
1707
1708         preempt_disable();
1709         /* If the preempt notifier has already run, it also called apic_timer_expired */
1710         if (!apic->lapic_timer.hv_timer_in_use)
1711                 goto out;
1712         WARN_ON(swait_active(&vcpu->wq));
1713         cancel_hv_timer(apic);
1714         apic_timer_expired(apic);
1715
1716         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1717                 advance_periodic_target_expiration(apic);
1718                 restart_apic_timer(apic);
1719         }
1720 out:
1721         preempt_enable();
1722 }
1723 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1724
1725 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1726 {
1727         restart_apic_timer(vcpu->arch.apic);
1728 }
1729 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1730
1731 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1732 {
1733         struct kvm_lapic *apic = vcpu->arch.apic;
1734
1735         preempt_disable();
1736         /* Possibly the TSC deadline timer is not enabled yet */
1737         if (apic->lapic_timer.hv_timer_in_use)
1738                 start_sw_timer(apic);
1739         preempt_enable();
1740 }
1741 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1742
1743 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1744 {
1745         struct kvm_lapic *apic = vcpu->arch.apic;
1746
1747         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1748         restart_apic_timer(apic);
1749 }
1750
1751 static void start_apic_timer(struct kvm_lapic *apic)
1752 {
1753         atomic_set(&apic->lapic_timer.pending, 0);
1754
1755         if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1756             && !set_target_expiration(apic))
1757                 return;
1758
1759         restart_apic_timer(apic);
1760 }
1761
1762 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1763 {
1764         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1765
1766         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1767                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1768                 if (lvt0_in_nmi_mode) {
1769                         apic_debug("Receive NMI setting on APIC_LVT0 "
1770                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1771                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1772                 } else
1773                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1774         }
1775 }
1776
1777 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1778 {
1779         int ret = 0;
1780
1781         trace_kvm_apic_write(reg, val);
1782
1783         switch (reg) {
1784         case APIC_ID:           /* Local APIC ID */
1785                 if (!apic_x2apic_mode(apic))
1786                         kvm_apic_set_xapic_id(apic, val >> 24);
1787                 else
1788                         ret = 1;
1789                 break;
1790
1791         case APIC_TASKPRI:
1792                 report_tpr_access(apic, true);
1793                 apic_set_tpr(apic, val & 0xff);
1794                 break;
1795
1796         case APIC_EOI:
1797                 apic_set_eoi(apic);
1798                 break;
1799
1800         case APIC_LDR:
1801                 if (!apic_x2apic_mode(apic))
1802                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1803                 else
1804                         ret = 1;
1805                 break;
1806
1807         case APIC_DFR:
1808                 if (!apic_x2apic_mode(apic)) {
1809                         kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1810                         recalculate_apic_map(apic->vcpu->kvm);
1811                 } else
1812                         ret = 1;
1813                 break;
1814
1815         case APIC_SPIV: {
1816                 u32 mask = 0x3ff;
1817                 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1818                         mask |= APIC_SPIV_DIRECTED_EOI;
1819                 apic_set_spiv(apic, val & mask);
1820                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1821                         int i;
1822                         u32 lvt_val;
1823
1824                         for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1825                                 lvt_val = kvm_lapic_get_reg(apic,
1826                                                        APIC_LVTT + 0x10 * i);
1827                                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1828                                              lvt_val | APIC_LVT_MASKED);
1829                         }
1830                         apic_update_lvtt(apic);
1831                         atomic_set(&apic->lapic_timer.pending, 0);
1832
1833                 }
1834                 break;
1835         }
1836         case APIC_ICR:
1837                 /* No delay here, so we always clear the pending bit */
1838                 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1839                 apic_send_ipi(apic);
1840                 break;
1841
1842         case APIC_ICR2:
1843                 if (!apic_x2apic_mode(apic))
1844                         val &= 0xff000000;
1845                 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1846                 break;
1847
1848         case APIC_LVT0:
1849                 apic_manage_nmi_watchdog(apic, val);
1850         case APIC_LVTTHMR:
1851         case APIC_LVTPC:
1852         case APIC_LVT1:
1853         case APIC_LVTERR:
1854                 /* TODO: Check vector */
1855                 if (!kvm_apic_sw_enabled(apic))
1856                         val |= APIC_LVT_MASKED;
1857
1858                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1859                 kvm_lapic_set_reg(apic, reg, val);
1860
1861                 break;
1862
1863         case APIC_LVTT:
1864                 if (!kvm_apic_sw_enabled(apic))
1865                         val |= APIC_LVT_MASKED;
1866                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1867                 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1868                 apic_update_lvtt(apic);
1869                 break;
1870
1871         case APIC_TMICT:
1872                 if (apic_lvtt_tscdeadline(apic))
1873                         break;
1874
1875                 hrtimer_cancel(&apic->lapic_timer.timer);
1876                 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1877                 start_apic_timer(apic);
1878                 break;
1879
1880         case APIC_TDCR: {
1881                 uint32_t old_divisor = apic->divide_count;
1882
1883                 if (val & 4)
1884                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1885                 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1886                 update_divide_count(apic);
1887                 if (apic->divide_count != old_divisor &&
1888                                 apic->lapic_timer.period) {
1889                         hrtimer_cancel(&apic->lapic_timer.timer);
1890                         update_target_expiration(apic, old_divisor);
1891                         restart_apic_timer(apic);
1892                 }
1893                 break;
1894         }
1895         case APIC_ESR:
1896                 if (apic_x2apic_mode(apic) && val != 0) {
1897                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1898                         ret = 1;
1899                 }
1900                 break;
1901
1902         case APIC_SELF_IPI:
1903                 if (apic_x2apic_mode(apic)) {
1904                         kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1905                 } else
1906                         ret = 1;
1907                 break;
1908         default:
1909                 ret = 1;
1910                 break;
1911         }
1912         if (ret)
1913                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1914         return ret;
1915 }
1916 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1917
1918 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1919                             gpa_t address, int len, const void *data)
1920 {
1921         struct kvm_lapic *apic = to_lapic(this);
1922         unsigned int offset = address - apic->base_address;
1923         u32 val;
1924
1925         if (!apic_mmio_in_range(apic, address))
1926                 return -EOPNOTSUPP;
1927
1928         if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1929                 if (!kvm_check_has_quirk(vcpu->kvm,
1930                                          KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1931                         return -EOPNOTSUPP;
1932
1933                 return 0;
1934         }
1935
1936         /*
1937          * APIC register must be aligned on 128-bits boundary.
1938          * 32/64/128 bits registers must be accessed thru 32 bits.
1939          * Refer SDM 8.4.1
1940          */
1941         if (len != 4 || (offset & 0xf)) {
1942                 /* Don't shout loud, $infamous_os would cause only noise. */
1943                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1944                 return 0;
1945         }
1946
1947         val = *(u32*)data;
1948
1949         /* too common printing */
1950         if (offset != APIC_EOI)
1951                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1952                            "0x%x\n", __func__, offset, len, val);
1953
1954         kvm_lapic_reg_write(apic, offset & 0xff0, val);
1955
1956         return 0;
1957 }
1958
1959 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1960 {
1961         kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1962 }
1963 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1964
1965 /* emulate APIC access in a trap manner */
1966 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1967 {
1968         u32 val = 0;
1969
1970         /* hw has done the conditional check and inst decode */
1971         offset &= 0xff0;
1972
1973         kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
1974
1975         /* TODO: optimize to just emulate side effect w/o one more write */
1976         kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
1977 }
1978 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1979
1980 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1981 {
1982         struct kvm_lapic *apic = vcpu->arch.apic;
1983
1984         if (!vcpu->arch.apic)
1985                 return;
1986
1987         hrtimer_cancel(&apic->lapic_timer.timer);
1988
1989         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1990                 static_key_slow_dec_deferred(&apic_hw_disabled);
1991
1992         if (!apic->sw_enabled)
1993                 static_key_slow_dec_deferred(&apic_sw_disabled);
1994
1995         if (apic->regs)
1996                 free_page((unsigned long)apic->regs);
1997
1998         kfree(apic);
1999 }
2000
2001 /*
2002  *----------------------------------------------------------------------
2003  * LAPIC interface
2004  *----------------------------------------------------------------------
2005  */
2006 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2007 {
2008         struct kvm_lapic *apic = vcpu->arch.apic;
2009
2010         if (!lapic_in_kernel(vcpu) ||
2011                 !apic_lvtt_tscdeadline(apic))
2012                 return 0;
2013
2014         return apic->lapic_timer.tscdeadline;
2015 }
2016
2017 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2018 {
2019         struct kvm_lapic *apic = vcpu->arch.apic;
2020
2021         if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
2022                         apic_lvtt_period(apic))
2023                 return;
2024
2025         hrtimer_cancel(&apic->lapic_timer.timer);
2026         apic->lapic_timer.tscdeadline = data;
2027         start_apic_timer(apic);
2028 }
2029
2030 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2031 {
2032         struct kvm_lapic *apic = vcpu->arch.apic;
2033
2034         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
2035                      | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
2036 }
2037
2038 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2039 {
2040         u64 tpr;
2041
2042         tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2043
2044         return (tpr & 0xf0) >> 4;
2045 }
2046
2047 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2048 {
2049         u64 old_value = vcpu->arch.apic_base;
2050         struct kvm_lapic *apic = vcpu->arch.apic;
2051
2052         if (!apic)
2053                 value |= MSR_IA32_APICBASE_BSP;
2054
2055         vcpu->arch.apic_base = value;
2056
2057         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2058                 kvm_update_cpuid(vcpu);
2059
2060         if (!apic)
2061                 return;
2062
2063         /* update jump label if enable bit changes */
2064         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2065                 if (value & MSR_IA32_APICBASE_ENABLE) {
2066                         kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2067                         static_key_slow_dec_deferred(&apic_hw_disabled);
2068                 } else {
2069                         static_key_slow_inc(&apic_hw_disabled.key);
2070                         recalculate_apic_map(vcpu->kvm);
2071                 }
2072         }
2073
2074         if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2075                 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2076
2077         if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2078                 kvm_x86_ops->set_virtual_apic_mode(vcpu);
2079
2080         apic->base_address = apic->vcpu->arch.apic_base &
2081                              MSR_IA32_APICBASE_BASE;
2082
2083         if ((value & MSR_IA32_APICBASE_ENABLE) &&
2084              apic->base_address != APIC_DEFAULT_PHYS_BASE)
2085                 pr_warn_once("APIC base relocation is unsupported by KVM");
2086
2087         /* with FSB delivery interrupt, we can restart APIC functionality */
2088         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
2089                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
2090
2091 }
2092
2093 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2094 {
2095         struct kvm_lapic *apic = vcpu->arch.apic;
2096         int i;
2097
2098         if (!apic)
2099                 return;
2100
2101         apic_debug("%s\n", __func__);
2102
2103         /* Stop the timer in case it's a reset to an active apic */
2104         hrtimer_cancel(&apic->lapic_timer.timer);
2105
2106         if (!init_event) {
2107                 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2108                                          MSR_IA32_APICBASE_ENABLE);
2109                 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2110         }
2111         kvm_apic_set_version(apic->vcpu);
2112
2113         for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2114                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2115         apic_update_lvtt(apic);
2116         if (kvm_vcpu_is_reset_bsp(vcpu) &&
2117             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2118                 kvm_lapic_set_reg(apic, APIC_LVT0,
2119                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2120         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2121
2122         kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
2123         apic_set_spiv(apic, 0xff);
2124         kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2125         if (!apic_x2apic_mode(apic))
2126                 kvm_apic_set_ldr(apic, 0);
2127         kvm_lapic_set_reg(apic, APIC_ESR, 0);
2128         kvm_lapic_set_reg(apic, APIC_ICR, 0);
2129         kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2130         kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2131         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2132         for (i = 0; i < 8; i++) {
2133                 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2134                 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2135                 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2136         }
2137         apic->irr_pending = vcpu->arch.apicv_active;
2138         apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
2139         apic->highest_isr_cache = -1;
2140         update_divide_count(apic);
2141         atomic_set(&apic->lapic_timer.pending, 0);
2142         if (kvm_vcpu_is_bsp(vcpu))
2143                 kvm_lapic_set_base(vcpu,
2144                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2145         vcpu->arch.pv_eoi.msr_val = 0;
2146         apic_update_ppr(apic);
2147         if (vcpu->arch.apicv_active) {
2148                 kvm_x86_ops->apicv_post_state_restore(vcpu);
2149                 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2150                 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2151         }
2152
2153         vcpu->arch.apic_arb_prio = 0;
2154         vcpu->arch.apic_attention = 0;
2155
2156         apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
2157                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
2158                    vcpu, kvm_lapic_get_reg(apic, APIC_ID),
2159                    vcpu->arch.apic_base, apic->base_address);
2160 }
2161
2162 /*
2163  *----------------------------------------------------------------------
2164  * timer interface
2165  *----------------------------------------------------------------------
2166  */
2167
2168 static bool lapic_is_periodic(struct kvm_lapic *apic)
2169 {
2170         return apic_lvtt_period(apic);
2171 }
2172
2173 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2174 {
2175         struct kvm_lapic *apic = vcpu->arch.apic;
2176
2177         if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2178                 return atomic_read(&apic->lapic_timer.pending);
2179
2180         return 0;
2181 }
2182
2183 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2184 {
2185         u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2186         int vector, mode, trig_mode;
2187
2188         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2189                 vector = reg & APIC_VECTOR_MASK;
2190                 mode = reg & APIC_MODE_MASK;
2191                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2192                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2193                                         NULL);
2194         }
2195         return 0;
2196 }
2197
2198 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2199 {
2200         struct kvm_lapic *apic = vcpu->arch.apic;
2201
2202         if (apic)
2203                 kvm_apic_local_deliver(apic, APIC_LVT0);
2204 }
2205
2206 static const struct kvm_io_device_ops apic_mmio_ops = {
2207         .read     = apic_mmio_read,
2208         .write    = apic_mmio_write,
2209 };
2210
2211 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2212 {
2213         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2214         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2215
2216         apic_timer_expired(apic);
2217
2218         if (lapic_is_periodic(apic)) {
2219                 advance_periodic_target_expiration(apic);
2220                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2221                 return HRTIMER_RESTART;
2222         } else
2223                 return HRTIMER_NORESTART;
2224 }
2225
2226 int kvm_create_lapic(struct kvm_vcpu *vcpu)
2227 {
2228         struct kvm_lapic *apic;
2229
2230         ASSERT(vcpu != NULL);
2231         apic_debug("apic_init %d\n", vcpu->vcpu_id);
2232
2233         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
2234         if (!apic)
2235                 goto nomem;
2236
2237         vcpu->arch.apic = apic;
2238
2239         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
2240         if (!apic->regs) {
2241                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2242                        vcpu->vcpu_id);
2243                 goto nomem_free_apic;
2244         }
2245         apic->vcpu = vcpu;
2246
2247         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2248                      HRTIMER_MODE_ABS_PINNED);
2249         apic->lapic_timer.timer.function = apic_timer_fn;
2250
2251         /*
2252          * APIC is created enabled. This will prevent kvm_lapic_set_base from
2253          * thinking that APIC satet has changed.
2254          */
2255         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2256         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2257         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2258
2259         return 0;
2260 nomem_free_apic:
2261         kfree(apic);
2262 nomem:
2263         return -ENOMEM;
2264 }
2265
2266 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2267 {
2268         struct kvm_lapic *apic = vcpu->arch.apic;
2269         u32 ppr;
2270
2271         if (!apic_enabled(apic))
2272                 return -1;
2273
2274         __apic_update_ppr(apic, &ppr);
2275         return apic_has_interrupt_for_ppr(apic, ppr);
2276 }
2277
2278 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2279 {
2280         u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2281         int r = 0;
2282
2283         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2284                 r = 1;
2285         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2286             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2287                 r = 1;
2288         return r;
2289 }
2290
2291 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2292 {
2293         struct kvm_lapic *apic = vcpu->arch.apic;
2294
2295         if (atomic_read(&apic->lapic_timer.pending) > 0) {
2296                 kvm_apic_local_deliver(apic, APIC_LVTT);
2297                 if (apic_lvtt_tscdeadline(apic))
2298                         apic->lapic_timer.tscdeadline = 0;
2299                 if (apic_lvtt_oneshot(apic)) {
2300                         apic->lapic_timer.tscdeadline = 0;
2301                         apic->lapic_timer.target_expiration = 0;
2302                 }
2303                 atomic_set(&apic->lapic_timer.pending, 0);
2304         }
2305 }
2306
2307 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2308 {
2309         int vector = kvm_apic_has_interrupt(vcpu);
2310         struct kvm_lapic *apic = vcpu->arch.apic;
2311         u32 ppr;
2312
2313         if (vector == -1)
2314                 return -1;
2315
2316         /*
2317          * We get here even with APIC virtualization enabled, if doing
2318          * nested virtualization and L1 runs with the "acknowledge interrupt
2319          * on exit" mode.  Then we cannot inject the interrupt via RVI,
2320          * because the process would deliver it through the IDT.
2321          */
2322
2323         apic_clear_irr(vector, apic);
2324         if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2325                 /*
2326                  * For auto-EOI interrupts, there might be another pending
2327                  * interrupt above PPR, so check whether to raise another
2328                  * KVM_REQ_EVENT.
2329                  */
2330                 apic_update_ppr(apic);
2331         } else {
2332                 /*
2333                  * For normal interrupts, PPR has been raised and there cannot
2334                  * be a higher-priority pending interrupt---except if there was
2335                  * a concurrent interrupt injection, but that would have
2336                  * triggered KVM_REQ_EVENT already.
2337                  */
2338                 apic_set_isr(vector, apic);
2339                 __apic_update_ppr(apic, &ppr);
2340         }
2341
2342         return vector;
2343 }
2344
2345 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2346                 struct kvm_lapic_state *s, bool set)
2347 {
2348         if (apic_x2apic_mode(vcpu->arch.apic)) {
2349                 u32 *id = (u32 *)(s->regs + APIC_ID);
2350                 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2351
2352                 if (vcpu->kvm->arch.x2apic_format) {
2353                         if (*id != vcpu->vcpu_id)
2354                                 return -EINVAL;
2355                 } else {
2356                         if (set)
2357                                 *id >>= 24;
2358                         else
2359                                 *id <<= 24;
2360                 }
2361
2362                 /* In x2APIC mode, the LDR is fixed and based on the id */
2363                 if (set)
2364                         *ldr = kvm_apic_calc_x2apic_ldr(*id);
2365         }
2366
2367         return 0;
2368 }
2369
2370 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2371 {
2372         memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2373         return kvm_apic_state_fixup(vcpu, s, false);
2374 }
2375
2376 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2377 {
2378         struct kvm_lapic *apic = vcpu->arch.apic;
2379         int r;
2380
2381
2382         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2383         /* set SPIV separately to get count of SW disabled APICs right */
2384         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2385
2386         r = kvm_apic_state_fixup(vcpu, s, true);
2387         if (r)
2388                 return r;
2389         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2390
2391         recalculate_apic_map(vcpu->kvm);
2392         kvm_apic_set_version(vcpu);
2393
2394         apic_update_ppr(apic);
2395         hrtimer_cancel(&apic->lapic_timer.timer);
2396         apic_update_lvtt(apic);
2397         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2398         update_divide_count(apic);
2399         start_apic_timer(apic);
2400         apic->irr_pending = true;
2401         apic->isr_count = vcpu->arch.apicv_active ?
2402                                 1 : count_vectors(apic->regs + APIC_ISR);
2403         apic->highest_isr_cache = -1;
2404         if (vcpu->arch.apicv_active) {
2405                 kvm_x86_ops->apicv_post_state_restore(vcpu);
2406                 kvm_x86_ops->hwapic_irr_update(vcpu,
2407                                 apic_find_highest_irr(apic));
2408                 kvm_x86_ops->hwapic_isr_update(vcpu,
2409                                 apic_find_highest_isr(apic));
2410         }
2411         kvm_make_request(KVM_REQ_EVENT, vcpu);
2412         if (ioapic_in_kernel(vcpu->kvm))
2413                 kvm_rtc_eoi_tracking_restore_one(vcpu);
2414
2415         vcpu->arch.apic_arb_prio = 0;
2416
2417         return 0;
2418 }
2419
2420 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2421 {
2422         struct hrtimer *timer;
2423
2424         if (!lapic_in_kernel(vcpu))
2425                 return;
2426
2427         timer = &vcpu->arch.apic->lapic_timer.timer;
2428         if (hrtimer_cancel(timer))
2429                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2430 }
2431
2432 /*
2433  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2434  *
2435  * Detect whether guest triggered PV EOI since the
2436  * last entry. If yes, set EOI on guests's behalf.
2437  * Clear PV EOI in guest memory in any case.
2438  */
2439 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2440                                         struct kvm_lapic *apic)
2441 {
2442         bool pending;
2443         int vector;
2444         /*
2445          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2446          * and KVM_PV_EOI_ENABLED in guest memory as follows:
2447          *
2448          * KVM_APIC_PV_EOI_PENDING is unset:
2449          *      -> host disabled PV EOI.
2450          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2451          *      -> host enabled PV EOI, guest did not execute EOI yet.
2452          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2453          *      -> host enabled PV EOI, guest executed EOI.
2454          */
2455         BUG_ON(!pv_eoi_enabled(vcpu));
2456         pending = pv_eoi_get_pending(vcpu);
2457         /*
2458          * Clear pending bit in any case: it will be set again on vmentry.
2459          * While this might not be ideal from performance point of view,
2460          * this makes sure pv eoi is only enabled when we know it's safe.
2461          */
2462         pv_eoi_clr_pending(vcpu);
2463         if (pending)
2464                 return;
2465         vector = apic_set_eoi(apic);
2466         trace_kvm_pv_eoi(apic, vector);
2467 }
2468
2469 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2470 {
2471         u32 data;
2472
2473         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2474                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2475
2476         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2477                 return;
2478
2479         if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2480                                   sizeof(u32)))
2481                 return;
2482
2483         apic_set_tpr(vcpu->arch.apic, data & 0xff);
2484 }
2485
2486 /*
2487  * apic_sync_pv_eoi_to_guest - called before vmentry
2488  *
2489  * Detect whether it's safe to enable PV EOI and
2490  * if yes do so.
2491  */
2492 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2493                                         struct kvm_lapic *apic)
2494 {
2495         if (!pv_eoi_enabled(vcpu) ||
2496             /* IRR set or many bits in ISR: could be nested. */
2497             apic->irr_pending ||
2498             /* Cache not set: could be safe but we don't bother. */
2499             apic->highest_isr_cache == -1 ||
2500             /* Need EOI to update ioapic. */
2501             kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2502                 /*
2503                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2504                  * so we need not do anything here.
2505                  */
2506                 return;
2507         }
2508
2509         pv_eoi_set_pending(apic->vcpu);
2510 }
2511
2512 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2513 {
2514         u32 data, tpr;
2515         int max_irr, max_isr;
2516         struct kvm_lapic *apic = vcpu->arch.apic;
2517
2518         apic_sync_pv_eoi_to_guest(vcpu, apic);
2519
2520         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2521                 return;
2522
2523         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2524         max_irr = apic_find_highest_irr(apic);
2525         if (max_irr < 0)
2526                 max_irr = 0;
2527         max_isr = apic_find_highest_isr(apic);
2528         if (max_isr < 0)
2529                 max_isr = 0;
2530         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2531
2532         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2533                                 sizeof(u32));
2534 }
2535
2536 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2537 {
2538         if (vapic_addr) {
2539                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2540                                         &vcpu->arch.apic->vapic_cache,
2541                                         vapic_addr, sizeof(u32)))
2542                         return -EINVAL;
2543                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2544         } else {
2545                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2546         }
2547
2548         vcpu->arch.apic->vapic_addr = vapic_addr;
2549         return 0;
2550 }
2551
2552 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2553 {
2554         struct kvm_lapic *apic = vcpu->arch.apic;
2555         u32 reg = (msr - APIC_BASE_MSR) << 4;
2556
2557         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2558                 return 1;
2559
2560         if (reg == APIC_ICR2)
2561                 return 1;
2562
2563         /* if this is ICR write vector before command */
2564         if (reg == APIC_ICR)
2565                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2566         return kvm_lapic_reg_write(apic, reg, (u32)data);
2567 }
2568
2569 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2570 {
2571         struct kvm_lapic *apic = vcpu->arch.apic;
2572         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2573
2574         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2575                 return 1;
2576
2577         if (reg == APIC_DFR || reg == APIC_ICR2) {
2578                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2579                            reg);
2580                 return 1;
2581         }
2582
2583         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2584                 return 1;
2585         if (reg == APIC_ICR)
2586                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2587
2588         *data = (((u64)high) << 32) | low;
2589
2590         return 0;
2591 }
2592
2593 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2594 {
2595         struct kvm_lapic *apic = vcpu->arch.apic;
2596
2597         if (!lapic_in_kernel(vcpu))
2598                 return 1;
2599
2600         /* if this is ICR write vector before command */
2601         if (reg == APIC_ICR)
2602                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2603         return kvm_lapic_reg_write(apic, reg, (u32)data);
2604 }
2605
2606 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2607 {
2608         struct kvm_lapic *apic = vcpu->arch.apic;
2609         u32 low, high = 0;
2610
2611         if (!lapic_in_kernel(vcpu))
2612                 return 1;
2613
2614         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2615                 return 1;
2616         if (reg == APIC_ICR)
2617                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2618
2619         *data = (((u64)high) << 32) | low;
2620
2621         return 0;
2622 }
2623
2624 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2625 {
2626         u64 addr = data & ~KVM_MSR_ENABLED;
2627         if (!IS_ALIGNED(addr, 4))
2628                 return 1;
2629
2630         vcpu->arch.pv_eoi.msr_val = data;
2631         if (!pv_eoi_enabled(vcpu))
2632                 return 0;
2633         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2634                                          addr, sizeof(u8));
2635 }
2636
2637 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2638 {
2639         struct kvm_lapic *apic = vcpu->arch.apic;
2640         u8 sipi_vector;
2641         unsigned long pe;
2642
2643         if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2644                 return;
2645
2646         /*
2647          * INITs are latched while in SMM.  Because an SMM CPU cannot
2648          * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2649          * and delay processing of INIT until the next RSM.
2650          */
2651         if (is_smm(vcpu)) {
2652                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2653                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2654                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2655                 return;
2656         }
2657
2658         pe = xchg(&apic->pending_events, 0);
2659         if (test_bit(KVM_APIC_INIT, &pe)) {
2660                 kvm_vcpu_reset(vcpu, true);
2661                 if (kvm_vcpu_is_bsp(apic->vcpu))
2662                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2663                 else
2664                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2665         }
2666         if (test_bit(KVM_APIC_SIPI, &pe) &&
2667             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2668                 /* evaluate pending_events before reading the vector */
2669                 smp_rmb();
2670                 sipi_vector = apic->sipi_vector;
2671                 apic_debug("vcpu %d received sipi with vector # %x\n",
2672                          vcpu->vcpu_id, sipi_vector);
2673                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2674                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2675         }
2676 }
2677
2678 void kvm_lapic_init(void)
2679 {
2680         /* do not patch jump label more than once per second */
2681         jump_label_rate_limit(&apic_hw_disabled, HZ);
2682         jump_label_rate_limit(&apic_sw_disabled, HZ);
2683 }
2684
2685 void kvm_lapic_exit(void)
2686 {
2687         static_key_deferred_flush(&apic_hw_disabled);
2688         static_key_deferred_flush(&apic_sw_disabled);
2689 }