arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/export.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44 #include "hyperv.h"
  45
  46 #ifndef CONFIG_X86_64
  47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  48 #else
  49 #define mod_64(x, y) ((x) % (y))
  50 #endif
  51
  52 #define PRId64 "d"
  53 #define PRIx64 "llx"
  54 #define PRIu64 "u"
  55 #define PRIo64 "o"
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...) do {} while (0)
  59
  60 /* 14 is the version for Xeon and Pentium 8.4.8*/
  61 #define APIC_VERSION                    (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
  62 #define LAPIC_MMIO_LENGTH               (1 << 12)
  63 /* followed define is not in apicdef.h */
  64 #define APIC_SHORT_MASK                 0xc0000
  65 #define APIC_DEST_NOSHORT               0x0
  66 #define APIC_DEST_MASK                  0x800
  67 #define MAX_APIC_VECTOR                 256
  68 #define APIC_VECTORS_PER_REG            32
  69
  70 #define APIC_BROADCAST                  0xFF
  71 #define X2APIC_BROADCAST                0xFFFFFFFFul
  72
  73 #define LAPIC_TIMER_ADVANCE_ADJUST_DONE 100
  74 /* step-by-step approximation to mitigate fluctuation */
  75 #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
  76
  77 static inline int apic_test_vector(int vec, void *bitmap)
  78 {
  79         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  80 }
  81
  82 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  83 {
  84         struct kvm_lapic *apic = vcpu->arch.apic;
  85
  86         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  87                 apic_test_vector(vector, apic->regs + APIC_IRR);
  88 }
  89
  90 static inline void apic_clear_vector(int vec, void *bitmap)
  91 {
  92         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  93 }
  94
  95 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
  96 {
  97         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  98 }
  99
 100 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 101 {
 102         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 103 }
 104
 105 struct static_key_deferred apic_hw_disabled __read_mostly;
 106 struct static_key_deferred apic_sw_disabled __read_mostly;
 107
 108 static inline int apic_enabled(struct kvm_lapic *apic)
 109 {
 110         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 111 }
 112
 113 #define LVT_MASK        \
 114         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 115
 116 #define LINT_MASK       \
 117         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 118          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 119
 120 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
 121 {
 122         return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
 123 }
 124
 125 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
 126 {
 127         return apic->vcpu->vcpu_id;
 128 }
 129
 130 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
 131                 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
 132         switch (map->mode) {
 133         case KVM_APIC_MODE_X2APIC: {
 134                 u32 offset = (dest_id >> 16) * 16;
 135                 u32 max_apic_id = map->max_apic_id;
 136
 137                 if (offset <= max_apic_id) {
 138                         u8 cluster_size = min(max_apic_id - offset + 1, 16U);
 139
 140                         offset = array_index_nospec(offset, map->max_apic_id + 1);
 141                         *cluster = &map->phys_map[offset];
 142                         *mask = dest_id & (0xffff >> (16 - cluster_size));
 143                 } else {
 144                         *mask = 0;
 145                 }
 146
 147                 return true;
 148                 }
 149         case KVM_APIC_MODE_XAPIC_FLAT:
 150                 *cluster = map->xapic_flat_map;
 151                 *mask = dest_id & 0xff;
 152                 return true;
 153         case KVM_APIC_MODE_XAPIC_CLUSTER:
 154                 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
 155                 *mask = dest_id & 0xf;
 156                 return true;
 157         default:
 158                 /* Not optimized. */
 159                 return false;
 160         }
 161 }
 162
 163 static void kvm_apic_map_free(struct rcu_head *rcu)
 164 {
 165         struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
 166
 167         kvfree(map);
 168 }
 169
 170 static void recalculate_apic_map(struct kvm *kvm)
 171 {
 172         struct kvm_apic_map *new, *old = NULL;
 173         struct kvm_vcpu *vcpu;
 174         int i;
 175         u32 max_id = 255; /* enough space for any xAPIC ID */
 176
 177         mutex_lock(&kvm->arch.apic_map_lock);
 178
 179         kvm_for_each_vcpu(i, vcpu, kvm)
 180                 if (kvm_apic_present(vcpu))
 181                         max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
 182
 183         new = kvzalloc(sizeof(struct kvm_apic_map) +
 184                            sizeof(struct kvm_lapic *) * ((u64)max_id + 1),
 185                            GFP_KERNEL_ACCOUNT);
 186
 187         if (!new)
 188                 goto out;
 189
 190         new->max_apic_id = max_id;
 191
 192         kvm_for_each_vcpu(i, vcpu, kvm) {
 193                 struct kvm_lapic *apic = vcpu->arch.apic;
 194                 struct kvm_lapic **cluster;
 195                 u16 mask;
 196                 u32 ldr;
 197                 u8 xapic_id;
 198                 u32 x2apic_id;
 199
 200                 if (!kvm_apic_present(vcpu))
 201                         continue;
 202
 203                 xapic_id = kvm_xapic_id(apic);
 204                 x2apic_id = kvm_x2apic_id(apic);
 205
 206                 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
 207                 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
 208                                 x2apic_id <= new->max_apic_id)
 209                         new->phys_map[x2apic_id] = apic;
 210                 /*
 211                  * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
 212                  * prevent them from masking VCPUs with APIC ID <= 0xff.
 213                  */
 214                 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
 215                         new->phys_map[xapic_id] = apic;
 216
 217                 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
 218
 219                 if (apic_x2apic_mode(apic)) {
 220                         new->mode |= KVM_APIC_MODE_X2APIC;
 221                 } else if (ldr) {
 222                         ldr = GET_APIC_LOGICAL_ID(ldr);
 223                         if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
 224                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
 225                         else
 226                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
 227                 }
 228
 229                 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
 230                         continue;
 231
 232                 if (mask)
 233                         cluster[ffs(mask) - 1] = apic;
 234         }
 235 out:
 236         old = rcu_dereference_protected(kvm->arch.apic_map,
 237                         lockdep_is_held(&kvm->arch.apic_map_lock));
 238         rcu_assign_pointer(kvm->arch.apic_map, new);
 239         mutex_unlock(&kvm->arch.apic_map_lock);
 240
 241         if (old)
 242                 call_rcu(&old->rcu, kvm_apic_map_free);
 243
 244         kvm_make_scan_ioapic_request(kvm);
 245 }
 246
 247 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 248 {
 249         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 250
 251         kvm_lapic_set_reg(apic, APIC_SPIV, val);
 252
 253         if (enabled != apic->sw_enabled) {
 254                 apic->sw_enabled = enabled;
 255                 if (enabled)
 256                         static_key_slow_dec_deferred(&apic_sw_disabled);
 257                 else
 258                         static_key_slow_inc(&apic_sw_disabled.key);
 259         }
 260 }
 261
 262 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
 263 {
 264         kvm_lapic_set_reg(apic, APIC_ID, id << 24);
 265         recalculate_apic_map(apic->vcpu->kvm);
 266 }
 267
 268 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 269 {
 270         kvm_lapic_set_reg(apic, APIC_LDR, id);
 271         recalculate_apic_map(apic->vcpu->kvm);
 272 }
 273
 274 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
 275 {
 276         return ((id >> 4) << 16) | (1 << (id & 0xf));
 277 }
 278
 279 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
 280 {
 281         u32 ldr = kvm_apic_calc_x2apic_ldr(id);
 282
 283         WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
 284
 285         kvm_lapic_set_reg(apic, APIC_ID, id);
 286         kvm_lapic_set_reg(apic, APIC_LDR, ldr);
 287         recalculate_apic_map(apic->vcpu->kvm);
 288 }
 289
 290 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 291 {
 292         return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 293 }
 294
 295 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 296 {
 297         return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 298 }
 299
 300 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 301 {
 302         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 303 }
 304
 305 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 306 {
 307         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 308 }
 309
 310 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 311 {
 312         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 313 }
 314
 315 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 316 {
 317         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 318 }
 319
 320 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 321 {
 322         struct kvm_lapic *apic = vcpu->arch.apic;
 323         struct kvm_cpuid_entry2 *feat;
 324         u32 v = APIC_VERSION;
 325
 326         if (!lapic_in_kernel(vcpu))
 327                 return;
 328
 329         /*
 330          * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
 331          * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
 332          * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
 333          * version first and level-triggered interrupts never get EOIed in
 334          * IOAPIC.
 335          */
 336         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 337         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
 338             !ioapic_in_kernel(vcpu->kvm))
 339                 v |= APIC_LVR_DIRECTED_EOI;
 340         kvm_lapic_set_reg(apic, APIC_LVR, v);
 341 }
 342
 343 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
 344         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 345         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 346         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 347         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 348         LVT_MASK                /* LVTERR */
 349 };
 350
 351 static int find_highest_vector(void *bitmap)
 352 {
 353         int vec;
 354         u32 *reg;
 355
 356         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 357              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 358                 reg = bitmap + REG_POS(vec);
 359                 if (*reg)
 360                         return __fls(*reg) + vec;
 361         }
 362
 363         return -1;
 364 }
 365
 366 static u8 count_vectors(void *bitmap)
 367 {
 368         int vec;
 369         u32 *reg;
 370         u8 count = 0;
 371
 372         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 373                 reg = bitmap + REG_POS(vec);
 374                 count += hweight32(*reg);
 375         }
 376
 377         return count;
 378 }
 379
 380 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
 381 {
 382         u32 i, vec;
 383         u32 pir_val, irr_val, prev_irr_val;
 384         int max_updated_irr;
 385
 386         max_updated_irr = -1;
 387         *max_irr = -1;
 388
 389         for (i = vec = 0; i <= 7; i++, vec += 32) {
 390                 pir_val = READ_ONCE(pir[i]);
 391                 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
 392                 if (pir_val) {
 393                         prev_irr_val = irr_val;
 394                         irr_val |= xchg(&pir[i], 0);
 395                         *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
 396                         if (prev_irr_val != irr_val) {
 397                                 max_updated_irr =
 398                                         __fls(irr_val ^ prev_irr_val) + vec;
 399                         }
 400                 }
 401                 if (irr_val)
 402                         *max_irr = __fls(irr_val) + vec;
 403         }
 404
 405         return ((max_updated_irr != -1) &&
 406                 (max_updated_irr == *max_irr));
 407 }
 408 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 409
 410 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
 411 {
 412         struct kvm_lapic *apic = vcpu->arch.apic;
 413
 414         return __kvm_apic_update_irr(pir, apic->regs, max_irr);
 415 }
 416 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 417
 418 static inline int apic_search_irr(struct kvm_lapic *apic)
 419 {
 420         return find_highest_vector(apic->regs + APIC_IRR);
 421 }
 422
 423 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 424 {
 425         int result;
 426
 427         /*
 428          * Note that irr_pending is just a hint. It will be always
 429          * true with virtual interrupt delivery enabled.
 430          */
 431         if (!apic->irr_pending)
 432                 return -1;
 433
 434         result = apic_search_irr(apic);
 435         ASSERT(result == -1 || result >= 16);
 436
 437         return result;
 438 }
 439
 440 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 441 {
 442         struct kvm_vcpu *vcpu;
 443
 444         vcpu = apic->vcpu;
 445
 446         if (unlikely(vcpu->arch.apicv_active)) {
 447                 /* need to update RVI */
 448                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 449                 kvm_x86_ops->hwapic_irr_update(vcpu,
 450                                 apic_find_highest_irr(apic));
 451         } else {
 452                 apic->irr_pending = false;
 453                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 454                 if (apic_search_irr(apic) != -1)
 455                         apic->irr_pending = true;
 456         }
 457 }
 458
 459 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 460 {
 461         struct kvm_vcpu *vcpu;
 462
 463         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 464                 return;
 465
 466         vcpu = apic->vcpu;
 467
 468         /*
 469          * With APIC virtualization enabled, all caching is disabled
 470          * because the processor can modify ISR under the hood.  Instead
 471          * just set SVI.
 472          */
 473         if (unlikely(vcpu->arch.apicv_active))
 474                 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
 475         else {
 476                 ++apic->isr_count;
 477                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 478                 /*
 479                  * ISR (in service register) bit is set when injecting an interrupt.
 480                  * The highest vector is injected. Thus the latest bit set matches
 481                  * the highest bit in ISR.
 482                  */
 483                 apic->highest_isr_cache = vec;
 484         }
 485 }
 486
 487 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 488 {
 489         int result;
 490
 491         /*
 492          * Note that isr_count is always 1, and highest_isr_cache
 493          * is always -1, with APIC virtualization enabled.
 494          */
 495         if (!apic->isr_count)
 496                 return -1;
 497         if (likely(apic->highest_isr_cache != -1))
 498                 return apic->highest_isr_cache;
 499
 500         result = find_highest_vector(apic->regs + APIC_ISR);
 501         ASSERT(result == -1 || result >= 16);
 502
 503         return result;
 504 }
 505
 506 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 507 {
 508         struct kvm_vcpu *vcpu;
 509         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 510                 return;
 511
 512         vcpu = apic->vcpu;
 513
 514         /*
 515          * We do get here for APIC virtualization enabled if the guest
 516          * uses the Hyper-V APIC enlightenment.  In this case we may need
 517          * to trigger a new interrupt delivery by writing the SVI field;
 518          * on the other hand isr_count and highest_isr_cache are unused
 519          * and must be left alone.
 520          */
 521         if (unlikely(vcpu->arch.apicv_active))
 522                 kvm_x86_ops->hwapic_isr_update(vcpu,
 523                                                apic_find_highest_isr(apic));
 524         else {
 525                 --apic->isr_count;
 526                 BUG_ON(apic->isr_count < 0);
 527                 apic->highest_isr_cache = -1;
 528         }
 529 }
 530
 531 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 532 {
 533         /* This may race with setting of irr in __apic_accept_irq() and
 534          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 535          * will cause vmexit immediately and the value will be recalculated
 536          * on the next vmentry.
 537          */
 538         return apic_find_highest_irr(vcpu->arch.apic);
 539 }
 540 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 541
 542 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 543                              int vector, int level, int trig_mode,
 544                              struct dest_map *dest_map);
 545
 546 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 547                      struct dest_map *dest_map)
 548 {
 549         struct kvm_lapic *apic = vcpu->arch.apic;
 550
 551         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 552                         irq->level, irq->trig_mode, dest_map);
 553 }
 554
 555 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
 556                     unsigned long ipi_bitmap_high, u32 min,
 557                     unsigned long icr, int op_64_bit)
 558 {
 559         int i;
 560         struct kvm_apic_map *map;
 561         struct kvm_vcpu *vcpu;
 562         struct kvm_lapic_irq irq = {0};
 563         int cluster_size = op_64_bit ? 64 : 32;
 564         int count = 0;
 565
 566         irq.vector = icr & APIC_VECTOR_MASK;
 567         irq.delivery_mode = icr & APIC_MODE_MASK;
 568         irq.level = (icr & APIC_INT_ASSERT) != 0;
 569         irq.trig_mode = icr & APIC_INT_LEVELTRIG;
 570
 571         if (icr & APIC_DEST_MASK)
 572                 return -KVM_EINVAL;
 573         if (icr & APIC_SHORT_MASK)
 574                 return -KVM_EINVAL;
 575
 576         rcu_read_lock();
 577         map = rcu_dereference(kvm->arch.apic_map);
 578
 579         if (unlikely(!map)) {
 580                 count = -EOPNOTSUPP;
 581                 goto out;
 582         }
 583
 584         if (min > map->max_apic_id)
 585                 goto out;
 586         /* Bits above cluster_size are masked in the caller.  */
 587         for_each_set_bit(i, &ipi_bitmap_low,
 588                 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
 589                 if (map->phys_map[min + i]) {
 590                         vcpu = map->phys_map[min + i]->vcpu;
 591                         count += kvm_apic_set_irq(vcpu, &irq, NULL);
 592                 }
 593         }
 594
 595         min += cluster_size;
 596
 597         if (min > map->max_apic_id)
 598                 goto out;
 599
 600         for_each_set_bit(i, &ipi_bitmap_high,
 601                 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
 602                 if (map->phys_map[min + i]) {
 603                         vcpu = map->phys_map[min + i]->vcpu;
 604                         count += kvm_apic_set_irq(vcpu, &irq, NULL);
 605                 }
 606         }
 607
 608 out:
 609         rcu_read_unlock();
 610         return count;
 611 }
 612
 613 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 614 {
 615
 616         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 617                                       sizeof(val));
 618 }
 619
 620 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 621 {
 622
 623         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 624                                       sizeof(*val));
 625 }
 626
 627 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 628 {
 629         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 630 }
 631
 632 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 633 {
 634         u8 val;
 635         if (pv_eoi_get_user(vcpu, &val) < 0)
 636                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 637                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 638         return val & 0x1;
 639 }
 640
 641 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 642 {
 643         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 644                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 645                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 646                 return;
 647         }
 648         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 649 }
 650
 651 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 652 {
 653         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 654                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 655                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 656                 return;
 657         }
 658         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 659 }
 660
 661 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
 662 {
 663         int highest_irr;
 664         if (apic->vcpu->arch.apicv_active)
 665                 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 666         else
 667                 highest_irr = apic_find_highest_irr(apic);
 668         if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
 669                 return -1;
 670         return highest_irr;
 671 }
 672
 673 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
 674 {
 675         u32 tpr, isrv, ppr, old_ppr;
 676         int isr;
 677
 678         old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
 679         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
 680         isr = apic_find_highest_isr(apic);
 681         isrv = (isr != -1) ? isr : 0;
 682
 683         if ((tpr & 0xf0) >= (isrv & 0xf0))
 684                 ppr = tpr & 0xff;
 685         else
 686                 ppr = isrv & 0xf0;
 687
 688         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 689                    apic, ppr, isr, isrv);
 690
 691         *new_ppr = ppr;
 692         if (old_ppr != ppr)
 693                 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
 694
 695         return ppr < old_ppr;
 696 }
 697
 698 static void apic_update_ppr(struct kvm_lapic *apic)
 699 {
 700         u32 ppr;
 701
 702         if (__apic_update_ppr(apic, &ppr) &&
 703             apic_has_interrupt_for_ppr(apic, ppr) != -1)
 704                 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 705 }
 706
 707 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
 708 {
 709         apic_update_ppr(vcpu->arch.apic);
 710 }
 711 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
 712
 713 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 714 {
 715         kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
 716         apic_update_ppr(apic);
 717 }
 718
 719 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 720 {
 721         return mda == (apic_x2apic_mode(apic) ?
 722                         X2APIC_BROADCAST : APIC_BROADCAST);
 723 }
 724
 725 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 726 {
 727         if (kvm_apic_broadcast(apic, mda))
 728                 return true;
 729
 730         if (apic_x2apic_mode(apic))
 731                 return mda == kvm_x2apic_id(apic);
 732
 733         /*
 734          * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
 735          * it were in x2APIC mode.  Hotplugged VCPUs start in xAPIC mode and
 736          * this allows unique addressing of VCPUs with APIC ID over 0xff.
 737          * The 0xff condition is needed because writeable xAPIC ID.
 738          */
 739         if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
 740                 return true;
 741
 742         return mda == kvm_xapic_id(apic);
 743 }
 744
 745 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 746 {
 747         u32 logical_id;
 748
 749         if (kvm_apic_broadcast(apic, mda))
 750                 return true;
 751
 752         logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
 753
 754         if (apic_x2apic_mode(apic))
 755                 return ((logical_id >> 16) == (mda >> 16))
 756                        && (logical_id & mda & 0xffff) != 0;
 757
 758         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 759
 760         switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
 761         case APIC_DFR_FLAT:
 762                 return (logical_id & mda) != 0;
 763         case APIC_DFR_CLUSTER:
 764                 return ((logical_id >> 4) == (mda >> 4))
 765                        && (logical_id & mda & 0xf) != 0;
 766         default:
 767                 apic_debug("Bad DFR vcpu %d: %08x\n",
 768                            apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
 769                 return false;
 770         }
 771 }
 772
 773 /* The KVM local APIC implementation has two quirks:
 774  *
 775  *  - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
 776  *    in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
 777  *    KVM doesn't do that aliasing.
 778  *
 779  *  - in-kernel IOAPIC messages have to be delivered directly to
 780  *    x2APIC, because the kernel does not support interrupt remapping.
 781  *    In order to support broadcast without interrupt remapping, x2APIC
 782  *    rewrites the destination of non-IPI messages from APIC_BROADCAST
 783  *    to X2APIC_BROADCAST.
 784  *
 785  * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API.  This is
 786  * important when userspace wants to use x2APIC-format MSIs, because
 787  * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
 788  */
 789 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
 790                 struct kvm_lapic *source, struct kvm_lapic *target)
 791 {
 792         bool ipi = source != NULL;
 793
 794         if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
 795             !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
 796                 return X2APIC_BROADCAST;
 797
 798         return dest_id;
 799 }
 800
 801 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 802                            int short_hand, unsigned int dest, int dest_mode)
 803 {
 804         struct kvm_lapic *target = vcpu->arch.apic;
 805         u32 mda = kvm_apic_mda(vcpu, dest, source, target);
 806
 807         apic_debug("target %p, source %p, dest 0x%x, "
 808                    "dest_mode 0x%x, short_hand 0x%x\n",
 809                    target, source, dest, dest_mode, short_hand);
 810
 811         ASSERT(target);
 812         switch (short_hand) {
 813         case APIC_DEST_NOSHORT:
 814                 if (dest_mode == APIC_DEST_PHYSICAL)
 815                         return kvm_apic_match_physical_addr(target, mda);
 816                 else
 817                         return kvm_apic_match_logical_addr(target, mda);
 818         case APIC_DEST_SELF:
 819                 return target == source;
 820         case APIC_DEST_ALLINC:
 821                 return true;
 822         case APIC_DEST_ALLBUT:
 823                 return target != source;
 824         default:
 825                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 826                            short_hand);
 827                 return false;
 828         }
 829 }
 830 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
 831
 832 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 833                        const unsigned long *bitmap, u32 bitmap_size)
 834 {
 835         u32 mod;
 836         int i, idx = -1;
 837
 838         mod = vector % dest_vcpus;
 839
 840         for (i = 0; i <= mod; i++) {
 841                 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
 842                 BUG_ON(idx == bitmap_size);
 843         }
 844
 845         return idx;
 846 }
 847
 848 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
 849 {
 850         if (!kvm->arch.disabled_lapic_found) {
 851                 kvm->arch.disabled_lapic_found = true;
 852                 printk(KERN_INFO
 853                        "Disabled LAPIC found during irq injection\n");
 854         }
 855 }
 856
 857 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
 858                 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
 859 {
 860         if (kvm->arch.x2apic_broadcast_quirk_disabled) {
 861                 if ((irq->dest_id == APIC_BROADCAST &&
 862                                 map->mode != KVM_APIC_MODE_X2APIC))
 863                         return true;
 864                 if (irq->dest_id == X2APIC_BROADCAST)
 865                         return true;
 866         } else {
 867                 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
 868                 if (irq->dest_id == (x2apic_ipi ?
 869                                      X2APIC_BROADCAST : APIC_BROADCAST))
 870                         return true;
 871         }
 872
 873         return false;
 874 }
 875
 876 /* Return true if the interrupt can be handled by using *bitmap as index mask
 877  * for valid destinations in *dst array.
 878  * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
 879  * Note: we may have zero kvm_lapic destinations when we return true, which
 880  * means that the interrupt should be dropped.  In this case, *bitmap would be
 881  * zero and *dst undefined.
 882  */
 883 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
 884                 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
 885                 struct kvm_apic_map *map, struct kvm_lapic ***dst,
 886                 unsigned long *bitmap)
 887 {
 888         int i, lowest;
 889
 890         if (irq->shorthand == APIC_DEST_SELF && src) {
 891                 *dst = src;
 892                 *bitmap = 1;
 893                 return true;
 894         } else if (irq->shorthand)
 895                 return false;
 896
 897         if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
 898                 return false;
 899
 900         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 901                 if (irq->dest_id > map->max_apic_id) {
 902                         *bitmap = 0;
 903                 } else {
 904                         u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1);
 905                         *dst = &map->phys_map[dest_id];
 906                         *bitmap = 1;
 907                 }
 908                 return true;
 909         }
 910
 911         *bitmap = 0;
 912         if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
 913                                 (u16 *)bitmap))
 914                 return false;
 915
 916         if (!kvm_lowest_prio_delivery(irq))
 917                 return true;
 918
 919         if (!kvm_vector_hashing_enabled()) {
 920                 lowest = -1;
 921                 for_each_set_bit(i, bitmap, 16) {
 922                         if (!(*dst)[i])
 923                                 continue;
 924                         if (lowest < 0)
 925                                 lowest = i;
 926                         else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
 927                                                 (*dst)[lowest]->vcpu) < 0)
 928                                 lowest = i;
 929                 }
 930         } else {
 931                 if (!*bitmap)
 932                         return true;
 933
 934                 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
 935                                 bitmap, 16);
 936
 937                 if (!(*dst)[lowest]) {
 938                         kvm_apic_disabled_lapic_found(kvm);
 939                         *bitmap = 0;
 940                         return true;
 941                 }
 942         }
 943
 944         *bitmap = (lowest >= 0) ? 1 << lowest : 0;
 945
 946         return true;
 947 }
 948
 949 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 950                 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
 951 {
 952         struct kvm_apic_map *map;
 953         unsigned long bitmap;
 954         struct kvm_lapic **dst = NULL;
 955         int i;
 956         bool ret;
 957
 958         *r = -1;
 959
 960         if (irq->shorthand == APIC_DEST_SELF) {
 961                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 962                 return true;
 963         }
 964
 965         rcu_read_lock();
 966         map = rcu_dereference(kvm->arch.apic_map);
 967
 968         ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
 969         if (ret) {
 970                 *r = 0;
 971                 for_each_set_bit(i, &bitmap, 16) {
 972                         if (!dst[i])
 973                                 continue;
 974                         *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 975                 }
 976         }
 977
 978         rcu_read_unlock();
 979         return ret;
 980 }
 981
 982 /*
 983  * This routine tries to handler interrupts in posted mode, here is how
 984  * it deals with different cases:
 985  * - For single-destination interrupts, handle it in posted mode
 986  * - Else if vector hashing is enabled and it is a lowest-priority
 987  *   interrupt, handle it in posted mode and use the following mechanism
 988  *   to find the destinaiton vCPU.
 989  *      1. For lowest-priority interrupts, store all the possible
 990  *         destination vCPUs in an array.
 991  *      2. Use "guest vector % max number of destination vCPUs" to find
 992  *         the right destination vCPU in the array for the lowest-priority
 993  *         interrupt.
 994  * - Otherwise, use remapped mode to inject the interrupt.
 995  */
 996 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 997                         struct kvm_vcpu **dest_vcpu)
 998 {
 999         struct kvm_apic_map *map;
1000         unsigned long bitmap;
1001         struct kvm_lapic **dst = NULL;
1002         bool ret = false;
1003
1004         if (irq->shorthand)
1005                 return false;
1006
1007         rcu_read_lock();
1008         map = rcu_dereference(kvm->arch.apic_map);
1009
1010         if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1011                         hweight16(bitmap) == 1) {
1012                 unsigned long i = find_first_bit(&bitmap, 16);
1013
1014                 if (dst[i]) {
1015                         *dest_vcpu = dst[i]->vcpu;
1016                         ret = true;
1017                 }
1018         }
1019
1020         rcu_read_unlock();
1021         return ret;
1022 }
1023
1024 /*
1025  * Add a pending IRQ into lapic.
1026  * Return 1 if successfully added and 0 if discarded.
1027  */
1028 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1029                              int vector, int level, int trig_mode,
1030                              struct dest_map *dest_map)
1031 {
1032         int result = 0;
1033         struct kvm_vcpu *vcpu = apic->vcpu;
1034
1035         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1036                                   trig_mode, vector);
1037         switch (delivery_mode) {
1038         case APIC_DM_LOWEST:
1039                 vcpu->arch.apic_arb_prio++;
1040                 /* fall through */
1041         case APIC_DM_FIXED:
1042                 if (unlikely(trig_mode && !level))
1043                         break;
1044
1045                 /* FIXME add logic for vcpu on reset */
1046                 if (unlikely(!apic_enabled(apic)))
1047                         break;
1048
1049                 result = 1;
1050
1051                 if (dest_map) {
1052                         __set_bit(vcpu->vcpu_id, dest_map->map);
1053                         dest_map->vectors[vcpu->vcpu_id] = vector;
1054                 }
1055
1056                 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1057                         if (trig_mode)
1058                                 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
1059                         else
1060                                 apic_clear_vector(vector, apic->regs + APIC_TMR);
1061                 }
1062
1063                 if (vcpu->arch.apicv_active)
1064                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
1065                 else {
1066                         kvm_lapic_set_irr(vector, apic);
1067
1068                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1069                         kvm_vcpu_kick(vcpu);
1070                 }
1071                 break;
1072
1073         case APIC_DM_REMRD:
1074                 result = 1;
1075                 vcpu->arch.pv.pv_unhalted = 1;
1076                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1077                 kvm_vcpu_kick(vcpu);
1078                 break;
1079
1080         case APIC_DM_SMI:
1081                 result = 1;
1082                 kvm_make_request(KVM_REQ_SMI, vcpu);
1083                 kvm_vcpu_kick(vcpu);
1084                 break;
1085
1086         case APIC_DM_NMI:
1087                 result = 1;
1088                 kvm_inject_nmi(vcpu);
1089                 kvm_vcpu_kick(vcpu);
1090                 break;
1091
1092         case APIC_DM_INIT:
1093                 if (!trig_mode || level) {
1094                         result = 1;
1095                         /* assumes that there are only KVM_APIC_INIT/SIPI */
1096                         apic->pending_events = (1UL << KVM_APIC_INIT);
1097                         /* make sure pending_events is visible before sending
1098                          * the request */
1099                         smp_wmb();
1100                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1101                         kvm_vcpu_kick(vcpu);
1102                 } else {
1103                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1104                                    vcpu->vcpu_id);
1105                 }
1106                 break;
1107
1108         case APIC_DM_STARTUP:
1109                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1110                            vcpu->vcpu_id, vector);
1111                 result = 1;
1112                 apic->sipi_vector = vector;
1113                 /* make sure sipi_vector is visible for the receiver */
1114                 smp_wmb();
1115                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1116                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1117                 kvm_vcpu_kick(vcpu);
1118                 break;
1119
1120         case APIC_DM_EXTINT:
1121                 /*
1122                  * Should only be called by kvm_apic_local_deliver() with LVT0,
1123                  * before NMI watchdog was enabled. Already handled by
1124                  * kvm_apic_accept_pic_intr().
1125                  */
1126                 break;
1127
1128         default:
1129                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1130                        delivery_mode);
1131                 break;
1132         }
1133         return result;
1134 }
1135
1136 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1137 {
1138         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1139 }
1140
1141 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1142 {
1143         return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1144 }
1145
1146 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1147 {
1148         int trigger_mode;
1149
1150         /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1151         if (!kvm_ioapic_handles_vector(apic, vector))
1152                 return;
1153
1154         /* Request a KVM exit to inform the userspace IOAPIC. */
1155         if (irqchip_split(apic->vcpu->kvm)) {
1156                 apic->vcpu->arch.pending_ioapic_eoi = vector;
1157                 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1158                 return;
1159         }
1160
1161         if (apic_test_vector(vector, apic->regs + APIC_TMR))
1162                 trigger_mode = IOAPIC_LEVEL_TRIG;
1163         else
1164                 trigger_mode = IOAPIC_EDGE_TRIG;
1165
1166         kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1167 }
1168
1169 static int apic_set_eoi(struct kvm_lapic *apic)
1170 {
1171         int vector = apic_find_highest_isr(apic);
1172
1173         trace_kvm_eoi(apic, vector);
1174
1175         /*
1176          * Not every write EOI will has corresponding ISR,
1177          * one example is when Kernel check timer on setup_IO_APIC
1178          */
1179         if (vector == -1)
1180                 return vector;
1181
1182         apic_clear_isr(vector, apic);
1183         apic_update_ppr(apic);
1184
1185         if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1186                 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1187
1188         kvm_ioapic_send_eoi(apic, vector);
1189         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1190         return vector;
1191 }
1192
1193 /*
1194  * this interface assumes a trap-like exit, which has already finished
1195  * desired side effect including vISR and vPPR update.
1196  */
1197 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1198 {
1199         struct kvm_lapic *apic = vcpu->arch.apic;
1200
1201         trace_kvm_eoi(apic, vector);
1202
1203         kvm_ioapic_send_eoi(apic, vector);
1204         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1205 }
1206 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1207
1208 static void apic_send_ipi(struct kvm_lapic *apic)
1209 {
1210         u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1211         u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1212         struct kvm_lapic_irq irq;
1213
1214         irq.vector = icr_low & APIC_VECTOR_MASK;
1215         irq.delivery_mode = icr_low & APIC_MODE_MASK;
1216         irq.dest_mode = icr_low & APIC_DEST_MASK;
1217         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1218         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1219         irq.shorthand = icr_low & APIC_SHORT_MASK;
1220         irq.msi_redir_hint = false;
1221         if (apic_x2apic_mode(apic))
1222                 irq.dest_id = icr_high;
1223         else
1224                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1225
1226         trace_kvm_apic_ipi(icr_low, irq.dest_id);
1227
1228         apic_debug("icr_high 0x%x, icr_low 0x%x, "
1229                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1230                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1231                    "msi_redir_hint 0x%x\n",
1232                    icr_high, icr_low, irq.shorthand, irq.dest_id,
1233                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1234                    irq.vector, irq.msi_redir_hint);
1235
1236         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1237 }
1238
1239 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1240 {
1241         ktime_t remaining, now;
1242         s64 ns;
1243         u32 tmcct;
1244
1245         ASSERT(apic != NULL);
1246
1247         /* if initial count is 0, current count should also be 0 */
1248         if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1249                 apic->lapic_timer.period == 0)
1250                 return 0;
1251
1252         now = ktime_get();
1253         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1254         if (ktime_to_ns(remaining) < 0)
1255                 remaining = 0;
1256
1257         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1258         tmcct = div64_u64(ns,
1259                          (APIC_BUS_CYCLE_NS * apic->divide_count));
1260
1261         return tmcct;
1262 }
1263
1264 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1265 {
1266         struct kvm_vcpu *vcpu = apic->vcpu;
1267         struct kvm_run *run = vcpu->run;
1268
1269         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1270         run->tpr_access.rip = kvm_rip_read(vcpu);
1271         run->tpr_access.is_write = write;
1272 }
1273
1274 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1275 {
1276         if (apic->vcpu->arch.tpr_access_reporting)
1277                 __report_tpr_access(apic, write);
1278 }
1279
1280 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1281 {
1282         u32 val = 0;
1283
1284         if (offset >= LAPIC_MMIO_LENGTH)
1285                 return 0;
1286
1287         switch (offset) {
1288         case APIC_ARBPRI:
1289                 apic_debug("Access APIC ARBPRI register which is for P6\n");
1290                 break;
1291
1292         case APIC_TMCCT:        /* Timer CCR */
1293                 if (apic_lvtt_tscdeadline(apic))
1294                         return 0;
1295
1296                 val = apic_get_tmcct(apic);
1297                 break;
1298         case APIC_PROCPRI:
1299                 apic_update_ppr(apic);
1300                 val = kvm_lapic_get_reg(apic, offset);
1301                 break;
1302         case APIC_TASKPRI:
1303                 report_tpr_access(apic, false);
1304                 /* fall thru */
1305         default:
1306                 val = kvm_lapic_get_reg(apic, offset);
1307                 break;
1308         }
1309
1310         return val;
1311 }
1312
1313 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1314 {
1315         return container_of(dev, struct kvm_lapic, dev);
1316 }
1317
1318 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1319                 void *data)
1320 {
1321         unsigned char alignment = offset & 0xf;
1322         u32 result;
1323         /* this bitmask has a bit cleared for each reserved register */
1324         static const u64 rmask = 0x43ff01ffffffe70cULL;
1325
1326         if ((alignment + len) > 4) {
1327                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1328                            offset, len);
1329                 return 1;
1330         }
1331
1332         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1333                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1334                            offset);
1335                 return 1;
1336         }
1337
1338         result = __apic_read(apic, offset & ~0xf);
1339
1340         trace_kvm_apic_read(offset, result);
1341
1342         switch (len) {
1343         case 1:
1344         case 2:
1345         case 4:
1346                 memcpy(data, (char *)&result + alignment, len);
1347                 break;
1348         default:
1349                 printk(KERN_ERR "Local APIC read with len = %x, "
1350                        "should be 1,2, or 4 instead\n", len);
1351                 break;
1352         }
1353         return 0;
1354 }
1355 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1356
1357 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1358 {
1359         return addr >= apic->base_address &&
1360                 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1361 }
1362
1363 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1364                            gpa_t address, int len, void *data)
1365 {
1366         struct kvm_lapic *apic = to_lapic(this);
1367         u32 offset = address - apic->base_address;
1368
1369         if (!apic_mmio_in_range(apic, address))
1370                 return -EOPNOTSUPP;
1371
1372         if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1373                 if (!kvm_check_has_quirk(vcpu->kvm,
1374                                          KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1375                         return -EOPNOTSUPP;
1376
1377                 memset(data, 0xff, len);
1378                 return 0;
1379         }
1380
1381         kvm_lapic_reg_read(apic, offset, len, data);
1382
1383         return 0;
1384 }
1385
1386 static void update_divide_count(struct kvm_lapic *apic)
1387 {
1388         u32 tmp1, tmp2, tdcr;
1389
1390         tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1391         tmp1 = tdcr & 0xf;
1392         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1393         apic->divide_count = 0x1 << (tmp2 & 0x7);
1394
1395         apic_debug("timer divide count is 0x%x\n",
1396                                    apic->divide_count);
1397 }
1398
1399 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1400 {
1401         /*
1402          * Do not allow the guest to program periodic timers with small
1403          * interval, since the hrtimers are not throttled by the host
1404          * scheduler.
1405          */
1406         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1407                 s64 min_period = min_timer_period_us * 1000LL;
1408
1409                 if (apic->lapic_timer.period < min_period) {
1410                         pr_info_ratelimited(
1411                             "kvm: vcpu %i: requested %lld ns "
1412                             "lapic timer period limited to %lld ns\n",
1413                             apic->vcpu->vcpu_id,
1414                             apic->lapic_timer.period, min_period);
1415                         apic->lapic_timer.period = min_period;
1416                 }
1417         }
1418 }
1419
1420 static void apic_update_lvtt(struct kvm_lapic *apic)
1421 {
1422         u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1423                         apic->lapic_timer.timer_mode_mask;
1424
1425         if (apic->lapic_timer.timer_mode != timer_mode) {
1426                 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1427                                 APIC_LVT_TIMER_TSCDEADLINE)) {
1428                         hrtimer_cancel(&apic->lapic_timer.timer);
1429                         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1430                         apic->lapic_timer.period = 0;
1431                         apic->lapic_timer.tscdeadline = 0;
1432                 }
1433                 apic->lapic_timer.timer_mode = timer_mode;
1434                 limit_periodic_timer_frequency(apic);
1435         }
1436 }
1437
1438 static void apic_timer_expired(struct kvm_lapic *apic)
1439 {
1440         struct kvm_vcpu *vcpu = apic->vcpu;
1441         struct swait_queue_head *q = &vcpu->wq;
1442         struct kvm_timer *ktimer = &apic->lapic_timer;
1443
1444         if (atomic_read(&apic->lapic_timer.pending))
1445                 return;
1446
1447         atomic_inc(&apic->lapic_timer.pending);
1448         kvm_set_pending_timer(vcpu);
1449
1450         /*
1451          * For x86, the atomic_inc() is serialized, thus
1452          * using swait_active() is safe.
1453          */
1454         if (swait_active(q))
1455                 swake_up_one(q);
1456
1457         if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
1458                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1459 }
1460
1461 /*
1462  * On APICv, this test will cause a busy wait
1463  * during a higher-priority task.
1464  */
1465
1466 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1467 {
1468         struct kvm_lapic *apic = vcpu->arch.apic;
1469         u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1470
1471         if (kvm_apic_hw_enabled(apic)) {
1472                 int vec = reg & APIC_VECTOR_MASK;
1473                 void *bitmap = apic->regs + APIC_ISR;
1474
1475                 if (vcpu->arch.apicv_active)
1476                         bitmap = apic->regs + APIC_IRR;
1477
1478                 if (apic_test_vector(vec, bitmap))
1479                         return true;
1480         }
1481         return false;
1482 }
1483
1484 static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles)
1485 {
1486         u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;
1487
1488         /*
1489          * If the guest TSC is running at a different ratio than the host, then
1490          * convert the delay to nanoseconds to achieve an accurate delay.  Note
1491          * that __delay() uses delay_tsc whenever the hardware has TSC, thus
1492          * always for VMX enabled hardware.
1493          */
1494         if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) {
1495                 __delay(min(guest_cycles,
1496                         nsec_to_cycles(vcpu, timer_advance_ns)));
1497         } else {
1498                 u64 delay_ns = guest_cycles * 1000000ULL;
1499                 do_div(delay_ns, vcpu->arch.virtual_tsc_khz);
1500                 ndelay(min_t(u32, delay_ns, timer_advance_ns));
1501         }
1502 }
1503
1504 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1505 {
1506         struct kvm_lapic *apic = vcpu->arch.apic;
1507         u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
1508         u64 guest_tsc, tsc_deadline, ns;
1509
1510         if (apic->lapic_timer.expired_tscdeadline == 0)
1511                 return;
1512
1513         if (!lapic_timer_int_injected(vcpu))
1514                 return;
1515
1516         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1517         apic->lapic_timer.expired_tscdeadline = 0;
1518         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1519         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1520
1521         if (guest_tsc < tsc_deadline)
1522                 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
1523
1524         if (!apic->lapic_timer.timer_advance_adjust_done) {
1525                 /* too early */
1526                 if (guest_tsc < tsc_deadline) {
1527                         ns = (tsc_deadline - guest_tsc) * 1000000ULL;
1528                         do_div(ns, vcpu->arch.virtual_tsc_khz);
1529                         timer_advance_ns -= min((u32)ns,
1530                                 timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP);
1531                 } else {
1532                 /* too late */
1533                         ns = (guest_tsc - tsc_deadline) * 1000000ULL;
1534                         do_div(ns, vcpu->arch.virtual_tsc_khz);
1535                         timer_advance_ns += min((u32)ns,
1536                                 timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP);
1537                 }
1538                 if (abs(guest_tsc - tsc_deadline) < LAPIC_TIMER_ADVANCE_ADJUST_DONE)
1539                         apic->lapic_timer.timer_advance_adjust_done = true;
1540                 if (unlikely(timer_advance_ns > 5000)) {
1541                         timer_advance_ns = 0;
1542                         apic->lapic_timer.timer_advance_adjust_done = true;
1543                 }
1544                 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
1545         }
1546 }
1547
1548 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1549 {
1550         struct kvm_timer *ktimer = &apic->lapic_timer;
1551         u64 guest_tsc, tscdeadline = ktimer->tscdeadline;
1552         u64 ns = 0;
1553         ktime_t expire;
1554         struct kvm_vcpu *vcpu = apic->vcpu;
1555         unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1556         unsigned long flags;
1557         ktime_t now;
1558
1559         if (unlikely(!tscdeadline || !this_tsc_khz))
1560                 return;
1561
1562         local_irq_save(flags);
1563
1564         now = ktime_get();
1565         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1566
1567         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1568         do_div(ns, this_tsc_khz);
1569
1570         if (likely(tscdeadline > guest_tsc) &&
1571             likely(ns > apic->lapic_timer.timer_advance_ns)) {
1572                 expire = ktime_add_ns(now, ns);
1573                 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns);
1574                 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_PINNED);
1575         } else
1576                 apic_timer_expired(apic);
1577
1578         local_irq_restore(flags);
1579 }
1580
1581 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1582 {
1583         ktime_t now, remaining;
1584         u64 ns_remaining_old, ns_remaining_new;
1585
1586         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1587                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1588         limit_periodic_timer_frequency(apic);
1589
1590         now = ktime_get();
1591         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1592         if (ktime_to_ns(remaining) < 0)
1593                 remaining = 0;
1594
1595         ns_remaining_old = ktime_to_ns(remaining);
1596         ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1597                                            apic->divide_count, old_divisor);
1598
1599         apic->lapic_timer.tscdeadline +=
1600                 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1601                 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1602         apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1603 }
1604
1605 static bool set_target_expiration(struct kvm_lapic *apic)
1606 {
1607         ktime_t now;
1608         u64 tscl = rdtsc();
1609
1610         now = ktime_get();
1611         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1612                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1613
1614         if (!apic->lapic_timer.period) {
1615                 apic->lapic_timer.tscdeadline = 0;
1616                 return false;
1617         }
1618
1619         limit_periodic_timer_frequency(apic);
1620
1621         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1622                    PRIx64 ", "
1623                    "timer initial count 0x%x, period %lldns, "
1624                    "expire @ 0x%016" PRIx64 ".\n", __func__,
1625                    APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1626                    kvm_lapic_get_reg(apic, APIC_TMICT),
1627                    apic->lapic_timer.period,
1628                    ktime_to_ns(ktime_add_ns(now,
1629                                 apic->lapic_timer.period)));
1630
1631         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1632                 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1633         apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1634
1635         return true;
1636 }
1637
1638 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1639 {
1640         ktime_t now = ktime_get();
1641         u64 tscl = rdtsc();
1642         ktime_t delta;
1643
1644         /*
1645          * Synchronize both deadlines to the same time source or
1646          * differences in the periods (caused by differences in the
1647          * underlying clocks or numerical approximation errors) will
1648          * cause the two to drift apart over time as the errors
1649          * accumulate.
1650          */
1651         apic->lapic_timer.target_expiration =
1652                 ktime_add_ns(apic->lapic_timer.target_expiration,
1653                                 apic->lapic_timer.period);
1654         delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1655         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1656                 nsec_to_cycles(apic->vcpu, delta);
1657 }
1658
1659 static void start_sw_period(struct kvm_lapic *apic)
1660 {
1661         if (!apic->lapic_timer.period)
1662                 return;
1663
1664         if (ktime_after(ktime_get(),
1665                         apic->lapic_timer.target_expiration)) {
1666                 apic_timer_expired(apic);
1667
1668                 if (apic_lvtt_oneshot(apic))
1669                         return;
1670
1671                 advance_periodic_target_expiration(apic);
1672         }
1673
1674         hrtimer_start(&apic->lapic_timer.timer,
1675                 apic->lapic_timer.target_expiration,
1676                 HRTIMER_MODE_ABS_PINNED);
1677 }
1678
1679 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1680 {
1681         if (!lapic_in_kernel(vcpu))
1682                 return false;
1683
1684         return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1685 }
1686 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1687
1688 static void cancel_hv_timer(struct kvm_lapic *apic)
1689 {
1690         WARN_ON(preemptible());
1691         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1692         kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1693         apic->lapic_timer.hv_timer_in_use = false;
1694 }
1695
1696 static bool start_hv_timer(struct kvm_lapic *apic)
1697 {
1698         struct kvm_timer *ktimer = &apic->lapic_timer;
1699         struct kvm_vcpu *vcpu = apic->vcpu;
1700         bool expired;
1701
1702         WARN_ON(preemptible());
1703         if (!kvm_x86_ops->set_hv_timer)
1704                 return false;
1705
1706         if (!ktimer->tscdeadline)
1707                 return false;
1708
1709         if (kvm_x86_ops->set_hv_timer(vcpu, ktimer->tscdeadline, &expired))
1710                 return false;
1711
1712         ktimer->hv_timer_in_use = true;
1713         hrtimer_cancel(&ktimer->timer);
1714
1715         /*
1716          * To simplify handling the periodic timer, leave the hv timer running
1717          * even if the deadline timer has expired, i.e. rely on the resulting
1718          * VM-Exit to recompute the periodic timer's target expiration.
1719          */
1720         if (!apic_lvtt_period(apic)) {
1721                 /*
1722                  * Cancel the hv timer if the sw timer fired while the hv timer
1723                  * was being programmed, or if the hv timer itself expired.
1724                  */
1725                 if (atomic_read(&ktimer->pending)) {
1726                         cancel_hv_timer(apic);
1727                 } else if (expired) {
1728                         apic_timer_expired(apic);
1729                         cancel_hv_timer(apic);
1730                 }
1731         }
1732
1733         trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use);
1734
1735         return true;
1736 }
1737
1738 static void start_sw_timer(struct kvm_lapic *apic)
1739 {
1740         struct kvm_timer *ktimer = &apic->lapic_timer;
1741
1742         WARN_ON(preemptible());
1743         if (apic->lapic_timer.hv_timer_in_use)
1744                 cancel_hv_timer(apic);
1745         if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1746                 return;
1747
1748         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1749                 start_sw_period(apic);
1750         else if (apic_lvtt_tscdeadline(apic))
1751                 start_sw_tscdeadline(apic);
1752         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1753 }
1754
1755 static void restart_apic_timer(struct kvm_lapic *apic)
1756 {
1757         preempt_disable();
1758
1759         if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending))
1760                 goto out;
1761
1762         if (!start_hv_timer(apic))
1763                 start_sw_timer(apic);
1764 out:
1765         preempt_enable();
1766 }
1767
1768 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1769 {
1770         struct kvm_lapic *apic = vcpu->arch.apic;
1771
1772         preempt_disable();
1773         /* If the preempt notifier has already run, it also called apic_timer_expired */
1774         if (!apic->lapic_timer.hv_timer_in_use)
1775                 goto out;
1776         WARN_ON(swait_active(&vcpu->wq));
1777         cancel_hv_timer(apic);
1778         apic_timer_expired(apic);
1779
1780         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1781                 advance_periodic_target_expiration(apic);
1782                 restart_apic_timer(apic);
1783         }
1784 out:
1785         preempt_enable();
1786 }
1787 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1788
1789 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1790 {
1791         restart_apic_timer(vcpu->arch.apic);
1792 }
1793 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1794
1795 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1796 {
1797         struct kvm_lapic *apic = vcpu->arch.apic;
1798
1799         preempt_disable();
1800         /* Possibly the TSC deadline timer is not enabled yet */
1801         if (apic->lapic_timer.hv_timer_in_use)
1802                 start_sw_timer(apic);
1803         preempt_enable();
1804 }
1805 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1806
1807 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1808 {
1809         struct kvm_lapic *apic = vcpu->arch.apic;
1810
1811         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1812         restart_apic_timer(apic);
1813 }
1814
1815 static void start_apic_timer(struct kvm_lapic *apic)
1816 {
1817         atomic_set(&apic->lapic_timer.pending, 0);
1818
1819         if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1820             && !set_target_expiration(apic))
1821                 return;
1822
1823         restart_apic_timer(apic);
1824 }
1825
1826 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1827 {
1828         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1829
1830         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1831                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1832                 if (lvt0_in_nmi_mode) {
1833                         apic_debug("Receive NMI setting on APIC_LVT0 "
1834                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1835                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1836                 } else
1837                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1838         }
1839 }
1840
1841 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1842 {
1843         int ret = 0;
1844
1845         trace_kvm_apic_write(reg, val);
1846
1847         switch (reg) {
1848         case APIC_ID:           /* Local APIC ID */
1849                 if (!apic_x2apic_mode(apic))
1850                         kvm_apic_set_xapic_id(apic, val >> 24);
1851                 else
1852                         ret = 1;
1853                 break;
1854
1855         case APIC_TASKPRI:
1856                 report_tpr_access(apic, true);
1857                 apic_set_tpr(apic, val & 0xff);
1858                 break;
1859
1860         case APIC_EOI:
1861                 apic_set_eoi(apic);
1862                 break;
1863
1864         case APIC_LDR:
1865                 if (!apic_x2apic_mode(apic))
1866                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1867                 else
1868                         ret = 1;
1869                 break;
1870
1871         case APIC_DFR:
1872                 if (!apic_x2apic_mode(apic)) {
1873                         kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1874                         recalculate_apic_map(apic->vcpu->kvm);
1875                 } else
1876                         ret = 1;
1877                 break;
1878
1879         case APIC_SPIV: {
1880                 u32 mask = 0x3ff;
1881                 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1882                         mask |= APIC_SPIV_DIRECTED_EOI;
1883                 apic_set_spiv(apic, val & mask);
1884                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1885                         int i;
1886                         u32 lvt_val;
1887
1888                         for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1889                                 lvt_val = kvm_lapic_get_reg(apic,
1890                                                        APIC_LVTT + 0x10 * i);
1891                                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1892                                              lvt_val | APIC_LVT_MASKED);
1893                         }
1894                         apic_update_lvtt(apic);
1895                         atomic_set(&apic->lapic_timer.pending, 0);
1896
1897                 }
1898                 break;
1899         }
1900         case APIC_ICR:
1901                 /* No delay here, so we always clear the pending bit */
1902                 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1903                 apic_send_ipi(apic);
1904                 break;
1905
1906         case APIC_ICR2:
1907                 if (!apic_x2apic_mode(apic))
1908                         val &= 0xff000000;
1909                 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1910                 break;
1911
1912         case APIC_LVT0:
1913                 apic_manage_nmi_watchdog(apic, val);
1914                 /* fall through */
1915         case APIC_LVTTHMR:
1916         case APIC_LVTPC:
1917         case APIC_LVT1:
1918         case APIC_LVTERR:
1919                 /* TODO: Check vector */
1920                 if (!kvm_apic_sw_enabled(apic))
1921                         val |= APIC_LVT_MASKED;
1922
1923                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1924                 kvm_lapic_set_reg(apic, reg, val);
1925
1926                 break;
1927
1928         case APIC_LVTT:
1929                 if (!kvm_apic_sw_enabled(apic))
1930                         val |= APIC_LVT_MASKED;
1931                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1932                 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1933                 apic_update_lvtt(apic);
1934                 break;
1935
1936         case APIC_TMICT:
1937                 if (apic_lvtt_tscdeadline(apic))
1938                         break;
1939
1940                 hrtimer_cancel(&apic->lapic_timer.timer);
1941                 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1942                 start_apic_timer(apic);
1943                 break;
1944
1945         case APIC_TDCR: {
1946                 uint32_t old_divisor = apic->divide_count;
1947
1948                 if (val & 4)
1949                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1950                 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1951                 update_divide_count(apic);
1952                 if (apic->divide_count != old_divisor &&
1953                                 apic->lapic_timer.period) {
1954                         hrtimer_cancel(&apic->lapic_timer.timer);
1955                         update_target_expiration(apic, old_divisor);
1956                         restart_apic_timer(apic);
1957                 }
1958                 break;
1959         }
1960         case APIC_ESR:
1961                 if (apic_x2apic_mode(apic) && val != 0) {
1962                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1963                         ret = 1;
1964                 }
1965                 break;
1966
1967         case APIC_SELF_IPI:
1968                 if (apic_x2apic_mode(apic)) {
1969                         kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1970                 } else
1971                         ret = 1;
1972                 break;
1973         default:
1974                 ret = 1;
1975                 break;
1976         }
1977         if (ret)
1978                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1979         return ret;
1980 }
1981 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1982
1983 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1984                             gpa_t address, int len, const void *data)
1985 {
1986         struct kvm_lapic *apic = to_lapic(this);
1987         unsigned int offset = address - apic->base_address;
1988         u32 val;
1989
1990         if (!apic_mmio_in_range(apic, address))
1991                 return -EOPNOTSUPP;
1992
1993         if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1994                 if (!kvm_check_has_quirk(vcpu->kvm,
1995                                          KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1996                         return -EOPNOTSUPP;
1997
1998                 return 0;
1999         }
2000
2001         /*
2002          * APIC register must be aligned on 128-bits boundary.
2003          * 32/64/128 bits registers must be accessed thru 32 bits.
2004          * Refer SDM 8.4.1
2005          */
2006         if (len != 4 || (offset & 0xf)) {
2007                 /* Don't shout loud, $infamous_os would cause only noise. */
2008                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
2009                 return 0;
2010         }
2011
2012         val = *(u32*)data;
2013
2014         /* too common printing */
2015         if (offset != APIC_EOI)
2016                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
2017                            "0x%x\n", __func__, offset, len, val);
2018
2019         kvm_lapic_reg_write(apic, offset & 0xff0, val);
2020
2021         return 0;
2022 }
2023
2024 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
2025 {
2026         kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
2027 }
2028 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
2029
2030 /* emulate APIC access in a trap manner */
2031 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
2032 {
2033         u32 val = 0;
2034
2035         /* hw has done the conditional check and inst decode */
2036         offset &= 0xff0;
2037
2038         kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
2039
2040         /* TODO: optimize to just emulate side effect w/o one more write */
2041         kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
2042 }
2043 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2044
2045 void kvm_free_lapic(struct kvm_vcpu *vcpu)
2046 {
2047         struct kvm_lapic *apic = vcpu->arch.apic;
2048
2049         if (!vcpu->arch.apic)
2050                 return;
2051
2052         hrtimer_cancel(&apic->lapic_timer.timer);
2053
2054         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2055                 static_key_slow_dec_deferred(&apic_hw_disabled);
2056
2057         if (!apic->sw_enabled)
2058                 static_key_slow_dec_deferred(&apic_sw_disabled);
2059
2060         if (apic->regs)
2061                 free_page((unsigned long)apic->regs);
2062
2063         kfree(apic);
2064 }
2065
2066 /*
2067  *----------------------------------------------------------------------
2068  * LAPIC interface
2069  *----------------------------------------------------------------------
2070  */
2071 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2072 {
2073         struct kvm_lapic *apic = vcpu->arch.apic;
2074
2075         if (!lapic_in_kernel(vcpu) ||
2076                 !apic_lvtt_tscdeadline(apic))
2077                 return 0;
2078
2079         return apic->lapic_timer.tscdeadline;
2080 }
2081
2082 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2083 {
2084         struct kvm_lapic *apic = vcpu->arch.apic;
2085
2086         if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
2087                         apic_lvtt_period(apic))
2088                 return;
2089
2090         hrtimer_cancel(&apic->lapic_timer.timer);
2091         apic->lapic_timer.tscdeadline = data;
2092         start_apic_timer(apic);
2093 }
2094
2095 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2096 {
2097         struct kvm_lapic *apic = vcpu->arch.apic;
2098
2099         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
2100                      | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
2101 }
2102
2103 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2104 {
2105         u64 tpr;
2106
2107         tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2108
2109         return (tpr & 0xf0) >> 4;
2110 }
2111
2112 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2113 {
2114         u64 old_value = vcpu->arch.apic_base;
2115         struct kvm_lapic *apic = vcpu->arch.apic;
2116
2117         if (!apic)
2118                 value |= MSR_IA32_APICBASE_BSP;
2119
2120         vcpu->arch.apic_base = value;
2121
2122         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2123                 kvm_update_cpuid(vcpu);
2124
2125         if (!apic)
2126                 return;
2127
2128         /* update jump label if enable bit changes */
2129         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2130                 if (value & MSR_IA32_APICBASE_ENABLE) {
2131                         kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2132                         static_key_slow_dec_deferred(&apic_hw_disabled);
2133                 } else {
2134                         static_key_slow_inc(&apic_hw_disabled.key);
2135                         recalculate_apic_map(vcpu->kvm);
2136                 }
2137         }
2138
2139         if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2140                 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2141
2142         if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2143                 kvm_x86_ops->set_virtual_apic_mode(vcpu);
2144
2145         apic->base_address = apic->vcpu->arch.apic_base &
2146                              MSR_IA32_APICBASE_BASE;
2147
2148         if ((value & MSR_IA32_APICBASE_ENABLE) &&
2149              apic->base_address != APIC_DEFAULT_PHYS_BASE)
2150                 pr_warn_once("APIC base relocation is unsupported by KVM");
2151
2152         /* with FSB delivery interrupt, we can restart APIC functionality */
2153         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
2154                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
2155
2156 }
2157
2158 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2159 {
2160         struct kvm_lapic *apic = vcpu->arch.apic;
2161         int i;
2162
2163         if (!apic)
2164                 return;
2165
2166         apic_debug("%s\n", __func__);
2167
2168         /* Stop the timer in case it's a reset to an active apic */
2169         hrtimer_cancel(&apic->lapic_timer.timer);
2170
2171         if (!init_event) {
2172                 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2173                                          MSR_IA32_APICBASE_ENABLE);
2174                 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2175         }
2176         kvm_apic_set_version(apic->vcpu);
2177
2178         for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2179                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2180         apic_update_lvtt(apic);
2181         if (kvm_vcpu_is_reset_bsp(vcpu) &&
2182             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2183                 kvm_lapic_set_reg(apic, APIC_LVT0,
2184                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2185         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2186
2187         kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
2188         apic_set_spiv(apic, 0xff);
2189         kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2190         if (!apic_x2apic_mode(apic))
2191                 kvm_apic_set_ldr(apic, 0);
2192         kvm_lapic_set_reg(apic, APIC_ESR, 0);
2193         kvm_lapic_set_reg(apic, APIC_ICR, 0);
2194         kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2195         kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2196         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2197         for (i = 0; i < 8; i++) {
2198                 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2199                 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2200                 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2201         }
2202         apic->irr_pending = vcpu->arch.apicv_active;
2203         apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
2204         apic->highest_isr_cache = -1;
2205         update_divide_count(apic);
2206         atomic_set(&apic->lapic_timer.pending, 0);
2207         if (kvm_vcpu_is_bsp(vcpu))
2208                 kvm_lapic_set_base(vcpu,
2209                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2210         vcpu->arch.pv_eoi.msr_val = 0;
2211         apic_update_ppr(apic);
2212         if (vcpu->arch.apicv_active) {
2213                 kvm_x86_ops->apicv_post_state_restore(vcpu);
2214                 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2215                 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2216         }
2217
2218         vcpu->arch.apic_arb_prio = 0;
2219         vcpu->arch.apic_attention = 0;
2220
2221         apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
2222                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
2223                    vcpu, kvm_lapic_get_reg(apic, APIC_ID),
2224                    vcpu->arch.apic_base, apic->base_address);
2225 }
2226
2227 /*
2228  *----------------------------------------------------------------------
2229  * timer interface
2230  *----------------------------------------------------------------------
2231  */
2232
2233 static bool lapic_is_periodic(struct kvm_lapic *apic)
2234 {
2235         return apic_lvtt_period(apic);
2236 }
2237
2238 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2239 {
2240         struct kvm_lapic *apic = vcpu->arch.apic;
2241
2242         if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2243                 return atomic_read(&apic->lapic_timer.pending);
2244
2245         return 0;
2246 }
2247
2248 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2249 {
2250         u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2251         int vector, mode, trig_mode;
2252
2253         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2254                 vector = reg & APIC_VECTOR_MASK;
2255                 mode = reg & APIC_MODE_MASK;
2256                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2257                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2258                                         NULL);
2259         }
2260         return 0;
2261 }
2262
2263 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2264 {
2265         struct kvm_lapic *apic = vcpu->arch.apic;
2266
2267         if (apic)
2268                 kvm_apic_local_deliver(apic, APIC_LVT0);
2269 }
2270
2271 static const struct kvm_io_device_ops apic_mmio_ops = {
2272         .read     = apic_mmio_read,
2273         .write    = apic_mmio_write,
2274 };
2275
2276 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2277 {
2278         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2279         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2280
2281         apic_timer_expired(apic);
2282
2283         if (lapic_is_periodic(apic)) {
2284                 advance_periodic_target_expiration(apic);
2285                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2286                 return HRTIMER_RESTART;
2287         } else
2288                 return HRTIMER_NORESTART;
2289 }
2290
2291 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns)
2292 {
2293         struct kvm_lapic *apic;
2294
2295         ASSERT(vcpu != NULL);
2296         apic_debug("apic_init %d\n", vcpu->vcpu_id);
2297
2298         apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT);
2299         if (!apic)
2300                 goto nomem;
2301
2302         vcpu->arch.apic = apic;
2303
2304         apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
2305         if (!apic->regs) {
2306                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2307                        vcpu->vcpu_id);
2308                 goto nomem_free_apic;
2309         }
2310         apic->vcpu = vcpu;
2311
2312         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2313                      HRTIMER_MODE_ABS_PINNED);
2314         apic->lapic_timer.timer.function = apic_timer_fn;
2315         if (timer_advance_ns == -1) {
2316                 apic->lapic_timer.timer_advance_ns = 1000;
2317                 apic->lapic_timer.timer_advance_adjust_done = false;
2318         } else {
2319                 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
2320                 apic->lapic_timer.timer_advance_adjust_done = true;
2321         }
2322
2323
2324         /*
2325          * APIC is created enabled. This will prevent kvm_lapic_set_base from
2326          * thinking that APIC satet has changed.
2327          */
2328         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2329         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2330         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2331
2332         return 0;
2333 nomem_free_apic:
2334         kfree(apic);
2335 nomem:
2336         return -ENOMEM;
2337 }
2338
2339 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2340 {
2341         struct kvm_lapic *apic = vcpu->arch.apic;
2342         u32 ppr;
2343
2344         if (!apic_enabled(apic))
2345                 return -1;
2346
2347         __apic_update_ppr(apic, &ppr);
2348         return apic_has_interrupt_for_ppr(apic, ppr);
2349 }
2350
2351 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2352 {
2353         u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2354         int r = 0;
2355
2356         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2357                 r = 1;
2358         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2359             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2360                 r = 1;
2361         return r;
2362 }
2363
2364 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2365 {
2366         struct kvm_lapic *apic = vcpu->arch.apic;
2367
2368         if (atomic_read(&apic->lapic_timer.pending) > 0) {
2369                 kvm_apic_local_deliver(apic, APIC_LVTT);
2370                 if (apic_lvtt_tscdeadline(apic))
2371                         apic->lapic_timer.tscdeadline = 0;
2372                 if (apic_lvtt_oneshot(apic)) {
2373                         apic->lapic_timer.tscdeadline = 0;
2374                         apic->lapic_timer.target_expiration = 0;
2375                 }
2376                 atomic_set(&apic->lapic_timer.pending, 0);
2377         }
2378 }
2379
2380 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2381 {
2382         int vector = kvm_apic_has_interrupt(vcpu);
2383         struct kvm_lapic *apic = vcpu->arch.apic;
2384         u32 ppr;
2385
2386         if (vector == -1)
2387                 return -1;
2388
2389         /*
2390          * We get here even with APIC virtualization enabled, if doing
2391          * nested virtualization and L1 runs with the "acknowledge interrupt
2392          * on exit" mode.  Then we cannot inject the interrupt via RVI,
2393          * because the process would deliver it through the IDT.
2394          */
2395
2396         apic_clear_irr(vector, apic);
2397         if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2398                 /*
2399                  * For auto-EOI interrupts, there might be another pending
2400                  * interrupt above PPR, so check whether to raise another
2401                  * KVM_REQ_EVENT.
2402                  */
2403                 apic_update_ppr(apic);
2404         } else {
2405                 /*
2406                  * For normal interrupts, PPR has been raised and there cannot
2407                  * be a higher-priority pending interrupt---except if there was
2408                  * a concurrent interrupt injection, but that would have
2409                  * triggered KVM_REQ_EVENT already.
2410                  */
2411                 apic_set_isr(vector, apic);
2412                 __apic_update_ppr(apic, &ppr);
2413         }
2414
2415         return vector;
2416 }
2417
2418 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2419                 struct kvm_lapic_state *s, bool set)
2420 {
2421         if (apic_x2apic_mode(vcpu->arch.apic)) {
2422                 u32 *id = (u32 *)(s->regs + APIC_ID);
2423                 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2424
2425                 if (vcpu->kvm->arch.x2apic_format) {
2426                         if (*id != vcpu->vcpu_id)
2427                                 return -EINVAL;
2428                 } else {
2429                         if (set)
2430                                 *id >>= 24;
2431                         else
2432                                 *id <<= 24;
2433                 }
2434
2435                 /* In x2APIC mode, the LDR is fixed and based on the id */
2436                 if (set)
2437                         *ldr = kvm_apic_calc_x2apic_ldr(*id);
2438         }
2439
2440         return 0;
2441 }
2442
2443 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2444 {
2445         memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2446         return kvm_apic_state_fixup(vcpu, s, false);
2447 }
2448
2449 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2450 {
2451         struct kvm_lapic *apic = vcpu->arch.apic;
2452         int r;
2453
2454
2455         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2456         /* set SPIV separately to get count of SW disabled APICs right */
2457         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2458
2459         r = kvm_apic_state_fixup(vcpu, s, true);
2460         if (r)
2461                 return r;
2462         memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
2463
2464         recalculate_apic_map(vcpu->kvm);
2465         kvm_apic_set_version(vcpu);
2466
2467         apic_update_ppr(apic);
2468         hrtimer_cancel(&apic->lapic_timer.timer);
2469         apic_update_lvtt(apic);
2470         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2471         update_divide_count(apic);
2472         start_apic_timer(apic);
2473         apic->irr_pending = true;
2474         apic->isr_count = vcpu->arch.apicv_active ?
2475                                 1 : count_vectors(apic->regs + APIC_ISR);
2476         apic->highest_isr_cache = -1;
2477         if (vcpu->arch.apicv_active) {
2478                 kvm_x86_ops->apicv_post_state_restore(vcpu);
2479                 kvm_x86_ops->hwapic_irr_update(vcpu,
2480                                 apic_find_highest_irr(apic));
2481                 kvm_x86_ops->hwapic_isr_update(vcpu,
2482                                 apic_find_highest_isr(apic));
2483         }
2484         kvm_make_request(KVM_REQ_EVENT, vcpu);
2485         if (ioapic_in_kernel(vcpu->kvm))
2486                 kvm_rtc_eoi_tracking_restore_one(vcpu);
2487
2488         vcpu->arch.apic_arb_prio = 0;
2489
2490         return 0;
2491 }
2492
2493 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2494 {
2495         struct hrtimer *timer;
2496
2497         if (!lapic_in_kernel(vcpu))
2498                 return;
2499
2500         timer = &vcpu->arch.apic->lapic_timer.timer;
2501         if (hrtimer_cancel(timer))
2502                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2503 }
2504
2505 /*
2506  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2507  *
2508  * Detect whether guest triggered PV EOI since the
2509  * last entry. If yes, set EOI on guests's behalf.
2510  * Clear PV EOI in guest memory in any case.
2511  */
2512 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2513                                         struct kvm_lapic *apic)
2514 {
2515         bool pending;
2516         int vector;
2517         /*
2518          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2519          * and KVM_PV_EOI_ENABLED in guest memory as follows:
2520          *
2521          * KVM_APIC_PV_EOI_PENDING is unset:
2522          *      -> host disabled PV EOI.
2523          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2524          *      -> host enabled PV EOI, guest did not execute EOI yet.
2525          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2526          *      -> host enabled PV EOI, guest executed EOI.
2527          */
2528         BUG_ON(!pv_eoi_enabled(vcpu));
2529         pending = pv_eoi_get_pending(vcpu);
2530         /*
2531          * Clear pending bit in any case: it will be set again on vmentry.
2532          * While this might not be ideal from performance point of view,
2533          * this makes sure pv eoi is only enabled when we know it's safe.
2534          */
2535         pv_eoi_clr_pending(vcpu);
2536         if (pending)
2537                 return;
2538         vector = apic_set_eoi(apic);
2539         trace_kvm_pv_eoi(apic, vector);
2540 }
2541
2542 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2543 {
2544         u32 data;
2545
2546         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2547                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2548
2549         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2550                 return;
2551
2552         if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2553                                   sizeof(u32)))
2554                 return;
2555
2556         apic_set_tpr(vcpu->arch.apic, data & 0xff);
2557 }
2558
2559 /*
2560  * apic_sync_pv_eoi_to_guest - called before vmentry
2561  *
2562  * Detect whether it's safe to enable PV EOI and
2563  * if yes do so.
2564  */
2565 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2566                                         struct kvm_lapic *apic)
2567 {
2568         if (!pv_eoi_enabled(vcpu) ||
2569             /* IRR set or many bits in ISR: could be nested. */
2570             apic->irr_pending ||
2571             /* Cache not set: could be safe but we don't bother. */
2572             apic->highest_isr_cache == -1 ||
2573             /* Need EOI to update ioapic. */
2574             kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2575                 /*
2576                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2577                  * so we need not do anything here.
2578                  */
2579                 return;
2580         }
2581
2582         pv_eoi_set_pending(apic->vcpu);
2583 }
2584
2585 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2586 {
2587         u32 data, tpr;
2588         int max_irr, max_isr;
2589         struct kvm_lapic *apic = vcpu->arch.apic;
2590
2591         apic_sync_pv_eoi_to_guest(vcpu, apic);
2592
2593         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2594                 return;
2595
2596         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2597         max_irr = apic_find_highest_irr(apic);
2598         if (max_irr < 0)
2599                 max_irr = 0;
2600         max_isr = apic_find_highest_isr(apic);
2601         if (max_isr < 0)
2602                 max_isr = 0;
2603         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2604
2605         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2606                                 sizeof(u32));
2607 }
2608
2609 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2610 {
2611         if (vapic_addr) {
2612                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2613                                         &vcpu->arch.apic->vapic_cache,
2614                                         vapic_addr, sizeof(u32)))
2615                         return -EINVAL;
2616                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2617         } else {
2618                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2619         }
2620
2621         vcpu->arch.apic->vapic_addr = vapic_addr;
2622         return 0;
2623 }
2624
2625 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2626 {
2627         struct kvm_lapic *apic = vcpu->arch.apic;
2628         u32 reg = (msr - APIC_BASE_MSR) << 4;
2629
2630         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2631                 return 1;
2632
2633         if (reg == APIC_ICR2)
2634                 return 1;
2635
2636         /* if this is ICR write vector before command */
2637         if (reg == APIC_ICR)
2638                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2639         return kvm_lapic_reg_write(apic, reg, (u32)data);
2640 }
2641
2642 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2643 {
2644         struct kvm_lapic *apic = vcpu->arch.apic;
2645         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2646
2647         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2648                 return 1;
2649
2650         if (reg == APIC_DFR || reg == APIC_ICR2) {
2651                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2652                            reg);
2653                 return 1;
2654         }
2655
2656         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2657                 return 1;
2658         if (reg == APIC_ICR)
2659                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2660
2661         *data = (((u64)high) << 32) | low;
2662
2663         return 0;
2664 }
2665
2666 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2667 {
2668         struct kvm_lapic *apic = vcpu->arch.apic;
2669
2670         if (!lapic_in_kernel(vcpu))
2671                 return 1;
2672
2673         /* if this is ICR write vector before command */
2674         if (reg == APIC_ICR)
2675                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2676         return kvm_lapic_reg_write(apic, reg, (u32)data);
2677 }
2678
2679 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2680 {
2681         struct kvm_lapic *apic = vcpu->arch.apic;
2682         u32 low, high = 0;
2683
2684         if (!lapic_in_kernel(vcpu))
2685                 return 1;
2686
2687         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2688                 return 1;
2689         if (reg == APIC_ICR)
2690                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2691
2692         *data = (((u64)high) << 32) | low;
2693
2694         return 0;
2695 }
2696
2697 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
2698 {
2699         u64 addr = data & ~KVM_MSR_ENABLED;
2700         struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2701         unsigned long new_len;
2702
2703         if (!IS_ALIGNED(addr, 4))
2704                 return 1;
2705
2706         vcpu->arch.pv_eoi.msr_val = data;
2707         if (!pv_eoi_enabled(vcpu))
2708                 return 0;
2709
2710         if (addr == ghc->gpa && len <= ghc->len)
2711                 new_len = ghc->len;
2712         else
2713                 new_len = len;
2714
2715         return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
2716 }
2717
2718 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2719 {
2720         struct kvm_lapic *apic = vcpu->arch.apic;
2721         u8 sipi_vector;
2722         unsigned long pe;
2723
2724         if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2725                 return;
2726
2727         /*
2728          * INITs are latched while in SMM.  Because an SMM CPU cannot
2729          * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2730          * and delay processing of INIT until the next RSM.
2731          */
2732         if (is_smm(vcpu)) {
2733                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2734                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2735                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2736                 return;
2737         }
2738
2739         pe = xchg(&apic->pending_events, 0);
2740         if (test_bit(KVM_APIC_INIT, &pe)) {
2741                 kvm_vcpu_reset(vcpu, true);
2742                 if (kvm_vcpu_is_bsp(apic->vcpu))
2743                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2744                 else
2745                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2746         }
2747         if (test_bit(KVM_APIC_SIPI, &pe) &&
2748             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2749                 /* evaluate pending_events before reading the vector */
2750                 smp_rmb();
2751                 sipi_vector = apic->sipi_vector;
2752                 apic_debug("vcpu %d received sipi with vector # %x\n",
2753                          vcpu->vcpu_id, sipi_vector);
2754                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2755                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2756         }
2757 }
2758
2759 void kvm_lapic_init(void)
2760 {
2761         /* do not patch jump label more than once per second */
2762         jump_label_rate_limit(&apic_hw_disabled, HZ);
2763         jump_label_rate_limit(&apic_sw_disabled, HZ);
2764 }
2765
2766 void kvm_lapic_exit(void)
2767 {
2768         static_key_deferred_flush(&apic_hw_disabled);
2769         static_key_deferred_flush(&apic_sw_disabled);
2770 }