2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
5 * Pentium III FXSR, SSE support
6 * Gareth Hughes <gareth@valinux.com>, May 2000
10 * Handle hardware traps and faults.
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/context_tracking.h>
16 #include <linux/interrupt.h>
17 #include <linux/kallsyms.h>
18 #include <linux/spinlock.h>
19 #include <linux/kprobes.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kgdb.h>
23 #include <linux/kernel.h>
24 #include <linux/export.h>
25 #include <linux/ptrace.h>
26 #include <linux/uprobes.h>
27 #include <linux/string.h>
28 #include <linux/delay.h>
29 #include <linux/errno.h>
30 #include <linux/kexec.h>
31 #include <linux/sched.h>
32 #include <linux/sched/task_stack.h>
33 #include <linux/timer.h>
34 #include <linux/init.h>
35 #include <linux/bug.h>
36 #include <linux/nmi.h>
38 #include <linux/smp.h>
40 #include <linux/hardirq.h>
41 #include <linux/atomic.h>
43 #include <asm/stacktrace.h>
44 #include <asm/processor.h>
45 #include <asm/debugreg.h>
46 #include <asm/text-patching.h>
47 #include <asm/ftrace.h>
48 #include <asm/traps.h>
50 #include <asm/fpu/internal.h>
52 #include <asm/cpu_entry_area.h>
54 #include <asm/fixmap.h>
55 #include <asm/mach_traps.h>
56 #include <asm/alternative.h>
57 #include <asm/fpu/xstate.h>
61 #include <asm/insn-eval.h>
64 #include <asm/x86_init.h>
65 #include <asm/pgalloc.h>
66 #include <asm/proto.h>
68 #include <asm/processor-flags.h>
69 #include <asm/setup.h>
70 #include <asm/proto.h>
73 DECLARE_BITMAP(system_vectors, NR_VECTORS);
75 static inline void cond_local_irq_enable(struct pt_regs *regs)
77 if (regs->flags & X86_EFLAGS_IF)
81 static inline void cond_local_irq_disable(struct pt_regs *regs)
83 if (regs->flags & X86_EFLAGS_IF)
87 int is_valid_bugaddr(unsigned long addr)
91 if (addr < TASK_SIZE_MAX)
94 if (probe_kernel_address((unsigned short *)addr, ud))
97 return ud == INSN_UD0 || ud == INSN_UD2;
100 int fixup_bug(struct pt_regs *regs, int trapnr)
102 if (trapnr != X86_TRAP_UD)
105 switch (report_bug(regs->ip, regs)) {
106 case BUG_TRAP_TYPE_NONE:
107 case BUG_TRAP_TYPE_BUG:
110 case BUG_TRAP_TYPE_WARN:
118 static nokprobe_inline int
119 do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str,
120 struct pt_regs *regs, long error_code)
122 if (v8086_mode(regs)) {
124 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
125 * On nmi (interrupt 2), do_trap should not be called.
127 if (trapnr < X86_TRAP_UD) {
128 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
132 } else if (!user_mode(regs)) {
133 if (fixup_exception(regs, trapnr, error_code, 0))
136 tsk->thread.error_code = error_code;
137 tsk->thread.trap_nr = trapnr;
138 die(str, regs, error_code);
142 * We want error_code and trap_nr set for userspace faults and
143 * kernelspace faults which result in die(), but not
144 * kernelspace faults which are fixed up. die() gives the
145 * process no chance to handle the signal and notice the
146 * kernel fault information, so that won't result in polluting
147 * the information about previously queued, but not yet
148 * delivered, faults. See also exc_general_protection below.
150 tsk->thread.error_code = error_code;
151 tsk->thread.trap_nr = trapnr;
156 static void show_signal(struct task_struct *tsk, int signr,
157 const char *type, const char *desc,
158 struct pt_regs *regs, long error_code)
160 if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
161 printk_ratelimit()) {
162 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx",
163 tsk->comm, task_pid_nr(tsk), type, desc,
164 regs->ip, regs->sp, error_code);
165 print_vma_addr(KERN_CONT " in ", regs->ip);
171 do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
172 long error_code, int sicode, void __user *addr)
174 struct task_struct *tsk = current;
176 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
179 show_signal(tsk, signr, "trap ", str, regs, error_code);
184 force_sig_fault(signr, sicode, addr);
186 NOKPROBE_SYMBOL(do_trap);
188 static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
189 unsigned long trapnr, int signr, int sicode, void __user *addr)
191 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
194 * WARN*()s end up here; fix them up before we call the
197 if (!user_mode(regs) && fixup_bug(regs, trapnr))
200 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
202 cond_local_irq_enable(regs);
203 do_trap(trapnr, signr, str, regs, error_code, sicode, addr);
204 cond_local_irq_disable(regs);
209 * Posix requires to provide the address of the faulting instruction for
210 * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t.
212 * This address is usually regs->ip, but when an uprobe moved the code out
213 * of line then regs->ip points to the XOL code which would confuse
214 * anything which analyzes the fault address vs. the unmodified binary. If
215 * a trap happened in XOL code then uprobe maps regs->ip back to the
216 * original instruction address.
218 static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs)
220 return (void __user *)uprobe_get_trap_addr(regs);
223 DEFINE_IDTENTRY(exc_divide_error)
225 do_error_trap(regs, 0, "divide_error", X86_TRAP_DE, SIGFPE,
226 FPE_INTDIV, error_get_trap_addr(regs));
229 DEFINE_IDTENTRY(exc_overflow)
231 do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL);
234 #ifdef CONFIG_X86_F00F_BUG
235 void handle_invalid_op(struct pt_regs *regs)
237 static inline void handle_invalid_op(struct pt_regs *regs)
240 do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL,
241 ILL_ILLOPN, error_get_trap_addr(regs));
244 DEFINE_IDTENTRY(exc_invalid_op)
246 handle_invalid_op(regs);
249 DEFINE_IDTENTRY(exc_coproc_segment_overrun)
251 do_error_trap(regs, 0, "coprocessor segment overrun",
252 X86_TRAP_OLD_MF, SIGFPE, 0, NULL);
255 DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss)
257 do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV,
261 DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present)
263 do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP,
267 DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment)
269 do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS,
273 DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check)
275 char *str = "alignment check";
277 if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP)
280 if (!user_mode(regs))
281 die("Split lock detected\n", regs, error_code);
285 if (handle_user_split_lock(regs, error_code))
288 do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs,
289 error_code, BUS_ADRALN, NULL);
292 #ifdef CONFIG_VMAP_STACK
293 __visible void __noreturn handle_stack_overflow(const char *message,
294 struct pt_regs *regs,
295 unsigned long fault_address)
297 printk(KERN_EMERG "BUG: stack guard page was hit at %p (stack is %p..%p)\n",
298 (void *)fault_address, current->stack,
299 (char *)current->stack + THREAD_SIZE - 1);
300 die(message, regs, 0);
302 /* Be absolutely certain we don't return. */
303 panic("%s", message);
308 * Runs on an IST stack for x86_64 and on a special task stack for x86_32.
310 * On x86_64, this is more or less a normal kernel entry. Notwithstanding the
311 * SDM's warnings about double faults being unrecoverable, returning works as
312 * expected. Presumably what the SDM actually means is that the CPU may get
313 * the register state wrong on entry, so returning could be a bad idea.
315 * Various CPU engineers have promised that double faults due to an IRET fault
316 * while the stack is read-only are, in fact, recoverable.
318 * On x86_32, this is entered through a task gate, and regs are synthesized
319 * from the TSS. Returning is, in principle, okay, but changes to regs will
320 * be lost. If, for some reason, we need to return to a context with modified
321 * regs, the shim code could be adjusted to synchronize the registers.
323 dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code, unsigned long cr2)
325 static const char str[] = "double fault";
326 struct task_struct *tsk = current;
328 #ifdef CONFIG_X86_ESPFIX64
329 extern unsigned char native_irq_return_iret[];
332 * If IRET takes a non-IST fault on the espfix64 stack, then we
333 * end up promoting it to a doublefault. In that case, take
334 * advantage of the fact that we're not using the normal (TSS.sp0)
335 * stack right now. We can write a fake #GP(0) frame at TSS.sp0
336 * and then modify our own IRET frame so that, when we return,
337 * we land directly at the #GP(0) vector with the stack already
338 * set up according to its expectations.
340 * The net result is that our #GP handler will think that we
341 * entered from usermode with the bad user context.
343 * No need for nmi_enter() here because we don't use RCU.
345 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY &&
346 regs->cs == __KERNEL_CS &&
347 regs->ip == (unsigned long)native_irq_return_iret)
349 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
350 unsigned long *p = (unsigned long *)regs->sp;
353 * regs->sp points to the failing IRET frame on the
354 * ESPFIX64 stack. Copy it to the entry stack. This fills
355 * in gpregs->ss through gpregs->ip.
360 gpregs->flags = p[2];
363 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */
366 * Adjust our frame so that we return straight to the #GP
367 * vector with the expected RSP value. This is safe because
368 * we won't enable interupts or schedule before we invoke
369 * general_protection, so nothing will clobber the stack
370 * frame we just set up.
372 * We will enter general_protection with kernel GSBASE,
373 * which is what the stub expects, given that the faulting
374 * RIP will be the IRET instruction.
376 regs->ip = (unsigned long)asm_exc_general_protection;
377 regs->sp = (unsigned long)&gpregs->orig_ax;
384 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
386 tsk->thread.error_code = error_code;
387 tsk->thread.trap_nr = X86_TRAP_DF;
389 #ifdef CONFIG_VMAP_STACK
391 * If we overflow the stack into a guard page, the CPU will fail
392 * to deliver #PF and will send #DF instead. Similarly, if we
393 * take any non-IST exception while too close to the bottom of
394 * the stack, the processor will get a page fault while
395 * delivering the exception and will generate a double fault.
397 * According to the SDM (footnote in 6.15 under "Interrupt 14 -
398 * Page-Fault Exception (#PF):
400 * Processors update CR2 whenever a page fault is detected. If a
401 * second page fault occurs while an earlier page fault is being
402 * delivered, the faulting linear address of the second fault will
403 * overwrite the contents of CR2 (replacing the previous
404 * address). These updates to CR2 occur even if the page fault
405 * results in a double fault or occurs during the delivery of a
408 * The logic below has a small possibility of incorrectly diagnosing
409 * some errors as stack overflows. For example, if the IDT or GDT
410 * gets corrupted such that #GP delivery fails due to a bad descriptor
411 * causing #GP and we hit this condition while CR2 coincidentally
412 * points to the stack guard page, we'll think we overflowed the
413 * stack. Given that we're going to panic one way or another
414 * if this happens, this isn't necessarily worth fixing.
416 * If necessary, we could improve the test by only diagnosing
417 * a stack overflow if the saved RSP points within 47 bytes of
418 * the bottom of the stack: if RSP == tsk_stack + 48 and we
419 * take an exception, the stack is already aligned and there
420 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a
421 * possible error code, so a stack overflow would *not* double
422 * fault. With any less space left, exception delivery could
423 * fail, and, as a practical matter, we've overflowed the
424 * stack even if the actual trigger for the double fault was
427 if ((unsigned long)task_stack_page(tsk) - 1 - cr2 < PAGE_SIZE)
428 handle_stack_overflow("kernel stack overflow (double-fault)", regs, cr2);
431 pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code);
432 die("double fault", regs, error_code);
433 panic("Machine halted.");
436 DEFINE_IDTENTRY(exc_bounds)
438 if (notify_die(DIE_TRAP, "bounds", regs, 0,
439 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
441 cond_local_irq_enable(regs);
443 if (!user_mode(regs))
444 die("bounds", regs, 0);
446 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL);
448 cond_local_irq_disable(regs);
451 enum kernel_gp_hint {
458 * When an uncaught #GP occurs, try to determine the memory address accessed by
459 * the instruction and return that address to the caller. Also, try to figure
460 * out whether any part of the access to that address was non-canonical.
462 static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs,
465 u8 insn_buf[MAX_INSN_SIZE];
468 if (probe_kernel_read(insn_buf, (void *)regs->ip, MAX_INSN_SIZE))
471 kernel_insn_init(&insn, insn_buf, MAX_INSN_SIZE);
472 insn_get_modrm(&insn);
475 *addr = (unsigned long)insn_get_addr_ref(&insn, regs);
482 * - the operand is not in the kernel half
483 * - the last byte of the operand is not in the user canonical half
485 if (*addr < ~__VIRTUAL_MASK &&
486 *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK)
487 return GP_NON_CANONICAL;
493 #define GPFSTR "general protection fault"
495 DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)
497 char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR;
498 enum kernel_gp_hint hint = GP_NO_HINT;
499 struct task_struct *tsk;
500 unsigned long gp_addr;
503 cond_local_irq_enable(regs);
505 if (static_cpu_has(X86_FEATURE_UMIP)) {
506 if (user_mode(regs) && fixup_umip_exception(regs))
510 if (v8086_mode(regs)) {
512 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
519 if (user_mode(regs)) {
520 tsk->thread.error_code = error_code;
521 tsk->thread.trap_nr = X86_TRAP_GP;
523 show_signal(tsk, SIGSEGV, "", desc, regs, error_code);
528 if (fixup_exception(regs, X86_TRAP_GP, error_code, 0))
531 tsk->thread.error_code = error_code;
532 tsk->thread.trap_nr = X86_TRAP_GP;
535 * To be potentially processing a kprobe fault and to trust the result
536 * from kprobe_running(), we have to be non-preemptible.
538 if (!preemptible() &&
540 kprobe_fault_handler(regs, X86_TRAP_GP))
543 ret = notify_die(DIE_GPF, desc, regs, error_code, X86_TRAP_GP, SIGSEGV);
544 if (ret == NOTIFY_STOP)
548 snprintf(desc, sizeof(desc), "segment-related " GPFSTR);
550 hint = get_kernel_gp_address(regs, &gp_addr);
552 if (hint != GP_NO_HINT)
553 snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx",
554 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address"
555 : "maybe for address",
559 * KASAN is interested only in the non-canonical case, clear it
562 if (hint != GP_NON_CANONICAL)
565 die_addr(desc, regs, error_code, gp_addr);
568 cond_local_irq_disable(regs);
571 dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
574 * poke_int3_handler() is completely self contained code; it does (and
575 * must) *NOT* call out to anything, lest it hits upon yet another
578 if (poke_int3_handler(regs))
582 * Unlike any other non-IST entry, we can be called from pretty much
583 * any location in the kernel through kprobes -- text_poke() will most
584 * likely be handled by poke_int3_handler() above. This means this
585 * handler is effectively NMI-like.
587 if (!user_mode(regs))
590 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
591 if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
592 SIGTRAP) == NOTIFY_STOP)
594 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
596 #ifdef CONFIG_KPROBES
597 if (kprobe_int3_handler(regs))
601 if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
602 SIGTRAP) == NOTIFY_STOP)
605 cond_local_irq_enable(regs);
606 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, 0, NULL);
607 cond_local_irq_disable(regs);
610 if (!user_mode(regs))
613 NOKPROBE_SYMBOL(do_int3);
617 * Help handler running on a per-cpu (IST or entry trampoline) stack
618 * to switch to the normal thread stack if the interrupted code was in
619 * user mode. The actual stack switch is done in entry_64.S
621 asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs)
623 struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1;
629 struct bad_iret_stack {
630 void *error_entry_ret;
634 asmlinkage __visible noinstr
635 struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
638 * This is called from entry_64.S early in handling a fault
639 * caused by a bad iret to user mode. To handle the fault
640 * correctly, we want to move our stack frame to where it would
641 * be had we entered directly on the entry stack (rather than
642 * just below the IRET frame) and we want to pretend that the
643 * exception came from the IRET target.
645 struct bad_iret_stack tmp, *new_stack =
646 (struct bad_iret_stack *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
648 /* Copy the IRET target to the temporary storage. */
649 memcpy(&tmp.regs.ip, (void *)s->regs.sp, 5*8);
651 /* Copy the remainder of the stack from the current stack. */
652 memcpy(&tmp, s, offsetof(struct bad_iret_stack, regs.ip));
654 /* Update the entry stack */
655 memcpy(new_stack, &tmp, sizeof(tmp));
657 BUG_ON(!user_mode(&new_stack->regs));
662 static bool is_sysenter_singlestep(struct pt_regs *regs)
665 * We don't try for precision here. If we're anywhere in the region of
666 * code that can be single-stepped in the SYSENTER entry path, then
667 * assume that this is a useless single-step trap due to SYSENTER
668 * being invoked with TF set. (We don't know in advance exactly
669 * which instructions will be hit because BTF could plausibly
673 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) <
674 (unsigned long)__end_SYSENTER_singlestep_region -
675 (unsigned long)__begin_SYSENTER_singlestep_region;
676 #elif defined(CONFIG_IA32_EMULATION)
677 return (regs->ip - (unsigned long)entry_SYSENTER_compat) <
678 (unsigned long)__end_entry_SYSENTER_compat -
679 (unsigned long)entry_SYSENTER_compat;
686 * Our handling of the processor debug registers is non-trivial.
687 * We do not clear them on entry and exit from the kernel. Therefore
688 * it is possible to get a watchpoint trap here from inside the kernel.
689 * However, the code in ./ptrace.c has ensured that the user can
690 * only set watchpoints on userspace addresses. Therefore the in-kernel
691 * watchpoint trap can only occur in code which is reading/writing
692 * from user space. Such code must not hold kernel locks (since it
693 * can equally take a page fault), therefore it is safe to call
694 * force_sig_info even though that claims and releases locks.
696 * Code in ./signal.c ensures that the debug control register
697 * is restored before we deliver any signal, and therefore that
698 * user code runs with the correct debug control register even though
701 * Being careful here means that we don't have to be as careful in a
702 * lot of more complicated places (task switching can be a bit lazy
703 * about restoring all the debug state, and ptrace doesn't have to
704 * find every occurrence of the TF bit that could be saved away even
707 * May run on IST stack.
709 dotraplinkage void do_debug(struct pt_regs *regs, long error_code)
711 struct task_struct *tsk = current;
718 get_debugreg(dr6, 6);
720 * The Intel SDM says:
722 * Certain debug exceptions may clear bits 0-3. The remaining
723 * contents of the DR6 register are never cleared by the
724 * processor. To avoid confusion in identifying debug
725 * exceptions, debug handlers should clear the register before
726 * returning to the interrupted task.
728 * Keep it simple: clear DR6 immediately.
732 /* Filter out all the reserved bits which are preset to 1 */
733 dr6 &= ~DR6_RESERVED;
736 * The SDM says "The processor clears the BTF flag when it
737 * generates a debug exception." Clear TIF_BLOCKSTEP to keep
738 * TIF_BLOCKSTEP in sync with the hardware BTF flag.
740 clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP);
742 if (unlikely(!user_mode(regs) && (dr6 & DR_STEP) &&
743 is_sysenter_singlestep(regs))) {
748 * else we might have gotten a single-step trap and hit a
749 * watchpoint at the same time, in which case we should fall
750 * through and handle the watchpoint.
755 * If dr6 has no reason to give us about the origin of this trap,
756 * then it's very likely the result of an icebp/int01 trap.
757 * User wants a sigtrap for that.
759 if (!dr6 && user_mode(regs))
762 /* Store the virtualized DR6 value */
763 tsk->thread.debugreg6 = dr6;
765 #ifdef CONFIG_KPROBES
766 if (kprobe_debug_handler(regs))
770 if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code,
771 SIGTRAP) == NOTIFY_STOP)
775 * Let others (NMI) know that the debug stack is in use
776 * as we may switch to the interrupt stack.
778 debug_stack_usage_inc();
780 /* It's safe to allow irq's after DR6 has been saved */
781 cond_local_irq_enable(regs);
783 if (v8086_mode(regs)) {
784 handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code,
786 cond_local_irq_disable(regs);
787 debug_stack_usage_dec();
791 if (WARN_ON_ONCE((dr6 & DR_STEP) && !user_mode(regs))) {
793 * Historical junk that used to handle SYSENTER single-stepping.
794 * This should be unreachable now. If we survive for a while
795 * without anyone hitting this warning, we'll turn this into
798 tsk->thread.debugreg6 &= ~DR_STEP;
799 set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
800 regs->flags &= ~X86_EFLAGS_TF;
802 si_code = get_si_code(tsk->thread.debugreg6);
803 if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
804 send_sigtrap(regs, error_code, si_code);
805 cond_local_irq_disable(regs);
806 debug_stack_usage_dec();
811 NOKPROBE_SYMBOL(do_debug);
814 * Note that we play around with the 'TS' bit in an attempt to get
815 * the correct behaviour even in the presence of the asynchronous
818 static void math_error(struct pt_regs *regs, int trapnr)
820 struct task_struct *task = current;
821 struct fpu *fpu = &task->thread.fpu;
823 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
826 cond_local_irq_enable(regs);
828 if (!user_mode(regs)) {
829 if (fixup_exception(regs, trapnr, 0, 0))
832 task->thread.error_code = 0;
833 task->thread.trap_nr = trapnr;
835 if (notify_die(DIE_TRAP, str, regs, 0, trapnr,
836 SIGFPE) != NOTIFY_STOP)
842 * Save the info for the exception handler and clear the error.
846 task->thread.trap_nr = trapnr;
847 task->thread.error_code = 0;
849 si_code = fpu__exception_code(fpu, trapnr);
850 /* Retry when we get spurious exceptions: */
854 force_sig_fault(SIGFPE, si_code,
855 (void __user *)uprobe_get_trap_addr(regs));
857 cond_local_irq_disable(regs);
860 DEFINE_IDTENTRY(exc_coprocessor_error)
862 math_error(regs, X86_TRAP_MF);
865 DEFINE_IDTENTRY(exc_simd_coprocessor_error)
867 if (IS_ENABLED(CONFIG_X86_INVD_BUG)) {
868 /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */
869 if (!static_cpu_has(X86_FEATURE_XMM)) {
870 __exc_general_protection(regs, 0);
874 math_error(regs, X86_TRAP_XF);
877 DEFINE_IDTENTRY(exc_spurious_interrupt_bug)
880 * This addresses a Pentium Pro Erratum:
882 * PROBLEM: If the APIC subsystem is configured in mixed mode with
883 * Virtual Wire mode implemented through the local APIC, an
884 * interrupt vector of 0Fh (Intel reserved encoding) may be
885 * generated by the local APIC (Int 15). This vector may be
886 * generated upon receipt of a spurious interrupt (an interrupt
887 * which is removed before the system receives the INTA sequence)
888 * instead of the programmed 8259 spurious interrupt vector.
890 * IMPLICATION: The spurious interrupt vector programmed in the
891 * 8259 is normally handled by an operating system's spurious
892 * interrupt handler. However, a vector of 0Fh is unknown to some
893 * operating systems, which would crash if this erratum occurred.
895 * In theory this could be limited to 32bit, but the handler is not
896 * hurting and who knows which other CPUs suffer from this.
900 DEFINE_IDTENTRY(exc_device_not_available)
902 unsigned long cr0 = read_cr0();
904 #ifdef CONFIG_MATH_EMULATION
905 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) {
906 struct math_emu_info info = { };
908 cond_local_irq_enable(regs);
913 cond_local_irq_disable(regs);
918 /* This should not happen. */
919 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) {
920 /* Try to fix it up and carry on. */
921 write_cr0(cr0 & ~X86_CR0_TS);
924 * Something terrible happened, and we're better off trying
925 * to kill the task than getting stuck in a never-ending
926 * loop of #NM faults.
928 die("unexpected #NM exception", regs, 0);
933 DEFINE_IDTENTRY_SW(iret_error)
936 if (notify_die(DIE_TRAP, "iret exception", regs, 0,
937 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
938 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0,
939 ILL_BADSTK, (void __user *)NULL);
945 void __init trap_init(void)
947 /* Init cpu_entry_area before IST entries are set up */
948 setup_cpu_entry_areas();
953 * Set the IDT descriptor to a fixed read-only location, so that the
954 * "sidt" instruction will not leak the location of the kernel, and
955 * to defend the IDT against arbitrary memory write vulnerabilities.
956 * It will be reloaded in cpu_init() */
957 cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table),
959 idt_descr.address = CPU_ENTRY_AREA_RO_IDT;
962 * Should be a barrier for any external CPU state:
966 idt_setup_ist_traps();
968 idt_setup_debugidt_traps();