2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
5 * Pentium III FXSR, SSE support
6 * Gareth Hughes <gareth@valinux.com>, May 2000
10 * Handle hardware traps and faults.
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/context_tracking.h>
16 #include <linux/interrupt.h>
17 #include <linux/kallsyms.h>
18 #include <linux/spinlock.h>
19 #include <linux/kprobes.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kgdb.h>
23 #include <linux/kernel.h>
24 #include <linux/export.h>
25 #include <linux/ptrace.h>
26 #include <linux/uprobes.h>
27 #include <linux/string.h>
28 #include <linux/delay.h>
29 #include <linux/errno.h>
30 #include <linux/kexec.h>
31 #include <linux/sched.h>
32 #include <linux/sched/task_stack.h>
33 #include <linux/timer.h>
34 #include <linux/init.h>
35 #include <linux/bug.h>
36 #include <linux/nmi.h>
38 #include <linux/smp.h>
40 #include <linux/hardirq.h>
41 #include <linux/atomic.h>
43 #include <asm/stacktrace.h>
44 #include <asm/processor.h>
45 #include <asm/debugreg.h>
46 #include <asm/text-patching.h>
47 #include <asm/ftrace.h>
48 #include <asm/traps.h>
50 #include <asm/fpu/internal.h>
52 #include <asm/cpu_entry_area.h>
54 #include <asm/fixmap.h>
55 #include <asm/mach_traps.h>
56 #include <asm/alternative.h>
57 #include <asm/fpu/xstate.h>
61 #include <asm/insn-eval.h>
64 #include <asm/x86_init.h>
65 #include <asm/proto.h>
67 #include <asm/processor-flags.h>
68 #include <asm/setup.h>
69 #include <asm/proto.h>
72 DECLARE_BITMAP(system_vectors, NR_VECTORS);
74 static inline void cond_local_irq_enable(struct pt_regs *regs)
76 if (regs->flags & X86_EFLAGS_IF)
80 static inline void cond_local_irq_disable(struct pt_regs *regs)
82 if (regs->flags & X86_EFLAGS_IF)
86 __always_inline int is_valid_bugaddr(unsigned long addr)
88 if (addr < TASK_SIZE_MAX)
92 * We got #UD, if the text isn't readable we'd have gotten
93 * a different exception.
95 return *(unsigned short *)addr == INSN_UD2;
98 static nokprobe_inline int
99 do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str,
100 struct pt_regs *regs, long error_code)
102 if (v8086_mode(regs)) {
104 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
105 * On nmi (interrupt 2), do_trap should not be called.
107 if (trapnr < X86_TRAP_UD) {
108 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
112 } else if (!user_mode(regs)) {
113 if (fixup_exception(regs, trapnr, error_code, 0))
116 tsk->thread.error_code = error_code;
117 tsk->thread.trap_nr = trapnr;
118 die(str, regs, error_code);
122 * We want error_code and trap_nr set for userspace faults and
123 * kernelspace faults which result in die(), but not
124 * kernelspace faults which are fixed up. die() gives the
125 * process no chance to handle the signal and notice the
126 * kernel fault information, so that won't result in polluting
127 * the information about previously queued, but not yet
128 * delivered, faults. See also exc_general_protection below.
130 tsk->thread.error_code = error_code;
131 tsk->thread.trap_nr = trapnr;
136 static void show_signal(struct task_struct *tsk, int signr,
137 const char *type, const char *desc,
138 struct pt_regs *regs, long error_code)
140 if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
141 printk_ratelimit()) {
142 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx",
143 tsk->comm, task_pid_nr(tsk), type, desc,
144 regs->ip, regs->sp, error_code);
145 print_vma_addr(KERN_CONT " in ", regs->ip);
151 do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
152 long error_code, int sicode, void __user *addr)
154 struct task_struct *tsk = current;
156 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
159 show_signal(tsk, signr, "trap ", str, regs, error_code);
164 force_sig_fault(signr, sicode, addr);
166 NOKPROBE_SYMBOL(do_trap);
168 static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
169 unsigned long trapnr, int signr, int sicode, void __user *addr)
171 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
173 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
175 cond_local_irq_enable(regs);
176 do_trap(trapnr, signr, str, regs, error_code, sicode, addr);
177 cond_local_irq_disable(regs);
182 * Posix requires to provide the address of the faulting instruction for
183 * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t.
185 * This address is usually regs->ip, but when an uprobe moved the code out
186 * of line then regs->ip points to the XOL code which would confuse
187 * anything which analyzes the fault address vs. the unmodified binary. If
188 * a trap happened in XOL code then uprobe maps regs->ip back to the
189 * original instruction address.
191 static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs)
193 return (void __user *)uprobe_get_trap_addr(regs);
196 DEFINE_IDTENTRY(exc_divide_error)
198 do_error_trap(regs, 0, "divide_error", X86_TRAP_DE, SIGFPE,
199 FPE_INTDIV, error_get_trap_addr(regs));
202 DEFINE_IDTENTRY(exc_overflow)
204 do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL);
207 #ifdef CONFIG_X86_F00F_BUG
208 void handle_invalid_op(struct pt_regs *regs)
210 static inline void handle_invalid_op(struct pt_regs *regs)
213 do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL,
214 ILL_ILLOPN, error_get_trap_addr(regs));
217 static noinstr bool handle_bug(struct pt_regs *regs)
219 bool handled = false;
221 if (!is_valid_bugaddr(regs->ip))
225 * All lies, just get the WARN/BUG out.
227 instrumentation_begin();
229 * Since we're emulating a CALL with exceptions, restore the interrupt
230 * state to what it was at the exception site.
232 if (regs->flags & X86_EFLAGS_IF)
233 raw_local_irq_enable();
234 if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN) {
238 if (regs->flags & X86_EFLAGS_IF)
239 raw_local_irq_disable();
240 instrumentation_end();
245 DEFINE_IDTENTRY_RAW(exc_invalid_op)
247 irqentry_state_t state;
250 * We use UD2 as a short encoding for 'CALL __WARN', as such
251 * handle it before exception entry to avoid recursive WARN
252 * in case exception entry is the one triggering WARNs.
254 if (!user_mode(regs) && handle_bug(regs))
257 state = irqentry_enter(regs);
258 instrumentation_begin();
259 handle_invalid_op(regs);
260 instrumentation_end();
261 irqentry_exit(regs, state);
264 DEFINE_IDTENTRY(exc_coproc_segment_overrun)
266 do_error_trap(regs, 0, "coprocessor segment overrun",
267 X86_TRAP_OLD_MF, SIGFPE, 0, NULL);
270 DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss)
272 do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV,
276 DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present)
278 do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP,
282 DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment)
284 do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS,
288 DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check)
290 char *str = "alignment check";
292 if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP)
295 if (!user_mode(regs))
296 die("Split lock detected\n", regs, error_code);
300 if (handle_user_split_lock(regs, error_code))
303 do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs,
304 error_code, BUS_ADRALN, NULL);
309 #ifdef CONFIG_VMAP_STACK
310 __visible void __noreturn handle_stack_overflow(const char *message,
311 struct pt_regs *regs,
312 unsigned long fault_address)
314 printk(KERN_EMERG "BUG: stack guard page was hit at %p (stack is %p..%p)\n",
315 (void *)fault_address, current->stack,
316 (char *)current->stack + THREAD_SIZE - 1);
317 die(message, regs, 0);
319 /* Be absolutely certain we don't return. */
320 panic("%s", message);
325 * Runs on an IST stack for x86_64 and on a special task stack for x86_32.
327 * On x86_64, this is more or less a normal kernel entry. Notwithstanding the
328 * SDM's warnings about double faults being unrecoverable, returning works as
329 * expected. Presumably what the SDM actually means is that the CPU may get
330 * the register state wrong on entry, so returning could be a bad idea.
332 * Various CPU engineers have promised that double faults due to an IRET fault
333 * while the stack is read-only are, in fact, recoverable.
335 * On x86_32, this is entered through a task gate, and regs are synthesized
336 * from the TSS. Returning is, in principle, okay, but changes to regs will
337 * be lost. If, for some reason, we need to return to a context with modified
338 * regs, the shim code could be adjusted to synchronize the registers.
340 * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs
341 * to be read before doing anything else.
343 DEFINE_IDTENTRY_DF(exc_double_fault)
345 static const char str[] = "double fault";
346 struct task_struct *tsk = current;
348 #ifdef CONFIG_VMAP_STACK
349 unsigned long address = read_cr2();
352 #ifdef CONFIG_X86_ESPFIX64
353 extern unsigned char native_irq_return_iret[];
356 * If IRET takes a non-IST fault on the espfix64 stack, then we
357 * end up promoting it to a doublefault. In that case, take
358 * advantage of the fact that we're not using the normal (TSS.sp0)
359 * stack right now. We can write a fake #GP(0) frame at TSS.sp0
360 * and then modify our own IRET frame so that, when we return,
361 * we land directly at the #GP(0) vector with the stack already
362 * set up according to its expectations.
364 * The net result is that our #GP handler will think that we
365 * entered from usermode with the bad user context.
367 * No need for nmi_enter() here because we don't use RCU.
369 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY &&
370 regs->cs == __KERNEL_CS &&
371 regs->ip == (unsigned long)native_irq_return_iret)
373 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
374 unsigned long *p = (unsigned long *)regs->sp;
377 * regs->sp points to the failing IRET frame on the
378 * ESPFIX64 stack. Copy it to the entry stack. This fills
379 * in gpregs->ss through gpregs->ip.
384 gpregs->flags = p[2];
387 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */
390 * Adjust our frame so that we return straight to the #GP
391 * vector with the expected RSP value. This is safe because
392 * we won't enable interupts or schedule before we invoke
393 * general_protection, so nothing will clobber the stack
394 * frame we just set up.
396 * We will enter general_protection with kernel GSBASE,
397 * which is what the stub expects, given that the faulting
398 * RIP will be the IRET instruction.
400 regs->ip = (unsigned long)asm_exc_general_protection;
401 regs->sp = (unsigned long)&gpregs->orig_ax;
407 idtentry_enter_nmi(regs);
408 instrumentation_begin();
409 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
411 tsk->thread.error_code = error_code;
412 tsk->thread.trap_nr = X86_TRAP_DF;
414 #ifdef CONFIG_VMAP_STACK
416 * If we overflow the stack into a guard page, the CPU will fail
417 * to deliver #PF and will send #DF instead. Similarly, if we
418 * take any non-IST exception while too close to the bottom of
419 * the stack, the processor will get a page fault while
420 * delivering the exception and will generate a double fault.
422 * According to the SDM (footnote in 6.15 under "Interrupt 14 -
423 * Page-Fault Exception (#PF):
425 * Processors update CR2 whenever a page fault is detected. If a
426 * second page fault occurs while an earlier page fault is being
427 * delivered, the faulting linear address of the second fault will
428 * overwrite the contents of CR2 (replacing the previous
429 * address). These updates to CR2 occur even if the page fault
430 * results in a double fault or occurs during the delivery of a
433 * The logic below has a small possibility of incorrectly diagnosing
434 * some errors as stack overflows. For example, if the IDT or GDT
435 * gets corrupted such that #GP delivery fails due to a bad descriptor
436 * causing #GP and we hit this condition while CR2 coincidentally
437 * points to the stack guard page, we'll think we overflowed the
438 * stack. Given that we're going to panic one way or another
439 * if this happens, this isn't necessarily worth fixing.
441 * If necessary, we could improve the test by only diagnosing
442 * a stack overflow if the saved RSP points within 47 bytes of
443 * the bottom of the stack: if RSP == tsk_stack + 48 and we
444 * take an exception, the stack is already aligned and there
445 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a
446 * possible error code, so a stack overflow would *not* double
447 * fault. With any less space left, exception delivery could
448 * fail, and, as a practical matter, we've overflowed the
449 * stack even if the actual trigger for the double fault was
452 if ((unsigned long)task_stack_page(tsk) - 1 - address < PAGE_SIZE) {
453 handle_stack_overflow("kernel stack overflow (double-fault)",
458 pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code);
459 die("double fault", regs, error_code);
460 panic("Machine halted.");
461 instrumentation_end();
464 DEFINE_IDTENTRY(exc_bounds)
466 if (notify_die(DIE_TRAP, "bounds", regs, 0,
467 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
469 cond_local_irq_enable(regs);
471 if (!user_mode(regs))
472 die("bounds", regs, 0);
474 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL);
476 cond_local_irq_disable(regs);
479 enum kernel_gp_hint {
486 * When an uncaught #GP occurs, try to determine the memory address accessed by
487 * the instruction and return that address to the caller. Also, try to figure
488 * out whether any part of the access to that address was non-canonical.
490 static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs,
493 u8 insn_buf[MAX_INSN_SIZE];
496 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip,
500 kernel_insn_init(&insn, insn_buf, MAX_INSN_SIZE);
501 insn_get_modrm(&insn);
504 *addr = (unsigned long)insn_get_addr_ref(&insn, regs);
511 * - the operand is not in the kernel half
512 * - the last byte of the operand is not in the user canonical half
514 if (*addr < ~__VIRTUAL_MASK &&
515 *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK)
516 return GP_NON_CANONICAL;
522 #define GPFSTR "general protection fault"
524 DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)
526 char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR;
527 enum kernel_gp_hint hint = GP_NO_HINT;
528 struct task_struct *tsk;
529 unsigned long gp_addr;
532 cond_local_irq_enable(regs);
534 if (static_cpu_has(X86_FEATURE_UMIP)) {
535 if (user_mode(regs) && fixup_umip_exception(regs))
539 if (v8086_mode(regs)) {
541 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
548 if (user_mode(regs)) {
549 tsk->thread.error_code = error_code;
550 tsk->thread.trap_nr = X86_TRAP_GP;
552 show_signal(tsk, SIGSEGV, "", desc, regs, error_code);
557 if (fixup_exception(regs, X86_TRAP_GP, error_code, 0))
560 tsk->thread.error_code = error_code;
561 tsk->thread.trap_nr = X86_TRAP_GP;
564 * To be potentially processing a kprobe fault and to trust the result
565 * from kprobe_running(), we have to be non-preemptible.
567 if (!preemptible() &&
569 kprobe_fault_handler(regs, X86_TRAP_GP))
572 ret = notify_die(DIE_GPF, desc, regs, error_code, X86_TRAP_GP, SIGSEGV);
573 if (ret == NOTIFY_STOP)
577 snprintf(desc, sizeof(desc), "segment-related " GPFSTR);
579 hint = get_kernel_gp_address(regs, &gp_addr);
581 if (hint != GP_NO_HINT)
582 snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx",
583 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address"
584 : "maybe for address",
588 * KASAN is interested only in the non-canonical case, clear it
591 if (hint != GP_NON_CANONICAL)
594 die_addr(desc, regs, error_code, gp_addr);
597 cond_local_irq_disable(regs);
600 static bool do_int3(struct pt_regs *regs)
604 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
605 if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP,
606 SIGTRAP) == NOTIFY_STOP)
608 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
610 #ifdef CONFIG_KPROBES
611 if (kprobe_int3_handler(regs))
614 res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP);
616 return res == NOTIFY_STOP;
619 static void do_int3_user(struct pt_regs *regs)
624 cond_local_irq_enable(regs);
625 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL);
626 cond_local_irq_disable(regs);
629 DEFINE_IDTENTRY_RAW(exc_int3)
632 * poke_int3_handler() is completely self contained code; it does (and
633 * must) *NOT* call out to anything, lest it hits upon yet another
636 if (poke_int3_handler(regs))
640 * irqentry_enter_from_user_mode() uses static_branch_{,un}likely()
641 * and therefore can trigger INT3, hence poke_int3_handler() must
642 * be done before. If the entry came from kernel mode, then use
643 * nmi_enter() because the INT3 could have been hit in any context
646 if (user_mode(regs)) {
647 irqentry_enter_from_user_mode(regs);
648 instrumentation_begin();
650 instrumentation_end();
651 irqentry_exit_to_user_mode(regs);
653 bool irq_state = idtentry_enter_nmi(regs);
654 instrumentation_begin();
656 die("int3", regs, 0);
657 instrumentation_end();
658 idtentry_exit_nmi(regs, irq_state);
664 * Help handler running on a per-cpu (IST or entry trampoline) stack
665 * to switch to the normal thread stack if the interrupted code was in
666 * user mode. The actual stack switch is done in entry_64.S
668 asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs)
670 struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1;
676 struct bad_iret_stack {
677 void *error_entry_ret;
681 asmlinkage __visible noinstr
682 struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
685 * This is called from entry_64.S early in handling a fault
686 * caused by a bad iret to user mode. To handle the fault
687 * correctly, we want to move our stack frame to where it would
688 * be had we entered directly on the entry stack (rather than
689 * just below the IRET frame) and we want to pretend that the
690 * exception came from the IRET target.
692 struct bad_iret_stack tmp, *new_stack =
693 (struct bad_iret_stack *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
695 /* Copy the IRET target to the temporary storage. */
696 __memcpy(&tmp.regs.ip, (void *)s->regs.sp, 5*8);
698 /* Copy the remainder of the stack from the current stack. */
699 __memcpy(&tmp, s, offsetof(struct bad_iret_stack, regs.ip));
701 /* Update the entry stack */
702 __memcpy(new_stack, &tmp, sizeof(tmp));
704 BUG_ON(!user_mode(&new_stack->regs));
709 static bool is_sysenter_singlestep(struct pt_regs *regs)
712 * We don't try for precision here. If we're anywhere in the region of
713 * code that can be single-stepped in the SYSENTER entry path, then
714 * assume that this is a useless single-step trap due to SYSENTER
715 * being invoked with TF set. (We don't know in advance exactly
716 * which instructions will be hit because BTF could plausibly
720 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) <
721 (unsigned long)__end_SYSENTER_singlestep_region -
722 (unsigned long)__begin_SYSENTER_singlestep_region;
723 #elif defined(CONFIG_IA32_EMULATION)
724 return (regs->ip - (unsigned long)entry_SYSENTER_compat) <
725 (unsigned long)__end_entry_SYSENTER_compat -
726 (unsigned long)entry_SYSENTER_compat;
732 static __always_inline void debug_enter(unsigned long *dr6, unsigned long *dr7)
735 * Disable breakpoints during exception handling; recursive exceptions
736 * are exceedingly 'fun'.
738 * Since this function is NOKPROBE, and that also applies to
739 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a
740 * HW_BREAKPOINT_W on our stack)
742 * Entry text is excluded for HW_BP_X and cpu_entry_area, which
743 * includes the entry stack is excluded for everything.
745 *dr7 = local_db_save();
748 * The Intel SDM says:
750 * Certain debug exceptions may clear bits 0-3. The remaining
751 * contents of the DR6 register are never cleared by the
752 * processor. To avoid confusion in identifying debug
753 * exceptions, debug handlers should clear the register before
754 * returning to the interrupted task.
756 * Keep it simple: clear DR6 immediately.
758 get_debugreg(*dr6, 6);
760 /* Filter out all the reserved bits which are preset to 1 */
761 *dr6 &= ~DR6_RESERVED;
764 static __always_inline void debug_exit(unsigned long dr7)
766 local_db_restore(dr7);
770 * Our handling of the processor debug registers is non-trivial.
771 * We do not clear them on entry and exit from the kernel. Therefore
772 * it is possible to get a watchpoint trap here from inside the kernel.
773 * However, the code in ./ptrace.c has ensured that the user can
774 * only set watchpoints on userspace addresses. Therefore the in-kernel
775 * watchpoint trap can only occur in code which is reading/writing
776 * from user space. Such code must not hold kernel locks (since it
777 * can equally take a page fault), therefore it is safe to call
778 * force_sig_info even though that claims and releases locks.
780 * Code in ./signal.c ensures that the debug control register
781 * is restored before we deliver any signal, and therefore that
782 * user code runs with the correct debug control register even though
785 * Being careful here means that we don't have to be as careful in a
786 * lot of more complicated places (task switching can be a bit lazy
787 * about restoring all the debug state, and ptrace doesn't have to
788 * find every occurrence of the TF bit that could be saved away even
791 * May run on IST stack.
793 static void handle_debug(struct pt_regs *regs, unsigned long dr6, bool user)
795 struct task_struct *tsk = current;
800 * The SDM says "The processor clears the BTF flag when it
801 * generates a debug exception." Clear TIF_BLOCKSTEP to keep
802 * TIF_BLOCKSTEP in sync with the hardware BTF flag.
804 clear_thread_flag(TIF_BLOCKSTEP);
807 * If DR6 is zero, no point in trying to handle it. The kernel is
814 * If dr6 has no reason to give us about the origin of this trap,
815 * then it's very likely the result of an icebp/int01 trap.
816 * User wants a sigtrap for that.
818 user_icebp = user && !dr6;
820 /* Store the virtualized DR6 value */
821 tsk->thread.debugreg6 = dr6;
823 #ifdef CONFIG_KPROBES
824 if (kprobe_debug_handler(regs)) {
829 if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, 0,
830 SIGTRAP) == NOTIFY_STOP) {
834 /* It's safe to allow irq's after DR6 has been saved */
835 cond_local_irq_enable(regs);
837 if (v8086_mode(regs)) {
838 handle_vm86_trap((struct kernel_vm86_regs *) regs, 0,
843 if (WARN_ON_ONCE((dr6 & DR_STEP) && !user_mode(regs))) {
845 * Historical junk that used to handle SYSENTER single-stepping.
846 * This should be unreachable now. If we survive for a while
847 * without anyone hitting this warning, we'll turn this into
850 tsk->thread.debugreg6 &= ~DR_STEP;
851 set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
852 regs->flags &= ~X86_EFLAGS_TF;
855 si_code = get_si_code(tsk->thread.debugreg6);
856 if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
857 send_sigtrap(regs, 0, si_code);
860 cond_local_irq_disable(regs);
863 static __always_inline void exc_debug_kernel(struct pt_regs *regs,
866 bool irq_state = idtentry_enter_nmi(regs);
867 instrumentation_begin();
870 * If something gets miswired and we end up here for a user mode
871 * #DB, we will malfunction.
873 WARN_ON_ONCE(user_mode(regs));
876 * Catch SYSENTER with TF set and clear DR_STEP. If this hit a
877 * watchpoint at the same time then that will still be handled.
879 if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs))
882 handle_debug(regs, dr6, false);
884 instrumentation_end();
885 idtentry_exit_nmi(regs, irq_state);
888 static __always_inline void exc_debug_user(struct pt_regs *regs,
892 * If something gets miswired and we end up here for a kernel mode
893 * #DB, we will malfunction.
895 WARN_ON_ONCE(!user_mode(regs));
897 irqentry_enter_from_user_mode(regs);
898 instrumentation_begin();
900 handle_debug(regs, dr6, true);
902 instrumentation_end();
903 irqentry_exit_to_user_mode(regs);
907 /* IST stack entry */
908 DEFINE_IDTENTRY_DEBUG(exc_debug)
910 unsigned long dr6, dr7;
912 debug_enter(&dr6, &dr7);
913 exc_debug_kernel(regs, dr6);
917 /* User entry, runs on regular task stack */
918 DEFINE_IDTENTRY_DEBUG_USER(exc_debug)
920 unsigned long dr6, dr7;
922 debug_enter(&dr6, &dr7);
923 exc_debug_user(regs, dr6);
927 /* 32 bit does not have separate entry points. */
928 DEFINE_IDTENTRY_RAW(exc_debug)
930 unsigned long dr6, dr7;
932 debug_enter(&dr6, &dr7);
935 exc_debug_user(regs, dr6);
937 exc_debug_kernel(regs, dr6);
944 * Note that we play around with the 'TS' bit in an attempt to get
945 * the correct behaviour even in the presence of the asynchronous
948 static void math_error(struct pt_regs *regs, int trapnr)
950 struct task_struct *task = current;
951 struct fpu *fpu = &task->thread.fpu;
953 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
956 cond_local_irq_enable(regs);
958 if (!user_mode(regs)) {
959 if (fixup_exception(regs, trapnr, 0, 0))
962 task->thread.error_code = 0;
963 task->thread.trap_nr = trapnr;
965 if (notify_die(DIE_TRAP, str, regs, 0, trapnr,
966 SIGFPE) != NOTIFY_STOP)
972 * Save the info for the exception handler and clear the error.
976 task->thread.trap_nr = trapnr;
977 task->thread.error_code = 0;
979 si_code = fpu__exception_code(fpu, trapnr);
980 /* Retry when we get spurious exceptions: */
984 force_sig_fault(SIGFPE, si_code,
985 (void __user *)uprobe_get_trap_addr(regs));
987 cond_local_irq_disable(regs);
990 DEFINE_IDTENTRY(exc_coprocessor_error)
992 math_error(regs, X86_TRAP_MF);
995 DEFINE_IDTENTRY(exc_simd_coprocessor_error)
997 if (IS_ENABLED(CONFIG_X86_INVD_BUG)) {
998 /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */
999 if (!static_cpu_has(X86_FEATURE_XMM)) {
1000 __exc_general_protection(regs, 0);
1004 math_error(regs, X86_TRAP_XF);
1007 DEFINE_IDTENTRY(exc_spurious_interrupt_bug)
1010 * This addresses a Pentium Pro Erratum:
1012 * PROBLEM: If the APIC subsystem is configured in mixed mode with
1013 * Virtual Wire mode implemented through the local APIC, an
1014 * interrupt vector of 0Fh (Intel reserved encoding) may be
1015 * generated by the local APIC (Int 15). This vector may be
1016 * generated upon receipt of a spurious interrupt (an interrupt
1017 * which is removed before the system receives the INTA sequence)
1018 * instead of the programmed 8259 spurious interrupt vector.
1020 * IMPLICATION: The spurious interrupt vector programmed in the
1021 * 8259 is normally handled by an operating system's spurious
1022 * interrupt handler. However, a vector of 0Fh is unknown to some
1023 * operating systems, which would crash if this erratum occurred.
1025 * In theory this could be limited to 32bit, but the handler is not
1026 * hurting and who knows which other CPUs suffer from this.
1030 DEFINE_IDTENTRY(exc_device_not_available)
1032 unsigned long cr0 = read_cr0();
1034 #ifdef CONFIG_MATH_EMULATION
1035 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) {
1036 struct math_emu_info info = { };
1038 cond_local_irq_enable(regs);
1041 math_emulate(&info);
1043 cond_local_irq_disable(regs);
1048 /* This should not happen. */
1049 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) {
1050 /* Try to fix it up and carry on. */
1051 write_cr0(cr0 & ~X86_CR0_TS);
1054 * Something terrible happened, and we're better off trying
1055 * to kill the task than getting stuck in a never-ending
1056 * loop of #NM faults.
1058 die("unexpected #NM exception", regs, 0);
1062 #ifdef CONFIG_X86_32
1063 DEFINE_IDTENTRY_SW(iret_error)
1066 if (notify_die(DIE_TRAP, "iret exception", regs, 0,
1067 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
1068 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0,
1069 ILL_BADSTK, (void __user *)NULL);
1071 local_irq_disable();
1075 void __init trap_init(void)
1077 /* Init cpu_entry_area before IST entries are set up */
1078 setup_cpu_entry_areas();
1083 * Should be a barrier for any external CPU state:
1087 idt_setup_ist_traps();