1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
56 #include <linux/numa.h>
57 #include <linux/pgtable.h>
58 #include <linux/overflow.h>
64 #include <asm/realmode.h>
67 #include <asm/tlbflush.h>
69 #include <asm/mwait.h>
71 #include <asm/io_apic.h>
72 #include <asm/fpu/internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/i8259.h>
78 #include <asm/qspinlock.h>
79 #include <asm/intel-family.h>
80 #include <asm/cpu_device_id.h>
81 #include <asm/spec-ctrl.h>
82 #include <asm/hw_irq.h>
83 #include <asm/stackprotector.h>
85 /* representing HT siblings of each logical CPU */
86 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
87 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89 /* representing HT and core siblings of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
91 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
93 /* representing HT, core, and die siblings of each logical CPU */
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
95 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
99 /* Per CPU bogomips and other parameters */
100 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
101 EXPORT_PER_CPU_SYMBOL(cpu_info);
103 /* Logical package management. We might want to allocate that dynamically */
104 unsigned int __max_logical_packages __read_mostly;
105 EXPORT_SYMBOL(__max_logical_packages);
106 static unsigned int logical_packages __read_mostly;
107 static unsigned int logical_die __read_mostly;
109 /* Maximum number of SMT threads on any online core */
110 int __read_mostly __max_smt_threads = 1;
112 /* Flag to indicate if a complete sched domain rebuild is required */
113 bool x86_topology_update;
115 int arch_update_cpu_topology(void)
117 int retval = x86_topology_update;
119 x86_topology_update = false;
123 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
127 spin_lock_irqsave(&rtc_lock, flags);
128 CMOS_WRITE(0xa, 0xf);
129 spin_unlock_irqrestore(&rtc_lock, flags);
130 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
132 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
136 static inline void smpboot_restore_warm_reset_vector(void)
141 * Paranoid: Set warm reset code and vector here back
144 spin_lock_irqsave(&rtc_lock, flags);
146 spin_unlock_irqrestore(&rtc_lock, flags);
148 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
151 static void init_freq_invariance(bool secondary);
154 * Report back to the Boot Processor during boot time or to the caller processor
157 static void smp_callin(void)
162 * If waken up by an INIT in an 82489DX configuration
163 * cpu_callout_mask guarantees we don't get here before
164 * an INIT_deassert IPI reaches our local APIC, so it is
165 * now safe to touch our local APIC.
167 cpuid = smp_processor_id();
170 * the boot CPU has finished the init stage and is spinning
171 * on callin_map until we finish. We are free to set up this
172 * CPU, first the APIC. (this is probably redundant on most
178 * Save our processor parameters. Note: this information
179 * is needed for clock calibration.
181 smp_store_cpu_info(cpuid);
184 * The topology information must be up to date before
185 * calibrate_delay() and notify_cpu_starting().
187 set_cpu_sibling_map(raw_smp_processor_id());
189 init_freq_invariance(true);
193 * Update loops_per_jiffy in cpu_data. Previous call to
194 * smp_store_cpu_info() stored a value that is close but not as
195 * accurate as the value just calculated.
198 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
199 pr_debug("Stack at about %p\n", &cpuid);
203 notify_cpu_starting(cpuid);
206 * Allow the master to continue.
208 cpumask_set_cpu(cpuid, cpu_callin_mask);
211 static int cpu0_logical_apicid;
212 static int enable_start_cpu0;
214 * Activate a secondary processor.
216 static void notrace start_secondary(void *unused)
219 * Don't put *anything* except direct CPU state initialization
220 * before cpu_init(), SMP booting is too fragile that we want to
221 * limit the things done here to the most necessary things.
226 /* switch away from the initial page table */
227 load_cr3(swapper_pg_dir);
232 x86_cpuinit.early_percpu_clock_init();
236 enable_start_cpu0 = 0;
238 /* otherwise gcc will move up smp_processor_id before the cpu_init */
241 * Check TSC synchronization with the boot CPU:
243 check_tsc_sync_target();
245 speculative_store_bypass_ht_init();
248 * Lock vector_lock, set CPU online and bring the vector
249 * allocator online. Online must be set with vector_lock held
250 * to prevent a concurrent irq setup/teardown from seeing a
251 * half valid vector space.
254 set_cpu_online(smp_processor_id(), true);
256 unlock_vector_lock();
257 cpu_set_state_online(smp_processor_id());
258 x86_platform.nmi_init();
260 /* enable local interrupts */
263 x86_cpuinit.setup_percpu_clockev();
266 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
270 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
273 bool topology_is_primary_thread(unsigned int cpu)
275 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
279 * topology_smt_supported - Check whether SMT is supported by the CPUs
281 bool topology_smt_supported(void)
283 return smp_num_siblings > 1;
287 * topology_phys_to_logical_pkg - Map a physical package id to a logical
289 * Returns logical package id or -1 if not found
291 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
295 for_each_possible_cpu(cpu) {
296 struct cpuinfo_x86 *c = &cpu_data(cpu);
298 if (c->initialized && c->phys_proc_id == phys_pkg)
299 return c->logical_proc_id;
303 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
305 * topology_phys_to_logical_die - Map a physical die id to logical
307 * Returns logical die id or -1 if not found
309 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
312 int proc_id = cpu_data(cur_cpu).phys_proc_id;
314 for_each_possible_cpu(cpu) {
315 struct cpuinfo_x86 *c = &cpu_data(cpu);
317 if (c->initialized && c->cpu_die_id == die_id &&
318 c->phys_proc_id == proc_id)
319 return c->logical_die_id;
323 EXPORT_SYMBOL(topology_phys_to_logical_die);
326 * topology_update_package_map - Update the physical to logical package map
327 * @pkg: The physical package id as retrieved via CPUID
328 * @cpu: The cpu for which this is updated
330 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
334 /* Already available somewhere? */
335 new = topology_phys_to_logical_pkg(pkg);
339 new = logical_packages++;
341 pr_info("CPU %u Converting physical %u to logical package %u\n",
345 cpu_data(cpu).logical_proc_id = new;
349 * topology_update_die_map - Update the physical to logical die map
350 * @die: The die id as retrieved via CPUID
351 * @cpu: The cpu for which this is updated
353 int topology_update_die_map(unsigned int die, unsigned int cpu)
357 /* Already available somewhere? */
358 new = topology_phys_to_logical_die(die, cpu);
364 pr_info("CPU %u Converting physical %u to logical die %u\n",
368 cpu_data(cpu).logical_die_id = new;
372 void __init smp_store_boot_cpu_info(void)
374 int id = 0; /* CPU 0 */
375 struct cpuinfo_x86 *c = &cpu_data(id);
379 topology_update_package_map(c->phys_proc_id, id);
380 topology_update_die_map(c->cpu_die_id, id);
381 c->initialized = true;
385 * The bootstrap kernel entry code has set these up. Save them for
388 void smp_store_cpu_info(int id)
390 struct cpuinfo_x86 *c = &cpu_data(id);
392 /* Copy boot_cpu_data only on the first bringup */
397 * During boot time, CPU0 has this setup already. Save the info when
398 * bringing up AP or offlined CPU0.
400 identify_secondary_cpu(c);
401 c->initialized = true;
405 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
407 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
409 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
413 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
415 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
417 return !WARN_ONCE(!topology_same_node(c, o),
418 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
419 "[node: %d != %d]. Ignoring dependency.\n",
420 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
423 #define link_mask(mfunc, c1, c2) \
425 cpumask_set_cpu((c1), mfunc(c2)); \
426 cpumask_set_cpu((c2), mfunc(c1)); \
429 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
431 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
432 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
434 if (c->phys_proc_id == o->phys_proc_id &&
435 c->cpu_die_id == o->cpu_die_id &&
436 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
437 if (c->cpu_core_id == o->cpu_core_id)
438 return topology_sane(c, o, "smt");
440 if ((c->cu_id != 0xff) &&
441 (o->cu_id != 0xff) &&
442 (c->cu_id == o->cu_id))
443 return topology_sane(c, o, "smt");
446 } else if (c->phys_proc_id == o->phys_proc_id &&
447 c->cpu_die_id == o->cpu_die_id &&
448 c->cpu_core_id == o->cpu_core_id) {
449 return topology_sane(c, o, "smt");
456 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
458 * These are Intel CPUs that enumerate an LLC that is shared by
459 * multiple NUMA nodes. The LLC on these systems is shared for
460 * off-package data access but private to the NUMA node (half
461 * of the package) for on-package access.
463 * CPUID (the source of the information about the LLC) can only
464 * enumerate the cache as being shared *or* unshared, but not
465 * this particular configuration. The CPU in this case enumerates
466 * the cache to be shared across the entire package (spanning both
470 static const struct x86_cpu_id snc_cpu[] = {
471 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL),
475 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
477 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
479 /* Do not match if we do not have a valid APICID for cpu: */
480 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
483 /* Do not match if LLC id does not match: */
484 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
488 * Allow the SNC topology without warning. Return of false
489 * means 'c' does not share the LLC of 'o'. This will be
490 * reflected to userspace.
492 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
495 return topology_sane(c, o, "llc");
499 * Unlike the other levels, we do not enforce keeping a
500 * multicore group inside a NUMA node. If this happens, we will
501 * discard the MC level of the topology later.
503 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
505 if (c->phys_proc_id == o->phys_proc_id)
510 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
512 if ((c->phys_proc_id == o->phys_proc_id) &&
513 (c->cpu_die_id == o->cpu_die_id))
519 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
520 static inline int x86_sched_itmt_flags(void)
522 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
525 #ifdef CONFIG_SCHED_MC
526 static int x86_core_flags(void)
528 return cpu_core_flags() | x86_sched_itmt_flags();
531 #ifdef CONFIG_SCHED_SMT
532 static int x86_smt_flags(void)
534 return cpu_smt_flags() | x86_sched_itmt_flags();
539 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
540 #ifdef CONFIG_SCHED_SMT
541 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
543 #ifdef CONFIG_SCHED_MC
544 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
549 static struct sched_domain_topology_level x86_topology[] = {
550 #ifdef CONFIG_SCHED_SMT
551 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
553 #ifdef CONFIG_SCHED_MC
554 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
556 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
561 * Set if a package/die has multiple NUMA nodes inside.
562 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
563 * Sub-NUMA Clustering have this.
565 static bool x86_has_numa_in_package;
567 void set_cpu_sibling_map(int cpu)
569 bool has_smt = smp_num_siblings > 1;
570 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
571 struct cpuinfo_x86 *c = &cpu_data(cpu);
572 struct cpuinfo_x86 *o;
575 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
578 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
579 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
580 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
581 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
586 for_each_cpu(i, cpu_sibling_setup_mask) {
589 if ((i == cpu) || (has_smt && match_smt(c, o)))
590 link_mask(topology_sibling_cpumask, cpu, i);
592 if ((i == cpu) || (has_mp && match_llc(c, o)))
593 link_mask(cpu_llc_shared_mask, cpu, i);
598 * This needs a separate iteration over the cpus because we rely on all
599 * topology_sibling_cpumask links to be set-up.
601 for_each_cpu(i, cpu_sibling_setup_mask) {
604 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
605 link_mask(topology_core_cpumask, cpu, i);
608 * Does this new cpu bringup a new core?
611 topology_sibling_cpumask(cpu)) == 1) {
613 * for each core in package, increment
614 * the booted_cores for this new cpu
617 topology_sibling_cpumask(i)) == i)
620 * increment the core count for all
621 * the other cpus in this package
624 cpu_data(i).booted_cores++;
625 } else if (i != cpu && !c->booted_cores)
626 c->booted_cores = cpu_data(i).booted_cores;
628 if (match_pkg(c, o) && !topology_same_node(c, o))
629 x86_has_numa_in_package = true;
631 if ((i == cpu) || (has_mp && match_die(c, o)))
632 link_mask(topology_die_cpumask, cpu, i);
635 threads = cpumask_weight(topology_sibling_cpumask(cpu));
636 if (threads > __max_smt_threads)
637 __max_smt_threads = threads;
640 /* maps the cpu to the sched domain representing multi-core */
641 const struct cpumask *cpu_coregroup_mask(int cpu)
643 return cpu_llc_shared_mask(cpu);
646 static void impress_friends(void)
649 unsigned long bogosum = 0;
651 * Allow the user to impress friends.
653 pr_debug("Before bogomips\n");
654 for_each_possible_cpu(cpu)
655 if (cpumask_test_cpu(cpu, cpu_callout_mask))
656 bogosum += cpu_data(cpu).loops_per_jiffy;
657 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
660 (bogosum/(5000/HZ))%100);
662 pr_debug("Before bogocount - setting activated=1\n");
665 void __inquire_remote_apic(int apicid)
667 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
668 const char * const names[] = { "ID", "VERSION", "SPIV" };
672 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
674 for (i = 0; i < ARRAY_SIZE(regs); i++) {
675 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
680 status = safe_apic_wait_icr_idle();
682 pr_cont("a previous APIC delivery may have failed\n");
684 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
689 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
690 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
693 case APIC_ICR_RR_VALID:
694 status = apic_read(APIC_RRR);
695 pr_cont("%08x\n", status);
704 * The Multiprocessor Specification 1.4 (1997) example code suggests
705 * that there should be a 10ms delay between the BSP asserting INIT
706 * and de-asserting INIT, when starting a remote processor.
707 * But that slows boot and resume on modern processors, which include
708 * many cores and don't require that delay.
710 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
711 * Modern processor families are quirked to remove the delay entirely.
713 #define UDELAY_10MS_DEFAULT 10000
715 static unsigned int init_udelay = UINT_MAX;
717 static int __init cpu_init_udelay(char *str)
719 get_option(&str, &init_udelay);
723 early_param("cpu_init_udelay", cpu_init_udelay);
725 static void __init smp_quirk_init_udelay(void)
727 /* if cmdline changed it from default, leave it alone */
728 if (init_udelay != UINT_MAX)
731 /* if modern processor, use no delay */
732 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
733 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
734 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
738 /* else, use legacy delay */
739 init_udelay = UDELAY_10MS_DEFAULT;
743 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
744 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
745 * won't ... remember to clear down the APIC, etc later.
748 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
750 unsigned long send_status, accept_status = 0;
754 /* Boot on the stack */
755 /* Kick the second */
756 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
758 pr_debug("Waiting for send to finish...\n");
759 send_status = safe_apic_wait_icr_idle();
762 * Give the other CPU some time to accept the IPI.
765 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
766 maxlvt = lapic_get_maxlvt();
767 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
768 apic_write(APIC_ESR, 0);
769 accept_status = (apic_read(APIC_ESR) & 0xEF);
771 pr_debug("NMI sent\n");
774 pr_err("APIC never delivered???\n");
776 pr_err("APIC delivery error (%lx)\n", accept_status);
778 return (send_status | accept_status);
782 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
784 unsigned long send_status = 0, accept_status = 0;
785 int maxlvt, num_starts, j;
787 maxlvt = lapic_get_maxlvt();
790 * Be paranoid about clearing APIC errors.
792 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
793 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
794 apic_write(APIC_ESR, 0);
798 pr_debug("Asserting INIT\n");
801 * Turn INIT on target chip
806 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
809 pr_debug("Waiting for send to finish...\n");
810 send_status = safe_apic_wait_icr_idle();
814 pr_debug("Deasserting INIT\n");
818 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
820 pr_debug("Waiting for send to finish...\n");
821 send_status = safe_apic_wait_icr_idle();
826 * Should we send STARTUP IPIs ?
828 * Determine this based on the APIC version.
829 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
831 if (APIC_INTEGRATED(boot_cpu_apic_version))
837 * Run STARTUP IPI loop.
839 pr_debug("#startup loops: %d\n", num_starts);
841 for (j = 1; j <= num_starts; j++) {
842 pr_debug("Sending STARTUP #%d\n", j);
843 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
844 apic_write(APIC_ESR, 0);
846 pr_debug("After apic_write\n");
853 /* Boot on the stack */
854 /* Kick the second */
855 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
859 * Give the other CPU some time to accept the IPI.
861 if (init_udelay == 0)
866 pr_debug("Startup point 1\n");
868 pr_debug("Waiting for send to finish...\n");
869 send_status = safe_apic_wait_icr_idle();
872 * Give the other CPU some time to accept the IPI.
874 if (init_udelay == 0)
879 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
880 apic_write(APIC_ESR, 0);
881 accept_status = (apic_read(APIC_ESR) & 0xEF);
882 if (send_status || accept_status)
885 pr_debug("After Startup\n");
888 pr_err("APIC never delivered???\n");
890 pr_err("APIC delivery error (%lx)\n", accept_status);
892 return (send_status | accept_status);
895 /* reduce the number of lines printed when booting a large cpu count system */
896 static void announce_cpu(int cpu, int apicid)
898 static int current_node = NUMA_NO_NODE;
899 int node = early_cpu_to_node(cpu);
900 static int width, node_width;
903 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
906 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
909 printk(KERN_INFO "x86: Booting SMP configuration:\n");
911 if (system_state < SYSTEM_RUNNING) {
912 if (node != current_node) {
913 if (current_node > (-1))
917 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
918 node_width - num_digits(node), " ", node);
921 /* Add padding for the BSP */
923 pr_cont("%*s", width + 1, " ");
925 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
928 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
932 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
936 cpu = smp_processor_id();
937 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
944 * Wake up AP by INIT, INIT, STARTUP sequence.
946 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
947 * boot-strap code which is not a desired behavior for waking up BSP. To
948 * void the boot-strap code, wake up CPU0 by NMI instead.
950 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
951 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
952 * We'll change this code in the future to wake up hard offlined CPU0 if
953 * real platform and request are available.
956 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
957 int *cpu0_nmi_registered)
965 * Wake up AP by INIT, INIT, STARTUP sequence.
968 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
973 * Wake up BSP by nmi.
975 * Register a NMI handler to help wake up CPU0.
977 boot_error = register_nmi_handler(NMI_LOCAL,
978 wakeup_cpu0_nmi, 0, "wake_cpu0");
981 enable_start_cpu0 = 1;
982 *cpu0_nmi_registered = 1;
983 if (apic->dest_logical == APIC_DEST_LOGICAL)
984 id = cpu0_logical_apicid;
987 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
996 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
1000 /* Just in case we booted with a single CPU. */
1001 alternatives_enable_smp();
1003 per_cpu(current_task, cpu) = idle;
1004 cpu_init_stack_canary(cpu, idle);
1006 /* Initialize the interrupt stack(s) */
1007 ret = irq_init_percpu_irqstack(cpu);
1011 #ifdef CONFIG_X86_32
1012 /* Stack for startup_32 can be just as for start_secondary onwards */
1013 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1015 initial_gs = per_cpu_offset(cpu);
1021 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1022 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1023 * Returns zero if CPU booted OK, else error code from
1024 * ->wakeup_secondary_cpu.
1026 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1027 int *cpu0_nmi_registered)
1029 /* start_ip had better be page-aligned! */
1030 unsigned long start_ip = real_mode_header->trampoline_start;
1032 unsigned long boot_error = 0;
1033 unsigned long timeout;
1035 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1036 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1037 initial_code = (unsigned long)start_secondary;
1038 initial_stack = idle->thread.sp;
1040 /* Enable the espfix hack for this CPU */
1041 init_espfix_ap(cpu);
1043 /* So we see what's up */
1044 announce_cpu(cpu, apicid);
1047 * This grunge runs the startup process for
1048 * the targeted processor.
1051 if (x86_platform.legacy.warm_reset) {
1053 pr_debug("Setting warm reset code and vector.\n");
1055 smpboot_setup_warm_reset_vector(start_ip);
1057 * Be paranoid about clearing APIC errors.
1059 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1060 apic_write(APIC_ESR, 0);
1061 apic_read(APIC_ESR);
1066 * AP might wait on cpu_callout_mask in cpu_init() with
1067 * cpu_initialized_mask set if previous attempt to online
1068 * it timed-out. Clear cpu_initialized_mask so that after
1069 * INIT/SIPI it could start with a clean state.
1071 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1075 * Wake up a CPU in difference cases:
1076 * - Use the method in the APIC driver if it's defined
1078 * - Use an INIT boot APIC message for APs or NMI for BSP.
1080 if (apic->wakeup_secondary_cpu)
1081 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1083 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1084 cpu0_nmi_registered);
1088 * Wait 10s total for first sign of life from AP
1091 timeout = jiffies + 10*HZ;
1092 while (time_before(jiffies, timeout)) {
1093 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1095 * Tell AP to proceed with initialization
1097 cpumask_set_cpu(cpu, cpu_callout_mask);
1107 * Wait till AP completes initial initialization
1109 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1111 * Allow other tasks to run while we wait for the
1112 * AP to come online. This also gives a chance
1113 * for the MTRR work(triggered by the AP coming online)
1114 * to be completed in the stop machine context.
1120 if (x86_platform.legacy.warm_reset) {
1122 * Cleanup possible dangling ends...
1124 smpboot_restore_warm_reset_vector();
1130 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1132 int apicid = apic->cpu_present_to_apicid(cpu);
1133 int cpu0_nmi_registered = 0;
1134 unsigned long flags;
1137 lockdep_assert_irqs_enabled();
1139 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1141 if (apicid == BAD_APICID ||
1142 !physid_isset(apicid, phys_cpu_present_map) ||
1143 !apic->apic_id_valid(apicid)) {
1144 pr_err("%s: bad cpu %d\n", __func__, cpu);
1149 * Already booted CPU?
1151 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1152 pr_debug("do_boot_cpu %d Already started\n", cpu);
1157 * Save current MTRR state in case it was changed since early boot
1158 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1162 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1163 err = cpu_check_up_prepare(cpu);
1164 if (err && err != -EBUSY)
1167 /* the FPU context is blank, nobody can own it */
1168 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1170 err = common_cpu_up(cpu, tidle);
1174 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1176 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1182 * Check TSC synchronization with the AP (keep irqs disabled
1185 local_irq_save(flags);
1186 check_tsc_sync_source(cpu);
1187 local_irq_restore(flags);
1189 while (!cpu_online(cpu)) {
1191 touch_nmi_watchdog();
1196 * Clean up the nmi handler. Do this after the callin and callout sync
1197 * to avoid impact of possible long unregister time.
1199 if (cpu0_nmi_registered)
1200 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1206 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1208 void arch_disable_smp_support(void)
1210 disable_ioapic_support();
1214 * Fall back to non SMP mode after errors.
1216 * RED-PEN audit/test this more. I bet there is more state messed up here.
1218 static __init void disable_smp(void)
1220 pr_info("SMP disabled\n");
1222 disable_ioapic_support();
1224 init_cpu_present(cpumask_of(0));
1225 init_cpu_possible(cpumask_of(0));
1227 if (smp_found_config)
1228 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1230 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1231 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1232 cpumask_set_cpu(0, topology_core_cpumask(0));
1233 cpumask_set_cpu(0, topology_die_cpumask(0));
1237 * Various sanity checks.
1239 static void __init smp_sanity_check(void)
1243 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1244 if (def_to_bigsmp && nr_cpu_ids > 8) {
1248 pr_warn("More than 8 CPUs detected - skipping them\n"
1249 "Use CONFIG_X86_BIGSMP\n");
1252 for_each_present_cpu(cpu) {
1254 set_cpu_present(cpu, false);
1259 for_each_possible_cpu(cpu) {
1261 set_cpu_possible(cpu, false);
1269 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1270 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1271 hard_smp_processor_id());
1273 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1277 * Should not be necessary because the MP table should list the boot
1278 * CPU too, but we do it for the sake of robustness anyway.
1280 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1281 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1282 boot_cpu_physical_apicid);
1283 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1288 static void __init smp_cpu_index_default(void)
1291 struct cpuinfo_x86 *c;
1293 for_each_possible_cpu(i) {
1295 /* mark all to hotplug */
1296 c->cpu_index = nr_cpu_ids;
1300 static void __init smp_get_logical_apicid(void)
1303 cpu0_logical_apicid = apic_read(APIC_LDR);
1305 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1309 * Prepare for SMP bootup.
1310 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1311 * for common interface support.
1313 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1317 smp_cpu_index_default();
1320 * Setup boot CPU information
1322 smp_store_boot_cpu_info(); /* Final full version of the data */
1323 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1326 for_each_possible_cpu(i) {
1327 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1328 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1329 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1330 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1334 * Set 'default' x86 topology, this matches default_topology() in that
1335 * it has NUMA nodes as a topology level. See also
1336 * native_smp_cpus_done().
1338 * Must be done before set_cpus_sibling_map() is ran.
1340 set_sched_topology(x86_topology);
1342 set_cpu_sibling_map(0);
1343 init_freq_invariance(false);
1346 switch (apic_intr_mode) {
1348 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1351 case APIC_SYMMETRIC_IO_NO_ROUTING:
1353 /* Setup local timer */
1354 x86_init.timers.setup_percpu_clockev();
1356 case APIC_VIRTUAL_WIRE:
1357 case APIC_SYMMETRIC_IO:
1361 /* Setup local timer */
1362 x86_init.timers.setup_percpu_clockev();
1364 smp_get_logical_apicid();
1367 print_cpu_info(&cpu_data(0));
1371 set_mtrr_aps_delayed_init();
1373 smp_quirk_init_udelay();
1375 speculative_store_bypass_ht_init();
1378 void arch_thaw_secondary_cpus_begin(void)
1380 set_mtrr_aps_delayed_init();
1383 void arch_thaw_secondary_cpus_end(void)
1389 * Early setup to make printk work.
1391 void __init native_smp_prepare_boot_cpu(void)
1393 int me = smp_processor_id();
1394 switch_to_new_gdt(me);
1395 /* already set me in cpu_online_mask in boot_cpu_init() */
1396 cpumask_set_cpu(me, cpu_callout_mask);
1397 cpu_set_state_online(me);
1398 native_pv_lock_init();
1401 void __init calculate_max_logical_packages(void)
1406 * Today neither Intel nor AMD support heterogenous systems so
1407 * extrapolate the boot cpu's data to all packages.
1409 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1410 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1411 pr_info("Max logical packages: %u\n", __max_logical_packages);
1414 void __init native_smp_cpus_done(unsigned int max_cpus)
1416 pr_debug("Boot done\n");
1418 calculate_max_logical_packages();
1420 if (x86_has_numa_in_package)
1421 set_sched_topology(x86_numa_in_package_topology);
1428 static int __initdata setup_possible_cpus = -1;
1429 static int __init _setup_possible_cpus(char *str)
1431 get_option(&str, &setup_possible_cpus);
1434 early_param("possible_cpus", _setup_possible_cpus);
1438 * cpu_possible_mask should be static, it cannot change as cpu's
1439 * are onlined, or offlined. The reason is per-cpu data-structures
1440 * are allocated by some modules at init time, and don't expect to
1441 * do this dynamically on cpu arrival/departure.
1442 * cpu_present_mask on the other hand can change dynamically.
1443 * In case when cpu_hotplug is not compiled, then we resort to current
1444 * behaviour, which is cpu_possible == cpu_present.
1447 * Three ways to find out the number of additional hotplug CPUs:
1448 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1449 * - The user can overwrite it with possible_cpus=NUM
1450 * - Otherwise don't reserve additional CPUs.
1451 * We do this because additional CPUs waste a lot of memory.
1454 __init void prefill_possible_map(void)
1458 /* No boot processor was found in mptable or ACPI MADT */
1459 if (!num_processors) {
1460 if (boot_cpu_has(X86_FEATURE_APIC)) {
1461 int apicid = boot_cpu_physical_apicid;
1462 int cpu = hard_smp_processor_id();
1464 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1466 /* Make sure boot cpu is enumerated */
1467 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1468 apic->apic_id_valid(apicid))
1469 generic_processor_info(apicid, boot_cpu_apic_version);
1472 if (!num_processors)
1476 i = setup_max_cpus ?: 1;
1477 if (setup_possible_cpus == -1) {
1478 possible = num_processors;
1479 #ifdef CONFIG_HOTPLUG_CPU
1481 possible += disabled_cpus;
1487 possible = setup_possible_cpus;
1489 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1491 /* nr_cpu_ids could be reduced via nr_cpus= */
1492 if (possible > nr_cpu_ids) {
1493 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1494 possible, nr_cpu_ids);
1495 possible = nr_cpu_ids;
1498 #ifdef CONFIG_HOTPLUG_CPU
1499 if (!setup_max_cpus)
1502 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1503 possible, setup_max_cpus);
1507 nr_cpu_ids = possible;
1509 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1510 possible, max_t(int, possible - num_processors, 0));
1512 reset_cpu_possible_mask();
1514 for (i = 0; i < possible; i++)
1515 set_cpu_possible(i, true);
1518 #ifdef CONFIG_HOTPLUG_CPU
1520 /* Recompute SMT state for all CPUs on offline */
1521 static void recompute_smt_state(void)
1523 int max_threads, cpu;
1526 for_each_online_cpu (cpu) {
1527 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1529 if (threads > max_threads)
1530 max_threads = threads;
1532 __max_smt_threads = max_threads;
1535 static void remove_siblinginfo(int cpu)
1538 struct cpuinfo_x86 *c = &cpu_data(cpu);
1540 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1541 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1543 * last thread sibling in this cpu core going down
1545 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1546 cpu_data(sibling).booted_cores--;
1549 for_each_cpu(sibling, topology_die_cpumask(cpu))
1550 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1551 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1552 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1553 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1554 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1555 cpumask_clear(cpu_llc_shared_mask(cpu));
1556 cpumask_clear(topology_sibling_cpumask(cpu));
1557 cpumask_clear(topology_core_cpumask(cpu));
1558 cpumask_clear(topology_die_cpumask(cpu));
1560 c->booted_cores = 0;
1561 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1562 recompute_smt_state();
1565 static void remove_cpu_from_maps(int cpu)
1567 set_cpu_online(cpu, false);
1568 cpumask_clear_cpu(cpu, cpu_callout_mask);
1569 cpumask_clear_cpu(cpu, cpu_callin_mask);
1570 /* was set by cpu_init() */
1571 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1572 numa_remove_cpu(cpu);
1575 void cpu_disable_common(void)
1577 int cpu = smp_processor_id();
1579 remove_siblinginfo(cpu);
1581 /* It's now safe to remove this processor from the online map */
1583 remove_cpu_from_maps(cpu);
1584 unlock_vector_lock();
1589 int native_cpu_disable(void)
1593 ret = lapic_can_unplug_cpu();
1598 * Disable the local APIC. Otherwise IPI broadcasts will reach
1599 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1602 apic_soft_disable();
1603 cpu_disable_common();
1608 int common_cpu_die(unsigned int cpu)
1612 /* We don't do anything here: idle task is faking death itself. */
1614 /* They ack this in play_dead() by setting CPU_DEAD */
1615 if (cpu_wait_death(cpu, 5)) {
1616 if (system_state == SYSTEM_RUNNING)
1617 pr_info("CPU %u is now offline\n", cpu);
1619 pr_err("CPU %u didn't die...\n", cpu);
1626 void native_cpu_die(unsigned int cpu)
1628 common_cpu_die(cpu);
1631 void play_dead_common(void)
1636 (void)cpu_report_death();
1639 * With physical CPU hotplug, we should halt the cpu
1641 local_irq_disable();
1644 static bool wakeup_cpu0(void)
1646 if (smp_processor_id() == 0 && enable_start_cpu0)
1653 * We need to flush the caches before going to sleep, lest we have
1654 * dirty data in our caches when we come back up.
1656 static inline void mwait_play_dead(void)
1658 unsigned int eax, ebx, ecx, edx;
1659 unsigned int highest_cstate = 0;
1660 unsigned int highest_subcstate = 0;
1664 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1665 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1667 if (!this_cpu_has(X86_FEATURE_MWAIT))
1669 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1671 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1674 eax = CPUID_MWAIT_LEAF;
1676 native_cpuid(&eax, &ebx, &ecx, &edx);
1679 * eax will be 0 if EDX enumeration is not valid.
1680 * Initialized below to cstate, sub_cstate value when EDX is valid.
1682 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1685 edx >>= MWAIT_SUBSTATE_SIZE;
1686 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1687 if (edx & MWAIT_SUBSTATE_MASK) {
1689 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1692 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1693 (highest_subcstate - 1);
1697 * This should be a memory location in a cache line which is
1698 * unlikely to be touched by other processors. The actual
1699 * content is immaterial as it is not actually modified in any way.
1701 mwait_ptr = ¤t_thread_info()->flags;
1707 * The CLFLUSH is a workaround for erratum AAI65 for
1708 * the Xeon 7400 series. It's not clear it is actually
1709 * needed, but it should be harmless in either case.
1710 * The WBINVD is insufficient due to the spurious-wakeup
1711 * case where we return around the loop.
1716 __monitor(mwait_ptr, 0, 0);
1720 * If NMI wants to wake up CPU0, start CPU0.
1727 void hlt_play_dead(void)
1729 if (__this_cpu_read(cpu_info.x86) >= 4)
1735 * If NMI wants to wake up CPU0, start CPU0.
1742 void native_play_dead(void)
1745 tboot_shutdown(TB_SHUTDOWN_WFS);
1747 mwait_play_dead(); /* Only returns on failure */
1748 if (cpuidle_play_dead())
1752 #else /* ... !CONFIG_HOTPLUG_CPU */
1753 int native_cpu_disable(void)
1758 void native_cpu_die(unsigned int cpu)
1760 /* We said "no" in __cpu_disable */
1764 void native_play_dead(void)
1771 #ifdef CONFIG_X86_64
1773 * APERF/MPERF frequency ratio computation.
1775 * The scheduler wants to do frequency invariant accounting and needs a <1
1776 * ratio to account for the 'current' frequency, corresponding to
1777 * freq_curr / freq_max.
1779 * Since the frequency freq_curr on x86 is controlled by micro-controller and
1780 * our P-state setting is little more than a request/hint, we need to observe
1781 * the effective frequency 'BusyMHz', i.e. the average frequency over a time
1782 * interval after discarding idle time. This is given by:
1784 * BusyMHz = delta_APERF / delta_MPERF * freq_base
1786 * where freq_base is the max non-turbo P-state.
1788 * The freq_max term has to be set to a somewhat arbitrary value, because we
1789 * can't know which turbo states will be available at a given point in time:
1790 * it all depends on the thermal headroom of the entire package. We set it to
1791 * the turbo level with 4 cores active.
1793 * Benchmarks show that's a good compromise between the 1C turbo ratio
1794 * (freq_curr/freq_max would rarely reach 1) and something close to freq_base,
1795 * which would ignore the entire turbo range (a conspicuous part, making
1796 * freq_curr/freq_max always maxed out).
1798 * An exception to the heuristic above is the Atom uarch, where we choose the
1799 * highest turbo level for freq_max since Atom's are generally oriented towards
1802 * Setting freq_max to anything less than the 1C turbo ratio makes the ratio
1803 * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1.
1806 DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key);
1808 static DEFINE_PER_CPU(u64, arch_prev_aperf);
1809 static DEFINE_PER_CPU(u64, arch_prev_mperf);
1810 static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE;
1811 static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE;
1813 void arch_set_max_freq_ratio(bool turbo_disabled)
1815 arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE :
1816 arch_turbo_freq_ratio;
1819 static bool turbo_disabled(void)
1824 err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en);
1828 return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
1831 static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1835 err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq);
1839 err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq);
1843 *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */
1844 *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */
1849 #include <asm/cpu_device_id.h>
1850 #include <asm/intel-family.h>
1852 #define X86_MATCH(model) \
1853 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \
1854 INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL)
1856 static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = {
1857 X86_MATCH(XEON_PHI_KNL),
1858 X86_MATCH(XEON_PHI_KNM),
1862 static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = {
1863 X86_MATCH(SKYLAKE_X),
1867 static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = {
1868 X86_MATCH(ATOM_GOLDMONT),
1869 X86_MATCH(ATOM_GOLDMONT_D),
1870 X86_MATCH(ATOM_GOLDMONT_PLUS),
1874 static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq,
1875 int num_delta_fratio)
1877 int fratio, delta_fratio, found;
1881 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1885 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1887 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1891 fratio = (msr >> 8) & 0xFF;
1895 if (found >= num_delta_fratio) {
1896 *turbo_freq = fratio;
1900 delta_fratio = (msr >> (i + 5)) & 0x7;
1904 fratio -= delta_fratio;
1913 static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size)
1919 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1923 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1925 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios);
1929 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts);
1933 for (i = 0; i < 64; i += 8) {
1934 group_size = (counts >> i) & 0xFF;
1935 if (group_size >= size) {
1936 *turbo_freq = (ratios >> i) & 0xFF;
1944 static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1949 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1953 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1957 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1958 *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */
1960 /* The CPU may have less than 4 cores */
1962 *turbo_freq = msr & 0xFF; /* 1C turbo */
1967 static bool intel_set_max_freq_ratio(void)
1969 u64 base_freq, turbo_freq;
1972 if (slv_set_max_freq_ratio(&base_freq, &turbo_freq))
1975 if (x86_match_cpu(has_glm_turbo_ratio_limits) &&
1976 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
1979 if (x86_match_cpu(has_knl_turbo_ratio_limits) &&
1980 knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
1983 if (x86_match_cpu(has_skx_turbo_ratio_limits) &&
1984 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4))
1987 if (core_set_max_freq_ratio(&base_freq, &turbo_freq))
1994 * Some hypervisors advertise X86_FEATURE_APERFMPERF
1995 * but then fill all MSR's with zeroes.
1996 * Some CPUs have turbo boost but don't declare any turbo ratio
1997 * in MSR_TURBO_RATIO_LIMIT.
1999 if (!base_freq || !turbo_freq) {
2000 pr_debug("Couldn't determine cpu base or turbo frequency, necessary for scale-invariant accounting.\n");
2004 turbo_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, base_freq);
2006 pr_debug("Non-zero turbo and base frequencies led to a 0 ratio.\n");
2010 arch_turbo_freq_ratio = turbo_ratio;
2011 arch_set_max_freq_ratio(turbo_disabled());
2016 static void init_counter_refs(void)
2020 rdmsrl(MSR_IA32_APERF, aperf);
2021 rdmsrl(MSR_IA32_MPERF, mperf);
2023 this_cpu_write(arch_prev_aperf, aperf);
2024 this_cpu_write(arch_prev_mperf, mperf);
2027 static void init_freq_invariance(bool secondary)
2031 if (!boot_cpu_has(X86_FEATURE_APERFMPERF))
2035 if (static_branch_likely(&arch_scale_freq_key)) {
2036 init_counter_refs();
2041 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2042 ret = intel_set_max_freq_ratio();
2045 init_counter_refs();
2046 static_branch_enable(&arch_scale_freq_key);
2048 pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n");
2052 static void disable_freq_invariance_workfn(struct work_struct *work)
2054 static_branch_disable(&arch_scale_freq_key);
2057 static DECLARE_WORK(disable_freq_invariance_work,
2058 disable_freq_invariance_workfn);
2060 DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE;
2062 void arch_scale_freq_tick(void)
2064 u64 freq_scale = SCHED_CAPACITY_SCALE;
2068 if (!arch_scale_freq_invariant())
2071 rdmsrl(MSR_IA32_APERF, aperf);
2072 rdmsrl(MSR_IA32_MPERF, mperf);
2074 acnt = aperf - this_cpu_read(arch_prev_aperf);
2075 mcnt = mperf - this_cpu_read(arch_prev_mperf);
2077 this_cpu_write(arch_prev_aperf, aperf);
2078 this_cpu_write(arch_prev_mperf, mperf);
2080 if (check_shl_overflow(acnt, 2*SCHED_CAPACITY_SHIFT, &acnt))
2083 if (check_mul_overflow(mcnt, arch_max_freq_ratio, &mcnt) || !mcnt)
2086 freq_scale = div64_u64(acnt, mcnt);
2090 if (freq_scale > SCHED_CAPACITY_SCALE)
2091 freq_scale = SCHED_CAPACITY_SCALE;
2093 this_cpu_write(arch_freq_scale, freq_scale);
2097 pr_warn("Scheduler frequency invariance went wobbly, disabling!\n");
2098 schedule_work(&disable_freq_invariance_work);
2101 static inline void init_freq_invariance(bool secondary)
2104 #endif /* CONFIG_X86_64 */