1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
56 #include <linux/numa.h>
57 #include <linux/pgtable.h>
58 #include <linux/overflow.h>
64 #include <asm/realmode.h>
67 #include <asm/tlbflush.h>
69 #include <asm/mwait.h>
71 #include <asm/io_apic.h>
72 #include <asm/fpu/api.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/i8259.h>
78 #include <asm/qspinlock.h>
79 #include <asm/intel-family.h>
80 #include <asm/cpu_device_id.h>
81 #include <asm/spec-ctrl.h>
82 #include <asm/hw_irq.h>
83 #include <asm/stackprotector.h>
86 /* representing HT siblings of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
90 /* representing HT and core siblings of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
92 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
94 /* representing HT, core, and die siblings of each logical CPU */
95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
96 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
98 /* Per CPU bogomips and other parameters */
99 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
100 EXPORT_PER_CPU_SYMBOL(cpu_info);
102 /* Logical package management. We might want to allocate that dynamically */
103 unsigned int __max_logical_packages __read_mostly;
104 EXPORT_SYMBOL(__max_logical_packages);
105 static unsigned int logical_packages __read_mostly;
106 static unsigned int logical_die __read_mostly;
108 /* Maximum number of SMT threads on any online core */
109 int __read_mostly __max_smt_threads = 1;
111 /* Flag to indicate if a complete sched domain rebuild is required */
112 bool x86_topology_update;
114 int arch_update_cpu_topology(void)
116 int retval = x86_topology_update;
118 x86_topology_update = false;
122 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
126 spin_lock_irqsave(&rtc_lock, flags);
127 CMOS_WRITE(0xa, 0xf);
128 spin_unlock_irqrestore(&rtc_lock, flags);
129 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
135 static inline void smpboot_restore_warm_reset_vector(void)
140 * Paranoid: Set warm reset code and vector here back
143 spin_lock_irqsave(&rtc_lock, flags);
145 spin_unlock_irqrestore(&rtc_lock, flags);
147 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
151 * Report back to the Boot Processor during boot time or to the caller processor
154 static void smp_callin(void)
159 * If waken up by an INIT in an 82489DX configuration
160 * cpu_callout_mask guarantees we don't get here before
161 * an INIT_deassert IPI reaches our local APIC, so it is
162 * now safe to touch our local APIC.
164 cpuid = smp_processor_id();
167 * the boot CPU has finished the init stage and is spinning
168 * on callin_map until we finish. We are free to set up this
169 * CPU, first the APIC. (this is probably redundant on most
175 * Save our processor parameters. Note: this information
176 * is needed for clock calibration.
178 smp_store_cpu_info(cpuid);
181 * The topology information must be up to date before
182 * calibrate_delay() and notify_cpu_starting().
184 set_cpu_sibling_map(raw_smp_processor_id());
186 ap_init_aperfmperf();
190 * Update loops_per_jiffy in cpu_data. Previous call to
191 * smp_store_cpu_info() stored a value that is close but not as
192 * accurate as the value just calculated.
195 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
196 pr_debug("Stack at about %p\n", &cpuid);
200 notify_cpu_starting(cpuid);
203 * Allow the master to continue.
205 cpumask_set_cpu(cpuid, cpu_callin_mask);
208 static int cpu0_logical_apicid;
209 static int enable_start_cpu0;
211 * Activate a secondary processor.
213 static void notrace start_secondary(void *unused)
216 * Don't put *anything* except direct CPU state initialization
217 * before cpu_init(), SMP booting is too fragile that we want to
218 * limit the things done here to the most necessary things.
223 /* switch away from the initial page table */
224 load_cr3(swapper_pg_dir);
227 cpu_init_secondary();
228 rcu_cpu_starting(raw_smp_processor_id());
229 x86_cpuinit.early_percpu_clock_init();
232 enable_start_cpu0 = 0;
234 /* otherwise gcc will move up smp_processor_id before the cpu_init */
237 * Check TSC synchronization with the boot CPU:
239 check_tsc_sync_target();
241 speculative_store_bypass_ht_init();
244 * Lock vector_lock, set CPU online and bring the vector
245 * allocator online. Online must be set with vector_lock held
246 * to prevent a concurrent irq setup/teardown from seeing a
247 * half valid vector space.
250 set_cpu_online(smp_processor_id(), true);
252 unlock_vector_lock();
253 cpu_set_state_online(smp_processor_id());
254 x86_platform.nmi_init();
256 /* enable local interrupts */
259 x86_cpuinit.setup_percpu_clockev();
262 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
266 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
269 bool topology_is_primary_thread(unsigned int cpu)
271 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
275 * topology_smt_supported - Check whether SMT is supported by the CPUs
277 bool topology_smt_supported(void)
279 return smp_num_siblings > 1;
283 * topology_phys_to_logical_pkg - Map a physical package id to a logical
285 * Returns logical package id or -1 if not found
287 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
291 for_each_possible_cpu(cpu) {
292 struct cpuinfo_x86 *c = &cpu_data(cpu);
294 if (c->initialized && c->phys_proc_id == phys_pkg)
295 return c->logical_proc_id;
299 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
301 * topology_phys_to_logical_die - Map a physical die id to logical
303 * Returns logical die id or -1 if not found
305 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
308 int proc_id = cpu_data(cur_cpu).phys_proc_id;
310 for_each_possible_cpu(cpu) {
311 struct cpuinfo_x86 *c = &cpu_data(cpu);
313 if (c->initialized && c->cpu_die_id == die_id &&
314 c->phys_proc_id == proc_id)
315 return c->logical_die_id;
319 EXPORT_SYMBOL(topology_phys_to_logical_die);
322 * topology_update_package_map - Update the physical to logical package map
323 * @pkg: The physical package id as retrieved via CPUID
324 * @cpu: The cpu for which this is updated
326 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
330 /* Already available somewhere? */
331 new = topology_phys_to_logical_pkg(pkg);
335 new = logical_packages++;
337 pr_info("CPU %u Converting physical %u to logical package %u\n",
341 cpu_data(cpu).logical_proc_id = new;
345 * topology_update_die_map - Update the physical to logical die map
346 * @die: The die id as retrieved via CPUID
347 * @cpu: The cpu for which this is updated
349 int topology_update_die_map(unsigned int die, unsigned int cpu)
353 /* Already available somewhere? */
354 new = topology_phys_to_logical_die(die, cpu);
360 pr_info("CPU %u Converting physical %u to logical die %u\n",
364 cpu_data(cpu).logical_die_id = new;
368 void __init smp_store_boot_cpu_info(void)
370 int id = 0; /* CPU 0 */
371 struct cpuinfo_x86 *c = &cpu_data(id);
375 topology_update_package_map(c->phys_proc_id, id);
376 topology_update_die_map(c->cpu_die_id, id);
377 c->initialized = true;
381 * The bootstrap kernel entry code has set these up. Save them for
384 void smp_store_cpu_info(int id)
386 struct cpuinfo_x86 *c = &cpu_data(id);
388 /* Copy boot_cpu_data only on the first bringup */
393 * During boot time, CPU0 has this setup already. Save the info when
394 * bringing up AP or offlined CPU0.
396 identify_secondary_cpu(c);
397 c->initialized = true;
401 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
403 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
405 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
409 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
411 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
413 return !WARN_ONCE(!topology_same_node(c, o),
414 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
415 "[node: %d != %d]. Ignoring dependency.\n",
416 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
419 #define link_mask(mfunc, c1, c2) \
421 cpumask_set_cpu((c1), mfunc(c2)); \
422 cpumask_set_cpu((c2), mfunc(c1)); \
425 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
427 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
428 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
430 if (c->phys_proc_id == o->phys_proc_id &&
431 c->cpu_die_id == o->cpu_die_id &&
432 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
433 if (c->cpu_core_id == o->cpu_core_id)
434 return topology_sane(c, o, "smt");
436 if ((c->cu_id != 0xff) &&
437 (o->cu_id != 0xff) &&
438 (c->cu_id == o->cu_id))
439 return topology_sane(c, o, "smt");
442 } else if (c->phys_proc_id == o->phys_proc_id &&
443 c->cpu_die_id == o->cpu_die_id &&
444 c->cpu_core_id == o->cpu_core_id) {
445 return topology_sane(c, o, "smt");
451 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
453 if (c->phys_proc_id == o->phys_proc_id &&
454 c->cpu_die_id == o->cpu_die_id)
459 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
461 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
463 /* If the arch didn't set up l2c_id, fall back to SMT */
464 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID)
465 return match_smt(c, o);
467 /* Do not match if L2 cache id does not match: */
468 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2))
471 return topology_sane(c, o, "l2c");
475 * Unlike the other levels, we do not enforce keeping a
476 * multicore group inside a NUMA node. If this happens, we will
477 * discard the MC level of the topology later.
479 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
481 if (c->phys_proc_id == o->phys_proc_id)
487 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
489 * Any Intel CPU that has multiple nodes per package and does not
490 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
492 * When in SNC mode, these CPUs enumerate an LLC that is shared
493 * by multiple NUMA nodes. The LLC is shared for off-package data
494 * access but private to the NUMA node (half of the package) for
495 * on-package access. CPUID (the source of the information about
496 * the LLC) can only enumerate the cache as shared or unshared,
497 * but not this particular configuration.
500 static const struct x86_cpu_id intel_cod_cpu[] = {
501 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */
502 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */
503 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */
507 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
509 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
510 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
511 bool intel_snc = id && id->driver_data;
513 /* Do not match if we do not have a valid APICID for cpu: */
514 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
517 /* Do not match if LLC id does not match: */
518 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
522 * Allow the SNC topology without warning. Return of false
523 * means 'c' does not share the LLC of 'o'. This will be
524 * reflected to userspace.
526 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
529 return topology_sane(c, o, "llc");
533 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC)
534 static inline int x86_sched_itmt_flags(void)
536 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
539 #ifdef CONFIG_SCHED_MC
540 static int x86_core_flags(void)
542 return cpu_core_flags() | x86_sched_itmt_flags();
545 #ifdef CONFIG_SCHED_SMT
546 static int x86_smt_flags(void)
548 return cpu_smt_flags() | x86_sched_itmt_flags();
551 #ifdef CONFIG_SCHED_CLUSTER
552 static int x86_cluster_flags(void)
554 return cpu_cluster_flags() | x86_sched_itmt_flags();
559 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
560 #ifdef CONFIG_SCHED_SMT
561 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
563 #ifdef CONFIG_SCHED_CLUSTER
564 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) },
566 #ifdef CONFIG_SCHED_MC
567 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
572 static struct sched_domain_topology_level x86_hybrid_topology[] = {
573 #ifdef CONFIG_SCHED_SMT
574 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
576 #ifdef CONFIG_SCHED_MC
577 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
579 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
583 static struct sched_domain_topology_level x86_topology[] = {
584 #ifdef CONFIG_SCHED_SMT
585 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
587 #ifdef CONFIG_SCHED_CLUSTER
588 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) },
590 #ifdef CONFIG_SCHED_MC
591 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
593 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
598 * Set if a package/die has multiple NUMA nodes inside.
599 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
600 * Sub-NUMA Clustering have this.
602 static bool x86_has_numa_in_package;
604 void set_cpu_sibling_map(int cpu)
606 bool has_smt = smp_num_siblings > 1;
607 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
608 struct cpuinfo_x86 *c = &cpu_data(cpu);
609 struct cpuinfo_x86 *o;
612 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
615 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
616 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
617 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu));
618 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
619 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
624 for_each_cpu(i, cpu_sibling_setup_mask) {
627 if (match_pkg(c, o) && !topology_same_node(c, o))
628 x86_has_numa_in_package = true;
630 if ((i == cpu) || (has_smt && match_smt(c, o)))
631 link_mask(topology_sibling_cpumask, cpu, i);
633 if ((i == cpu) || (has_mp && match_llc(c, o)))
634 link_mask(cpu_llc_shared_mask, cpu, i);
636 if ((i == cpu) || (has_mp && match_l2c(c, o)))
637 link_mask(cpu_l2c_shared_mask, cpu, i);
639 if ((i == cpu) || (has_mp && match_die(c, o)))
640 link_mask(topology_die_cpumask, cpu, i);
643 threads = cpumask_weight(topology_sibling_cpumask(cpu));
644 if (threads > __max_smt_threads)
645 __max_smt_threads = threads;
647 for_each_cpu(i, topology_sibling_cpumask(cpu))
648 cpu_data(i).smt_active = threads > 1;
651 * This needs a separate iteration over the cpus because we rely on all
652 * topology_sibling_cpumask links to be set-up.
654 for_each_cpu(i, cpu_sibling_setup_mask) {
657 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
658 link_mask(topology_core_cpumask, cpu, i);
661 * Does this new cpu bringup a new core?
665 * for each core in package, increment
666 * the booted_cores for this new cpu
669 topology_sibling_cpumask(i)) == i)
672 * increment the core count for all
673 * the other cpus in this package
676 cpu_data(i).booted_cores++;
677 } else if (i != cpu && !c->booted_cores)
678 c->booted_cores = cpu_data(i).booted_cores;
683 /* maps the cpu to the sched domain representing multi-core */
684 const struct cpumask *cpu_coregroup_mask(int cpu)
686 return cpu_llc_shared_mask(cpu);
689 const struct cpumask *cpu_clustergroup_mask(int cpu)
691 return cpu_l2c_shared_mask(cpu);
694 static void impress_friends(void)
697 unsigned long bogosum = 0;
699 * Allow the user to impress friends.
701 pr_debug("Before bogomips\n");
702 for_each_possible_cpu(cpu)
703 if (cpumask_test_cpu(cpu, cpu_callout_mask))
704 bogosum += cpu_data(cpu).loops_per_jiffy;
705 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
708 (bogosum/(5000/HZ))%100);
710 pr_debug("Before bogocount - setting activated=1\n");
713 void __inquire_remote_apic(int apicid)
715 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
716 const char * const names[] = { "ID", "VERSION", "SPIV" };
720 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
722 for (i = 0; i < ARRAY_SIZE(regs); i++) {
723 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
728 status = safe_apic_wait_icr_idle();
730 pr_cont("a previous APIC delivery may have failed\n");
732 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
737 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
738 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
741 case APIC_ICR_RR_VALID:
742 status = apic_read(APIC_RRR);
743 pr_cont("%08x\n", status);
752 * The Multiprocessor Specification 1.4 (1997) example code suggests
753 * that there should be a 10ms delay between the BSP asserting INIT
754 * and de-asserting INIT, when starting a remote processor.
755 * But that slows boot and resume on modern processors, which include
756 * many cores and don't require that delay.
758 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
759 * Modern processor families are quirked to remove the delay entirely.
761 #define UDELAY_10MS_DEFAULT 10000
763 static unsigned int init_udelay = UINT_MAX;
765 static int __init cpu_init_udelay(char *str)
767 get_option(&str, &init_udelay);
771 early_param("cpu_init_udelay", cpu_init_udelay);
773 static void __init smp_quirk_init_udelay(void)
775 /* if cmdline changed it from default, leave it alone */
776 if (init_udelay != UINT_MAX)
779 /* if modern processor, use no delay */
780 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
781 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
782 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
786 /* else, use legacy delay */
787 init_udelay = UDELAY_10MS_DEFAULT;
791 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
792 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
793 * won't ... remember to clear down the APIC, etc later.
796 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
798 u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
799 unsigned long send_status, accept_status = 0;
803 /* Boot on the stack */
804 /* Kick the second */
805 apic_icr_write(APIC_DM_NMI | dm, apicid);
807 pr_debug("Waiting for send to finish...\n");
808 send_status = safe_apic_wait_icr_idle();
811 * Give the other CPU some time to accept the IPI.
814 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
815 maxlvt = lapic_get_maxlvt();
816 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
817 apic_write(APIC_ESR, 0);
818 accept_status = (apic_read(APIC_ESR) & 0xEF);
820 pr_debug("NMI sent\n");
823 pr_err("APIC never delivered???\n");
825 pr_err("APIC delivery error (%lx)\n", accept_status);
827 return (send_status | accept_status);
831 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
833 unsigned long send_status = 0, accept_status = 0;
834 int maxlvt, num_starts, j;
836 maxlvt = lapic_get_maxlvt();
839 * Be paranoid about clearing APIC errors.
841 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
842 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
843 apic_write(APIC_ESR, 0);
847 pr_debug("Asserting INIT\n");
850 * Turn INIT on target chip
855 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
858 pr_debug("Waiting for send to finish...\n");
859 send_status = safe_apic_wait_icr_idle();
863 pr_debug("Deasserting INIT\n");
867 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
869 pr_debug("Waiting for send to finish...\n");
870 send_status = safe_apic_wait_icr_idle();
875 * Should we send STARTUP IPIs ?
877 * Determine this based on the APIC version.
878 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
880 if (APIC_INTEGRATED(boot_cpu_apic_version))
886 * Run STARTUP IPI loop.
888 pr_debug("#startup loops: %d\n", num_starts);
890 for (j = 1; j <= num_starts; j++) {
891 pr_debug("Sending STARTUP #%d\n", j);
892 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
893 apic_write(APIC_ESR, 0);
895 pr_debug("After apic_write\n");
902 /* Boot on the stack */
903 /* Kick the second */
904 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
908 * Give the other CPU some time to accept the IPI.
910 if (init_udelay == 0)
915 pr_debug("Startup point 1\n");
917 pr_debug("Waiting for send to finish...\n");
918 send_status = safe_apic_wait_icr_idle();
921 * Give the other CPU some time to accept the IPI.
923 if (init_udelay == 0)
928 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
929 apic_write(APIC_ESR, 0);
930 accept_status = (apic_read(APIC_ESR) & 0xEF);
931 if (send_status || accept_status)
934 pr_debug("After Startup\n");
937 pr_err("APIC never delivered???\n");
939 pr_err("APIC delivery error (%lx)\n", accept_status);
941 return (send_status | accept_status);
944 /* reduce the number of lines printed when booting a large cpu count system */
945 static void announce_cpu(int cpu, int apicid)
947 static int current_node = NUMA_NO_NODE;
948 int node = early_cpu_to_node(cpu);
949 static int width, node_width;
952 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
955 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
958 printk(KERN_INFO "x86: Booting SMP configuration:\n");
960 if (system_state < SYSTEM_RUNNING) {
961 if (node != current_node) {
962 if (current_node > (-1))
966 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
967 node_width - num_digits(node), " ", node);
970 /* Add padding for the BSP */
972 pr_cont("%*s", width + 1, " ");
974 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
977 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
981 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
985 cpu = smp_processor_id();
986 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
993 * Wake up AP by INIT, INIT, STARTUP sequence.
995 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
996 * boot-strap code which is not a desired behavior for waking up BSP. To
997 * void the boot-strap code, wake up CPU0 by NMI instead.
999 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
1000 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
1001 * We'll change this code in the future to wake up hard offlined CPU0 if
1002 * real platform and request are available.
1005 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
1006 int *cpu0_nmi_registered)
1014 * Wake up AP by INIT, INIT, STARTUP sequence.
1017 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
1022 * Wake up BSP by nmi.
1024 * Register a NMI handler to help wake up CPU0.
1026 boot_error = register_nmi_handler(NMI_LOCAL,
1027 wakeup_cpu0_nmi, 0, "wake_cpu0");
1030 enable_start_cpu0 = 1;
1031 *cpu0_nmi_registered = 1;
1032 id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid;
1033 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
1042 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
1046 /* Just in case we booted with a single CPU. */
1047 alternatives_enable_smp();
1049 per_cpu(current_task, cpu) = idle;
1050 cpu_init_stack_canary(cpu, idle);
1052 /* Initialize the interrupt stack(s) */
1053 ret = irq_init_percpu_irqstack(cpu);
1057 #ifdef CONFIG_X86_32
1058 /* Stack for startup_32 can be just as for start_secondary onwards */
1059 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1061 initial_gs = per_cpu_offset(cpu);
1067 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1068 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1069 * Returns zero if CPU booted OK, else error code from
1070 * ->wakeup_secondary_cpu.
1072 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1073 int *cpu0_nmi_registered)
1075 /* start_ip had better be page-aligned! */
1076 unsigned long start_ip = real_mode_header->trampoline_start;
1078 unsigned long boot_error = 0;
1079 unsigned long timeout;
1081 #ifdef CONFIG_X86_64
1082 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
1083 if (apic->wakeup_secondary_cpu_64)
1084 start_ip = real_mode_header->trampoline_start64;
1086 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1087 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1088 initial_code = (unsigned long)start_secondary;
1089 initial_stack = idle->thread.sp;
1091 /* Enable the espfix hack for this CPU */
1092 init_espfix_ap(cpu);
1094 /* So we see what's up */
1095 announce_cpu(cpu, apicid);
1098 * This grunge runs the startup process for
1099 * the targeted processor.
1102 if (x86_platform.legacy.warm_reset) {
1104 pr_debug("Setting warm reset code and vector.\n");
1106 smpboot_setup_warm_reset_vector(start_ip);
1108 * Be paranoid about clearing APIC errors.
1110 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1111 apic_write(APIC_ESR, 0);
1112 apic_read(APIC_ESR);
1117 * AP might wait on cpu_callout_mask in cpu_init() with
1118 * cpu_initialized_mask set if previous attempt to online
1119 * it timed-out. Clear cpu_initialized_mask so that after
1120 * INIT/SIPI it could start with a clean state.
1122 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1126 * Wake up a CPU in difference cases:
1127 * - Use a method from the APIC driver if one defined, with wakeup
1128 * straight to 64-bit mode preferred over wakeup to RM.
1130 * - Use an INIT boot APIC message for APs or NMI for BSP.
1132 if (apic->wakeup_secondary_cpu_64)
1133 boot_error = apic->wakeup_secondary_cpu_64(apicid, start_ip);
1134 else if (apic->wakeup_secondary_cpu)
1135 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1137 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1138 cpu0_nmi_registered);
1142 * Wait 10s total for first sign of life from AP
1145 timeout = jiffies + 10*HZ;
1146 while (time_before(jiffies, timeout)) {
1147 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1149 * Tell AP to proceed with initialization
1151 cpumask_set_cpu(cpu, cpu_callout_mask);
1161 * Wait till AP completes initial initialization
1163 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1165 * Allow other tasks to run while we wait for the
1166 * AP to come online. This also gives a chance
1167 * for the MTRR work(triggered by the AP coming online)
1168 * to be completed in the stop machine context.
1174 if (x86_platform.legacy.warm_reset) {
1176 * Cleanup possible dangling ends...
1178 smpboot_restore_warm_reset_vector();
1184 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1186 int apicid = apic->cpu_present_to_apicid(cpu);
1187 int cpu0_nmi_registered = 0;
1188 unsigned long flags;
1191 lockdep_assert_irqs_enabled();
1193 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1195 if (apicid == BAD_APICID ||
1196 !physid_isset(apicid, phys_cpu_present_map) ||
1197 !apic->apic_id_valid(apicid)) {
1198 pr_err("%s: bad cpu %d\n", __func__, cpu);
1203 * Already booted CPU?
1205 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1206 pr_debug("do_boot_cpu %d Already started\n", cpu);
1211 * Save current MTRR state in case it was changed since early boot
1212 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1216 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1217 err = cpu_check_up_prepare(cpu);
1218 if (err && err != -EBUSY)
1221 /* the FPU context is blank, nobody can own it */
1222 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1224 err = common_cpu_up(cpu, tidle);
1228 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1230 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1236 * Check TSC synchronization with the AP (keep irqs disabled
1239 local_irq_save(flags);
1240 check_tsc_sync_source(cpu);
1241 local_irq_restore(flags);
1243 while (!cpu_online(cpu)) {
1245 touch_nmi_watchdog();
1250 * Clean up the nmi handler. Do this after the callin and callout sync
1251 * to avoid impact of possible long unregister time.
1253 if (cpu0_nmi_registered)
1254 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1260 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1262 void arch_disable_smp_support(void)
1264 disable_ioapic_support();
1268 * Fall back to non SMP mode after errors.
1270 * RED-PEN audit/test this more. I bet there is more state messed up here.
1272 static __init void disable_smp(void)
1274 pr_info("SMP disabled\n");
1276 disable_ioapic_support();
1278 init_cpu_present(cpumask_of(0));
1279 init_cpu_possible(cpumask_of(0));
1281 if (smp_found_config)
1282 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1284 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1285 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1286 cpumask_set_cpu(0, topology_core_cpumask(0));
1287 cpumask_set_cpu(0, topology_die_cpumask(0));
1291 * Various sanity checks.
1293 static void __init smp_sanity_check(void)
1297 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1298 if (def_to_bigsmp && nr_cpu_ids > 8) {
1302 pr_warn("More than 8 CPUs detected - skipping them\n"
1303 "Use CONFIG_X86_BIGSMP\n");
1306 for_each_present_cpu(cpu) {
1308 set_cpu_present(cpu, false);
1313 for_each_possible_cpu(cpu) {
1315 set_cpu_possible(cpu, false);
1323 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1324 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1325 hard_smp_processor_id());
1327 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1331 * Should not be necessary because the MP table should list the boot
1332 * CPU too, but we do it for the sake of robustness anyway.
1334 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1335 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1336 boot_cpu_physical_apicid);
1337 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1342 static void __init smp_cpu_index_default(void)
1345 struct cpuinfo_x86 *c;
1347 for_each_possible_cpu(i) {
1349 /* mark all to hotplug */
1350 c->cpu_index = nr_cpu_ids;
1354 static void __init smp_get_logical_apicid(void)
1357 cpu0_logical_apicid = apic_read(APIC_LDR);
1359 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1362 void __init smp_prepare_cpus_common(void)
1366 smp_cpu_index_default();
1369 * Setup boot CPU information
1371 smp_store_boot_cpu_info(); /* Final full version of the data */
1372 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1375 for_each_possible_cpu(i) {
1376 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1377 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1378 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1379 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1380 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL);
1384 * Set 'default' x86 topology, this matches default_topology() in that
1385 * it has NUMA nodes as a topology level. See also
1386 * native_smp_cpus_done().
1388 * Must be done before set_cpus_sibling_map() is ran.
1390 set_sched_topology(x86_topology);
1392 set_cpu_sibling_map(0);
1396 * Prepare for SMP bootup.
1397 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1398 * for common interface support.
1400 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1402 smp_prepare_cpus_common();
1406 switch (apic_intr_mode) {
1408 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1411 case APIC_SYMMETRIC_IO_NO_ROUTING:
1413 /* Setup local timer */
1414 x86_init.timers.setup_percpu_clockev();
1416 case APIC_VIRTUAL_WIRE:
1417 case APIC_SYMMETRIC_IO:
1421 /* Setup local timer */
1422 x86_init.timers.setup_percpu_clockev();
1424 smp_get_logical_apicid();
1427 print_cpu_info(&cpu_data(0));
1431 set_mtrr_aps_delayed_init();
1433 smp_quirk_init_udelay();
1435 speculative_store_bypass_ht_init();
1437 snp_set_wakeup_secondary_cpu();
1440 void arch_thaw_secondary_cpus_begin(void)
1442 set_mtrr_aps_delayed_init();
1445 void arch_thaw_secondary_cpus_end(void)
1451 * Early setup to make printk work.
1453 void __init native_smp_prepare_boot_cpu(void)
1455 int me = smp_processor_id();
1456 switch_to_new_gdt(me);
1457 /* already set me in cpu_online_mask in boot_cpu_init() */
1458 cpumask_set_cpu(me, cpu_callout_mask);
1459 cpu_set_state_online(me);
1460 native_pv_lock_init();
1463 void __init calculate_max_logical_packages(void)
1468 * Today neither Intel nor AMD support heterogeneous systems so
1469 * extrapolate the boot cpu's data to all packages.
1471 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1472 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1473 pr_info("Max logical packages: %u\n", __max_logical_packages);
1476 void __init native_smp_cpus_done(unsigned int max_cpus)
1478 pr_debug("Boot done\n");
1480 calculate_max_logical_packages();
1482 /* XXX for now assume numa-in-package and hybrid don't overlap */
1483 if (x86_has_numa_in_package)
1484 set_sched_topology(x86_numa_in_package_topology);
1485 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
1486 set_sched_topology(x86_hybrid_topology);
1493 static int __initdata setup_possible_cpus = -1;
1494 static int __init _setup_possible_cpus(char *str)
1496 get_option(&str, &setup_possible_cpus);
1499 early_param("possible_cpus", _setup_possible_cpus);
1503 * cpu_possible_mask should be static, it cannot change as cpu's
1504 * are onlined, or offlined. The reason is per-cpu data-structures
1505 * are allocated by some modules at init time, and don't expect to
1506 * do this dynamically on cpu arrival/departure.
1507 * cpu_present_mask on the other hand can change dynamically.
1508 * In case when cpu_hotplug is not compiled, then we resort to current
1509 * behaviour, which is cpu_possible == cpu_present.
1512 * Three ways to find out the number of additional hotplug CPUs:
1513 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1514 * - The user can overwrite it with possible_cpus=NUM
1515 * - Otherwise don't reserve additional CPUs.
1516 * We do this because additional CPUs waste a lot of memory.
1519 __init void prefill_possible_map(void)
1523 /* No boot processor was found in mptable or ACPI MADT */
1524 if (!num_processors) {
1525 if (boot_cpu_has(X86_FEATURE_APIC)) {
1526 int apicid = boot_cpu_physical_apicid;
1527 int cpu = hard_smp_processor_id();
1529 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1531 /* Make sure boot cpu is enumerated */
1532 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1533 apic->apic_id_valid(apicid))
1534 generic_processor_info(apicid, boot_cpu_apic_version);
1537 if (!num_processors)
1541 i = setup_max_cpus ?: 1;
1542 if (setup_possible_cpus == -1) {
1543 possible = num_processors;
1544 #ifdef CONFIG_HOTPLUG_CPU
1546 possible += disabled_cpus;
1552 possible = setup_possible_cpus;
1554 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1556 /* nr_cpu_ids could be reduced via nr_cpus= */
1557 if (possible > nr_cpu_ids) {
1558 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1559 possible, nr_cpu_ids);
1560 possible = nr_cpu_ids;
1563 #ifdef CONFIG_HOTPLUG_CPU
1564 if (!setup_max_cpus)
1567 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1568 possible, setup_max_cpus);
1572 nr_cpu_ids = possible;
1574 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1575 possible, max_t(int, possible - num_processors, 0));
1577 reset_cpu_possible_mask();
1579 for (i = 0; i < possible; i++)
1580 set_cpu_possible(i, true);
1583 #ifdef CONFIG_HOTPLUG_CPU
1585 /* Recompute SMT state for all CPUs on offline */
1586 static void recompute_smt_state(void)
1588 int max_threads, cpu;
1591 for_each_online_cpu (cpu) {
1592 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1594 if (threads > max_threads)
1595 max_threads = threads;
1597 __max_smt_threads = max_threads;
1600 static void remove_siblinginfo(int cpu)
1603 struct cpuinfo_x86 *c = &cpu_data(cpu);
1605 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1606 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1608 * last thread sibling in this cpu core going down
1610 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1611 cpu_data(sibling).booted_cores--;
1614 for_each_cpu(sibling, topology_die_cpumask(cpu))
1615 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1617 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
1618 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1619 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
1620 cpu_data(sibling).smt_active = false;
1623 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1624 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1625 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
1626 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling));
1627 cpumask_clear(cpu_llc_shared_mask(cpu));
1628 cpumask_clear(cpu_l2c_shared_mask(cpu));
1629 cpumask_clear(topology_sibling_cpumask(cpu));
1630 cpumask_clear(topology_core_cpumask(cpu));
1631 cpumask_clear(topology_die_cpumask(cpu));
1633 c->booted_cores = 0;
1634 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1635 recompute_smt_state();
1638 static void remove_cpu_from_maps(int cpu)
1640 set_cpu_online(cpu, false);
1641 cpumask_clear_cpu(cpu, cpu_callout_mask);
1642 cpumask_clear_cpu(cpu, cpu_callin_mask);
1643 /* was set by cpu_init() */
1644 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1645 numa_remove_cpu(cpu);
1648 void cpu_disable_common(void)
1650 int cpu = smp_processor_id();
1652 remove_siblinginfo(cpu);
1654 /* It's now safe to remove this processor from the online map */
1656 remove_cpu_from_maps(cpu);
1657 unlock_vector_lock();
1662 int native_cpu_disable(void)
1666 ret = lapic_can_unplug_cpu();
1670 cpu_disable_common();
1673 * Disable the local APIC. Otherwise IPI broadcasts will reach
1674 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1677 * Disabling the APIC must happen after cpu_disable_common()
1678 * which invokes fixup_irqs().
1680 * Disabling the APIC preserves already set bits in IRR, but
1681 * an interrupt arriving after disabling the local APIC does not
1682 * set the corresponding IRR bit.
1684 * fixup_irqs() scans IRR for set bits so it can raise a not
1685 * yet handled interrupt on the new destination CPU via an IPI
1686 * but obviously it can't do so for IRR bits which are not set.
1687 * IOW, interrupts arriving after disabling the local APIC will
1690 apic_soft_disable();
1695 int common_cpu_die(unsigned int cpu)
1699 /* We don't do anything here: idle task is faking death itself. */
1701 /* They ack this in play_dead() by setting CPU_DEAD */
1702 if (cpu_wait_death(cpu, 5)) {
1703 if (system_state == SYSTEM_RUNNING)
1704 pr_info("CPU %u is now offline\n", cpu);
1706 pr_err("CPU %u didn't die...\n", cpu);
1713 void native_cpu_die(unsigned int cpu)
1715 common_cpu_die(cpu);
1718 void play_dead_common(void)
1723 (void)cpu_report_death();
1726 * With physical CPU hotplug, we should halt the cpu
1728 local_irq_disable();
1732 * cond_wakeup_cpu0 - Wake up CPU0 if needed.
1734 * If NMI wants to wake up CPU0, start CPU0.
1736 void cond_wakeup_cpu0(void)
1738 if (smp_processor_id() == 0 && enable_start_cpu0)
1741 EXPORT_SYMBOL_GPL(cond_wakeup_cpu0);
1744 * We need to flush the caches before going to sleep, lest we have
1745 * dirty data in our caches when we come back up.
1747 static inline void mwait_play_dead(void)
1749 unsigned int eax, ebx, ecx, edx;
1750 unsigned int highest_cstate = 0;
1751 unsigned int highest_subcstate = 0;
1755 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1756 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1758 if (!this_cpu_has(X86_FEATURE_MWAIT))
1760 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1762 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1765 eax = CPUID_MWAIT_LEAF;
1767 native_cpuid(&eax, &ebx, &ecx, &edx);
1770 * eax will be 0 if EDX enumeration is not valid.
1771 * Initialized below to cstate, sub_cstate value when EDX is valid.
1773 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1776 edx >>= MWAIT_SUBSTATE_SIZE;
1777 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1778 if (edx & MWAIT_SUBSTATE_MASK) {
1780 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1783 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1784 (highest_subcstate - 1);
1788 * This should be a memory location in a cache line which is
1789 * unlikely to be touched by other processors. The actual
1790 * content is immaterial as it is not actually modified in any way.
1792 mwait_ptr = ¤t_thread_info()->flags;
1798 * The CLFLUSH is a workaround for erratum AAI65 for
1799 * the Xeon 7400 series. It's not clear it is actually
1800 * needed, but it should be harmless in either case.
1801 * The WBINVD is insufficient due to the spurious-wakeup
1802 * case where we return around the loop.
1807 __monitor(mwait_ptr, 0, 0);
1815 void hlt_play_dead(void)
1817 if (__this_cpu_read(cpu_info.x86) >= 4)
1827 void native_play_dead(void)
1830 tboot_shutdown(TB_SHUTDOWN_WFS);
1832 mwait_play_dead(); /* Only returns on failure */
1833 if (cpuidle_play_dead())
1837 #else /* ... !CONFIG_HOTPLUG_CPU */
1838 int native_cpu_disable(void)
1843 void native_cpu_die(unsigned int cpu)
1845 /* We said "no" in __cpu_disable */
1849 void native_play_dead(void)