1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/stackprotector.h>
55 #include <linux/gfp.h>
56 #include <linux/cpuidle.h>
57 #include <linux/numa.h>
63 #include <asm/realmode.h>
66 #include <asm/pgtable.h>
67 #include <asm/tlbflush.h>
69 #include <asm/mwait.h>
71 #include <asm/io_apic.h>
72 #include <asm/fpu/internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/i8259.h>
78 #include <asm/qspinlock.h>
79 #include <asm/intel-family.h>
80 #include <asm/cpu_device_id.h>
81 #include <asm/spec-ctrl.h>
82 #include <asm/hw_irq.h>
84 /* representing HT siblings of each logical CPU */
85 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
86 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
88 /* representing HT and core siblings of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
90 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
92 /* representing HT, core, and die siblings of each logical CPU */
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
94 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
98 /* Per CPU bogomips and other parameters */
99 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
100 EXPORT_PER_CPU_SYMBOL(cpu_info);
102 /* Logical package management. We might want to allocate that dynamically */
103 unsigned int __max_logical_packages __read_mostly;
104 EXPORT_SYMBOL(__max_logical_packages);
105 static unsigned int logical_packages __read_mostly;
106 static unsigned int logical_die __read_mostly;
108 /* Maximum number of SMT threads on any online core */
109 int __read_mostly __max_smt_threads = 1;
111 /* Flag to indicate if a complete sched domain rebuild is required */
112 bool x86_topology_update;
114 int arch_update_cpu_topology(void)
116 int retval = x86_topology_update;
118 x86_topology_update = false;
122 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
126 spin_lock_irqsave(&rtc_lock, flags);
127 CMOS_WRITE(0xa, 0xf);
128 spin_unlock_irqrestore(&rtc_lock, flags);
129 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
135 static inline void smpboot_restore_warm_reset_vector(void)
140 * Paranoid: Set warm reset code and vector here back
143 spin_lock_irqsave(&rtc_lock, flags);
145 spin_unlock_irqrestore(&rtc_lock, flags);
147 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
150 static void init_freq_invariance(bool secondary);
153 * Report back to the Boot Processor during boot time or to the caller processor
156 static void smp_callin(void)
161 * If waken up by an INIT in an 82489DX configuration
162 * cpu_callout_mask guarantees we don't get here before
163 * an INIT_deassert IPI reaches our local APIC, so it is
164 * now safe to touch our local APIC.
166 cpuid = smp_processor_id();
169 * the boot CPU has finished the init stage and is spinning
170 * on callin_map until we finish. We are free to set up this
171 * CPU, first the APIC. (this is probably redundant on most
177 * Save our processor parameters. Note: this information
178 * is needed for clock calibration.
180 smp_store_cpu_info(cpuid);
183 * The topology information must be up to date before
184 * calibrate_delay() and notify_cpu_starting().
186 set_cpu_sibling_map(raw_smp_processor_id());
188 init_freq_invariance(true);
192 * Update loops_per_jiffy in cpu_data. Previous call to
193 * smp_store_cpu_info() stored a value that is close but not as
194 * accurate as the value just calculated.
197 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
198 pr_debug("Stack at about %p\n", &cpuid);
202 notify_cpu_starting(cpuid);
205 * Allow the master to continue.
207 cpumask_set_cpu(cpuid, cpu_callin_mask);
210 static int cpu0_logical_apicid;
211 static int enable_start_cpu0;
213 * Activate a secondary processor.
215 static void notrace start_secondary(void *unused)
218 * Don't put *anything* except direct CPU state initialization
219 * before cpu_init(), SMP booting is too fragile that we want to
220 * limit the things done here to the most necessary things.
225 /* switch away from the initial page table */
226 load_cr3(swapper_pg_dir);
231 x86_cpuinit.early_percpu_clock_init();
235 enable_start_cpu0 = 0;
237 /* otherwise gcc will move up smp_processor_id before the cpu_init */
240 * Check TSC synchronization with the boot CPU:
242 check_tsc_sync_target();
244 speculative_store_bypass_ht_init();
247 * Lock vector_lock, set CPU online and bring the vector
248 * allocator online. Online must be set with vector_lock held
249 * to prevent a concurrent irq setup/teardown from seeing a
250 * half valid vector space.
253 set_cpu_online(smp_processor_id(), true);
255 unlock_vector_lock();
256 cpu_set_state_online(smp_processor_id());
257 x86_platform.nmi_init();
259 /* enable local interrupts */
262 /* to prevent fake stack check failure in clock setup */
263 boot_init_stack_canary();
265 x86_cpuinit.setup_percpu_clockev();
268 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
271 * Prevent tail call to cpu_startup_entry() because the stack protector
272 * guard has been changed a couple of function calls up, in
273 * boot_init_stack_canary() and must not be checked before tail calling
276 prevent_tail_call_optimization();
280 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
283 bool topology_is_primary_thread(unsigned int cpu)
285 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
289 * topology_smt_supported - Check whether SMT is supported by the CPUs
291 bool topology_smt_supported(void)
293 return smp_num_siblings > 1;
297 * topology_phys_to_logical_pkg - Map a physical package id to a logical
299 * Returns logical package id or -1 if not found
301 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
305 for_each_possible_cpu(cpu) {
306 struct cpuinfo_x86 *c = &cpu_data(cpu);
308 if (c->initialized && c->phys_proc_id == phys_pkg)
309 return c->logical_proc_id;
313 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
315 * topology_phys_to_logical_die - Map a physical die id to logical
317 * Returns logical die id or -1 if not found
319 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
322 int proc_id = cpu_data(cur_cpu).phys_proc_id;
324 for_each_possible_cpu(cpu) {
325 struct cpuinfo_x86 *c = &cpu_data(cpu);
327 if (c->initialized && c->cpu_die_id == die_id &&
328 c->phys_proc_id == proc_id)
329 return c->logical_die_id;
333 EXPORT_SYMBOL(topology_phys_to_logical_die);
336 * topology_update_package_map - Update the physical to logical package map
337 * @pkg: The physical package id as retrieved via CPUID
338 * @cpu: The cpu for which this is updated
340 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
344 /* Already available somewhere? */
345 new = topology_phys_to_logical_pkg(pkg);
349 new = logical_packages++;
351 pr_info("CPU %u Converting physical %u to logical package %u\n",
355 cpu_data(cpu).logical_proc_id = new;
359 * topology_update_die_map - Update the physical to logical die map
360 * @die: The die id as retrieved via CPUID
361 * @cpu: The cpu for which this is updated
363 int topology_update_die_map(unsigned int die, unsigned int cpu)
367 /* Already available somewhere? */
368 new = topology_phys_to_logical_die(die, cpu);
374 pr_info("CPU %u Converting physical %u to logical die %u\n",
378 cpu_data(cpu).logical_die_id = new;
382 void __init smp_store_boot_cpu_info(void)
384 int id = 0; /* CPU 0 */
385 struct cpuinfo_x86 *c = &cpu_data(id);
389 topology_update_package_map(c->phys_proc_id, id);
390 topology_update_die_map(c->cpu_die_id, id);
391 c->initialized = true;
395 * The bootstrap kernel entry code has set these up. Save them for
398 void smp_store_cpu_info(int id)
400 struct cpuinfo_x86 *c = &cpu_data(id);
402 /* Copy boot_cpu_data only on the first bringup */
407 * During boot time, CPU0 has this setup already. Save the info when
408 * bringing up AP or offlined CPU0.
410 identify_secondary_cpu(c);
411 c->initialized = true;
415 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
417 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
419 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
423 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
425 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
427 return !WARN_ONCE(!topology_same_node(c, o),
428 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
429 "[node: %d != %d]. Ignoring dependency.\n",
430 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
433 #define link_mask(mfunc, c1, c2) \
435 cpumask_set_cpu((c1), mfunc(c2)); \
436 cpumask_set_cpu((c2), mfunc(c1)); \
439 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
441 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
442 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
444 if (c->phys_proc_id == o->phys_proc_id &&
445 c->cpu_die_id == o->cpu_die_id &&
446 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
447 if (c->cpu_core_id == o->cpu_core_id)
448 return topology_sane(c, o, "smt");
450 if ((c->cu_id != 0xff) &&
451 (o->cu_id != 0xff) &&
452 (c->cu_id == o->cu_id))
453 return topology_sane(c, o, "smt");
456 } else if (c->phys_proc_id == o->phys_proc_id &&
457 c->cpu_die_id == o->cpu_die_id &&
458 c->cpu_core_id == o->cpu_core_id) {
459 return topology_sane(c, o, "smt");
466 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
468 * These are Intel CPUs that enumerate an LLC that is shared by
469 * multiple NUMA nodes. The LLC on these systems is shared for
470 * off-package data access but private to the NUMA node (half
471 * of the package) for on-package access.
473 * CPUID (the source of the information about the LLC) can only
474 * enumerate the cache as being shared *or* unshared, but not
475 * this particular configuration. The CPU in this case enumerates
476 * the cache to be shared across the entire package (spanning both
480 static const struct x86_cpu_id snc_cpu[] = {
481 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL),
485 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
487 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
489 /* Do not match if we do not have a valid APICID for cpu: */
490 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
493 /* Do not match if LLC id does not match: */
494 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
498 * Allow the SNC topology without warning. Return of false
499 * means 'c' does not share the LLC of 'o'. This will be
500 * reflected to userspace.
502 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
505 return topology_sane(c, o, "llc");
509 * Unlike the other levels, we do not enforce keeping a
510 * multicore group inside a NUMA node. If this happens, we will
511 * discard the MC level of the topology later.
513 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
515 if (c->phys_proc_id == o->phys_proc_id)
520 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
522 if ((c->phys_proc_id == o->phys_proc_id) &&
523 (c->cpu_die_id == o->cpu_die_id))
529 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
530 static inline int x86_sched_itmt_flags(void)
532 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
535 #ifdef CONFIG_SCHED_MC
536 static int x86_core_flags(void)
538 return cpu_core_flags() | x86_sched_itmt_flags();
541 #ifdef CONFIG_SCHED_SMT
542 static int x86_smt_flags(void)
544 return cpu_smt_flags() | x86_sched_itmt_flags();
549 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
550 #ifdef CONFIG_SCHED_SMT
551 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
553 #ifdef CONFIG_SCHED_MC
554 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
559 static struct sched_domain_topology_level x86_topology[] = {
560 #ifdef CONFIG_SCHED_SMT
561 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
563 #ifdef CONFIG_SCHED_MC
564 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
566 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
571 * Set if a package/die has multiple NUMA nodes inside.
572 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
573 * Sub-NUMA Clustering have this.
575 static bool x86_has_numa_in_package;
577 void set_cpu_sibling_map(int cpu)
579 bool has_smt = smp_num_siblings > 1;
580 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
581 struct cpuinfo_x86 *c = &cpu_data(cpu);
582 struct cpuinfo_x86 *o;
585 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
588 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
589 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
590 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
591 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
596 for_each_cpu(i, cpu_sibling_setup_mask) {
599 if ((i == cpu) || (has_smt && match_smt(c, o)))
600 link_mask(topology_sibling_cpumask, cpu, i);
602 if ((i == cpu) || (has_mp && match_llc(c, o)))
603 link_mask(cpu_llc_shared_mask, cpu, i);
608 * This needs a separate iteration over the cpus because we rely on all
609 * topology_sibling_cpumask links to be set-up.
611 for_each_cpu(i, cpu_sibling_setup_mask) {
614 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
615 link_mask(topology_core_cpumask, cpu, i);
618 * Does this new cpu bringup a new core?
621 topology_sibling_cpumask(cpu)) == 1) {
623 * for each core in package, increment
624 * the booted_cores for this new cpu
627 topology_sibling_cpumask(i)) == i)
630 * increment the core count for all
631 * the other cpus in this package
634 cpu_data(i).booted_cores++;
635 } else if (i != cpu && !c->booted_cores)
636 c->booted_cores = cpu_data(i).booted_cores;
638 if (match_pkg(c, o) && !topology_same_node(c, o))
639 x86_has_numa_in_package = true;
641 if ((i == cpu) || (has_mp && match_die(c, o)))
642 link_mask(topology_die_cpumask, cpu, i);
645 threads = cpumask_weight(topology_sibling_cpumask(cpu));
646 if (threads > __max_smt_threads)
647 __max_smt_threads = threads;
650 /* maps the cpu to the sched domain representing multi-core */
651 const struct cpumask *cpu_coregroup_mask(int cpu)
653 return cpu_llc_shared_mask(cpu);
656 static void impress_friends(void)
659 unsigned long bogosum = 0;
661 * Allow the user to impress friends.
663 pr_debug("Before bogomips\n");
664 for_each_possible_cpu(cpu)
665 if (cpumask_test_cpu(cpu, cpu_callout_mask))
666 bogosum += cpu_data(cpu).loops_per_jiffy;
667 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
670 (bogosum/(5000/HZ))%100);
672 pr_debug("Before bogocount - setting activated=1\n");
675 void __inquire_remote_apic(int apicid)
677 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
678 const char * const names[] = { "ID", "VERSION", "SPIV" };
682 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
684 for (i = 0; i < ARRAY_SIZE(regs); i++) {
685 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
690 status = safe_apic_wait_icr_idle();
692 pr_cont("a previous APIC delivery may have failed\n");
694 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
699 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
700 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
703 case APIC_ICR_RR_VALID:
704 status = apic_read(APIC_RRR);
705 pr_cont("%08x\n", status);
714 * The Multiprocessor Specification 1.4 (1997) example code suggests
715 * that there should be a 10ms delay between the BSP asserting INIT
716 * and de-asserting INIT, when starting a remote processor.
717 * But that slows boot and resume on modern processors, which include
718 * many cores and don't require that delay.
720 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
721 * Modern processor families are quirked to remove the delay entirely.
723 #define UDELAY_10MS_DEFAULT 10000
725 static unsigned int init_udelay = UINT_MAX;
727 static int __init cpu_init_udelay(char *str)
729 get_option(&str, &init_udelay);
733 early_param("cpu_init_udelay", cpu_init_udelay);
735 static void __init smp_quirk_init_udelay(void)
737 /* if cmdline changed it from default, leave it alone */
738 if (init_udelay != UINT_MAX)
741 /* if modern processor, use no delay */
742 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
743 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
744 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
748 /* else, use legacy delay */
749 init_udelay = UDELAY_10MS_DEFAULT;
753 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
754 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
755 * won't ... remember to clear down the APIC, etc later.
758 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
760 unsigned long send_status, accept_status = 0;
764 /* Boot on the stack */
765 /* Kick the second */
766 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
768 pr_debug("Waiting for send to finish...\n");
769 send_status = safe_apic_wait_icr_idle();
772 * Give the other CPU some time to accept the IPI.
775 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
776 maxlvt = lapic_get_maxlvt();
777 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
778 apic_write(APIC_ESR, 0);
779 accept_status = (apic_read(APIC_ESR) & 0xEF);
781 pr_debug("NMI sent\n");
784 pr_err("APIC never delivered???\n");
786 pr_err("APIC delivery error (%lx)\n", accept_status);
788 return (send_status | accept_status);
792 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
794 unsigned long send_status = 0, accept_status = 0;
795 int maxlvt, num_starts, j;
797 maxlvt = lapic_get_maxlvt();
800 * Be paranoid about clearing APIC errors.
802 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
803 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
804 apic_write(APIC_ESR, 0);
808 pr_debug("Asserting INIT\n");
811 * Turn INIT on target chip
816 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
819 pr_debug("Waiting for send to finish...\n");
820 send_status = safe_apic_wait_icr_idle();
824 pr_debug("Deasserting INIT\n");
828 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
830 pr_debug("Waiting for send to finish...\n");
831 send_status = safe_apic_wait_icr_idle();
836 * Should we send STARTUP IPIs ?
838 * Determine this based on the APIC version.
839 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
841 if (APIC_INTEGRATED(boot_cpu_apic_version))
847 * Run STARTUP IPI loop.
849 pr_debug("#startup loops: %d\n", num_starts);
851 for (j = 1; j <= num_starts; j++) {
852 pr_debug("Sending STARTUP #%d\n", j);
853 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
854 apic_write(APIC_ESR, 0);
856 pr_debug("After apic_write\n");
863 /* Boot on the stack */
864 /* Kick the second */
865 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
869 * Give the other CPU some time to accept the IPI.
871 if (init_udelay == 0)
876 pr_debug("Startup point 1\n");
878 pr_debug("Waiting for send to finish...\n");
879 send_status = safe_apic_wait_icr_idle();
882 * Give the other CPU some time to accept the IPI.
884 if (init_udelay == 0)
889 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
890 apic_write(APIC_ESR, 0);
891 accept_status = (apic_read(APIC_ESR) & 0xEF);
892 if (send_status || accept_status)
895 pr_debug("After Startup\n");
898 pr_err("APIC never delivered???\n");
900 pr_err("APIC delivery error (%lx)\n", accept_status);
902 return (send_status | accept_status);
905 /* reduce the number of lines printed when booting a large cpu count system */
906 static void announce_cpu(int cpu, int apicid)
908 static int current_node = NUMA_NO_NODE;
909 int node = early_cpu_to_node(cpu);
910 static int width, node_width;
913 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
916 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
919 printk(KERN_INFO "x86: Booting SMP configuration:\n");
921 if (system_state < SYSTEM_RUNNING) {
922 if (node != current_node) {
923 if (current_node > (-1))
927 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
928 node_width - num_digits(node), " ", node);
931 /* Add padding for the BSP */
933 pr_cont("%*s", width + 1, " ");
935 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
938 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
942 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
946 cpu = smp_processor_id();
947 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
954 * Wake up AP by INIT, INIT, STARTUP sequence.
956 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
957 * boot-strap code which is not a desired behavior for waking up BSP. To
958 * void the boot-strap code, wake up CPU0 by NMI instead.
960 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
961 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
962 * We'll change this code in the future to wake up hard offlined CPU0 if
963 * real platform and request are available.
966 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
967 int *cpu0_nmi_registered)
975 * Wake up AP by INIT, INIT, STARTUP sequence.
978 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
983 * Wake up BSP by nmi.
985 * Register a NMI handler to help wake up CPU0.
987 boot_error = register_nmi_handler(NMI_LOCAL,
988 wakeup_cpu0_nmi, 0, "wake_cpu0");
991 enable_start_cpu0 = 1;
992 *cpu0_nmi_registered = 1;
993 if (apic->dest_logical == APIC_DEST_LOGICAL)
994 id = cpu0_logical_apicid;
997 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
1006 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
1010 /* Just in case we booted with a single CPU. */
1011 alternatives_enable_smp();
1013 per_cpu(current_task, cpu) = idle;
1015 /* Initialize the interrupt stack(s) */
1016 ret = irq_init_percpu_irqstack(cpu);
1020 #ifdef CONFIG_X86_32
1021 /* Stack for startup_32 can be just as for start_secondary onwards */
1022 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1024 initial_gs = per_cpu_offset(cpu);
1030 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1031 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1032 * Returns zero if CPU booted OK, else error code from
1033 * ->wakeup_secondary_cpu.
1035 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1036 int *cpu0_nmi_registered)
1038 /* start_ip had better be page-aligned! */
1039 unsigned long start_ip = real_mode_header->trampoline_start;
1041 unsigned long boot_error = 0;
1042 unsigned long timeout;
1044 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1045 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1046 initial_code = (unsigned long)start_secondary;
1047 initial_stack = idle->thread.sp;
1049 /* Enable the espfix hack for this CPU */
1050 init_espfix_ap(cpu);
1052 /* So we see what's up */
1053 announce_cpu(cpu, apicid);
1056 * This grunge runs the startup process for
1057 * the targeted processor.
1060 if (x86_platform.legacy.warm_reset) {
1062 pr_debug("Setting warm reset code and vector.\n");
1064 smpboot_setup_warm_reset_vector(start_ip);
1066 * Be paranoid about clearing APIC errors.
1068 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1069 apic_write(APIC_ESR, 0);
1070 apic_read(APIC_ESR);
1075 * AP might wait on cpu_callout_mask in cpu_init() with
1076 * cpu_initialized_mask set if previous attempt to online
1077 * it timed-out. Clear cpu_initialized_mask so that after
1078 * INIT/SIPI it could start with a clean state.
1080 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1084 * Wake up a CPU in difference cases:
1085 * - Use the method in the APIC driver if it's defined
1087 * - Use an INIT boot APIC message for APs or NMI for BSP.
1089 if (apic->wakeup_secondary_cpu)
1090 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1092 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1093 cpu0_nmi_registered);
1097 * Wait 10s total for first sign of life from AP
1100 timeout = jiffies + 10*HZ;
1101 while (time_before(jiffies, timeout)) {
1102 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1104 * Tell AP to proceed with initialization
1106 cpumask_set_cpu(cpu, cpu_callout_mask);
1116 * Wait till AP completes initial initialization
1118 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1120 * Allow other tasks to run while we wait for the
1121 * AP to come online. This also gives a chance
1122 * for the MTRR work(triggered by the AP coming online)
1123 * to be completed in the stop machine context.
1129 if (x86_platform.legacy.warm_reset) {
1131 * Cleanup possible dangling ends...
1133 smpboot_restore_warm_reset_vector();
1139 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1141 int apicid = apic->cpu_present_to_apicid(cpu);
1142 int cpu0_nmi_registered = 0;
1143 unsigned long flags;
1146 lockdep_assert_irqs_enabled();
1148 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1150 if (apicid == BAD_APICID ||
1151 !physid_isset(apicid, phys_cpu_present_map) ||
1152 !apic->apic_id_valid(apicid)) {
1153 pr_err("%s: bad cpu %d\n", __func__, cpu);
1158 * Already booted CPU?
1160 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1161 pr_debug("do_boot_cpu %d Already started\n", cpu);
1166 * Save current MTRR state in case it was changed since early boot
1167 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1171 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1172 err = cpu_check_up_prepare(cpu);
1173 if (err && err != -EBUSY)
1176 /* the FPU context is blank, nobody can own it */
1177 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1179 err = common_cpu_up(cpu, tidle);
1183 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1185 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1191 * Check TSC synchronization with the AP (keep irqs disabled
1194 local_irq_save(flags);
1195 check_tsc_sync_source(cpu);
1196 local_irq_restore(flags);
1198 while (!cpu_online(cpu)) {
1200 touch_nmi_watchdog();
1205 * Clean up the nmi handler. Do this after the callin and callout sync
1206 * to avoid impact of possible long unregister time.
1208 if (cpu0_nmi_registered)
1209 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1215 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1217 void arch_disable_smp_support(void)
1219 disable_ioapic_support();
1223 * Fall back to non SMP mode after errors.
1225 * RED-PEN audit/test this more. I bet there is more state messed up here.
1227 static __init void disable_smp(void)
1229 pr_info("SMP disabled\n");
1231 disable_ioapic_support();
1233 init_cpu_present(cpumask_of(0));
1234 init_cpu_possible(cpumask_of(0));
1236 if (smp_found_config)
1237 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1239 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1240 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1241 cpumask_set_cpu(0, topology_core_cpumask(0));
1242 cpumask_set_cpu(0, topology_die_cpumask(0));
1246 * Various sanity checks.
1248 static void __init smp_sanity_check(void)
1252 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1253 if (def_to_bigsmp && nr_cpu_ids > 8) {
1257 pr_warn("More than 8 CPUs detected - skipping them\n"
1258 "Use CONFIG_X86_BIGSMP\n");
1261 for_each_present_cpu(cpu) {
1263 set_cpu_present(cpu, false);
1268 for_each_possible_cpu(cpu) {
1270 set_cpu_possible(cpu, false);
1278 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1279 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1280 hard_smp_processor_id());
1282 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1286 * Should not be necessary because the MP table should list the boot
1287 * CPU too, but we do it for the sake of robustness anyway.
1289 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1290 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1291 boot_cpu_physical_apicid);
1292 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1297 static void __init smp_cpu_index_default(void)
1300 struct cpuinfo_x86 *c;
1302 for_each_possible_cpu(i) {
1304 /* mark all to hotplug */
1305 c->cpu_index = nr_cpu_ids;
1309 static void __init smp_get_logical_apicid(void)
1312 cpu0_logical_apicid = apic_read(APIC_LDR);
1314 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1318 * Prepare for SMP bootup.
1319 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1320 * for common interface support.
1322 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1326 smp_cpu_index_default();
1329 * Setup boot CPU information
1331 smp_store_boot_cpu_info(); /* Final full version of the data */
1332 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1335 for_each_possible_cpu(i) {
1336 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1337 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1338 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1339 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1343 * Set 'default' x86 topology, this matches default_topology() in that
1344 * it has NUMA nodes as a topology level. See also
1345 * native_smp_cpus_done().
1347 * Must be done before set_cpus_sibling_map() is ran.
1349 set_sched_topology(x86_topology);
1351 set_cpu_sibling_map(0);
1352 init_freq_invariance(false);
1355 switch (apic_intr_mode) {
1357 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1360 case APIC_SYMMETRIC_IO_NO_ROUTING:
1362 /* Setup local timer */
1363 x86_init.timers.setup_percpu_clockev();
1365 case APIC_VIRTUAL_WIRE:
1366 case APIC_SYMMETRIC_IO:
1370 /* Setup local timer */
1371 x86_init.timers.setup_percpu_clockev();
1373 smp_get_logical_apicid();
1376 print_cpu_info(&cpu_data(0));
1380 set_mtrr_aps_delayed_init();
1382 smp_quirk_init_udelay();
1384 speculative_store_bypass_ht_init();
1387 void arch_enable_nonboot_cpus_begin(void)
1389 set_mtrr_aps_delayed_init();
1392 void arch_enable_nonboot_cpus_end(void)
1398 * Early setup to make printk work.
1400 void __init native_smp_prepare_boot_cpu(void)
1402 int me = smp_processor_id();
1403 switch_to_new_gdt(me);
1404 /* already set me in cpu_online_mask in boot_cpu_init() */
1405 cpumask_set_cpu(me, cpu_callout_mask);
1406 cpu_set_state_online(me);
1407 native_pv_lock_init();
1410 void __init calculate_max_logical_packages(void)
1415 * Today neither Intel nor AMD support heterogenous systems so
1416 * extrapolate the boot cpu's data to all packages.
1418 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1419 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1420 pr_info("Max logical packages: %u\n", __max_logical_packages);
1423 void __init native_smp_cpus_done(unsigned int max_cpus)
1425 pr_debug("Boot done\n");
1427 calculate_max_logical_packages();
1429 if (x86_has_numa_in_package)
1430 set_sched_topology(x86_numa_in_package_topology);
1437 static int __initdata setup_possible_cpus = -1;
1438 static int __init _setup_possible_cpus(char *str)
1440 get_option(&str, &setup_possible_cpus);
1443 early_param("possible_cpus", _setup_possible_cpus);
1447 * cpu_possible_mask should be static, it cannot change as cpu's
1448 * are onlined, or offlined. The reason is per-cpu data-structures
1449 * are allocated by some modules at init time, and don't expect to
1450 * do this dynamically on cpu arrival/departure.
1451 * cpu_present_mask on the other hand can change dynamically.
1452 * In case when cpu_hotplug is not compiled, then we resort to current
1453 * behaviour, which is cpu_possible == cpu_present.
1456 * Three ways to find out the number of additional hotplug CPUs:
1457 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1458 * - The user can overwrite it with possible_cpus=NUM
1459 * - Otherwise don't reserve additional CPUs.
1460 * We do this because additional CPUs waste a lot of memory.
1463 __init void prefill_possible_map(void)
1467 /* No boot processor was found in mptable or ACPI MADT */
1468 if (!num_processors) {
1469 if (boot_cpu_has(X86_FEATURE_APIC)) {
1470 int apicid = boot_cpu_physical_apicid;
1471 int cpu = hard_smp_processor_id();
1473 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1475 /* Make sure boot cpu is enumerated */
1476 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1477 apic->apic_id_valid(apicid))
1478 generic_processor_info(apicid, boot_cpu_apic_version);
1481 if (!num_processors)
1485 i = setup_max_cpus ?: 1;
1486 if (setup_possible_cpus == -1) {
1487 possible = num_processors;
1488 #ifdef CONFIG_HOTPLUG_CPU
1490 possible += disabled_cpus;
1496 possible = setup_possible_cpus;
1498 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1500 /* nr_cpu_ids could be reduced via nr_cpus= */
1501 if (possible > nr_cpu_ids) {
1502 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1503 possible, nr_cpu_ids);
1504 possible = nr_cpu_ids;
1507 #ifdef CONFIG_HOTPLUG_CPU
1508 if (!setup_max_cpus)
1511 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1512 possible, setup_max_cpus);
1516 nr_cpu_ids = possible;
1518 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1519 possible, max_t(int, possible - num_processors, 0));
1521 reset_cpu_possible_mask();
1523 for (i = 0; i < possible; i++)
1524 set_cpu_possible(i, true);
1527 #ifdef CONFIG_HOTPLUG_CPU
1529 /* Recompute SMT state for all CPUs on offline */
1530 static void recompute_smt_state(void)
1532 int max_threads, cpu;
1535 for_each_online_cpu (cpu) {
1536 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1538 if (threads > max_threads)
1539 max_threads = threads;
1541 __max_smt_threads = max_threads;
1544 static void remove_siblinginfo(int cpu)
1547 struct cpuinfo_x86 *c = &cpu_data(cpu);
1549 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1550 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1552 * last thread sibling in this cpu core going down
1554 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1555 cpu_data(sibling).booted_cores--;
1558 for_each_cpu(sibling, topology_die_cpumask(cpu))
1559 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1560 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1561 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1562 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1563 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1564 cpumask_clear(cpu_llc_shared_mask(cpu));
1565 cpumask_clear(topology_sibling_cpumask(cpu));
1566 cpumask_clear(topology_core_cpumask(cpu));
1567 cpumask_clear(topology_die_cpumask(cpu));
1569 c->booted_cores = 0;
1570 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1571 recompute_smt_state();
1574 static void remove_cpu_from_maps(int cpu)
1576 set_cpu_online(cpu, false);
1577 cpumask_clear_cpu(cpu, cpu_callout_mask);
1578 cpumask_clear_cpu(cpu, cpu_callin_mask);
1579 /* was set by cpu_init() */
1580 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1581 numa_remove_cpu(cpu);
1584 void cpu_disable_common(void)
1586 int cpu = smp_processor_id();
1588 remove_siblinginfo(cpu);
1590 /* It's now safe to remove this processor from the online map */
1592 remove_cpu_from_maps(cpu);
1593 unlock_vector_lock();
1598 int native_cpu_disable(void)
1602 ret = lapic_can_unplug_cpu();
1607 * Disable the local APIC. Otherwise IPI broadcasts will reach
1608 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1611 apic_soft_disable();
1612 cpu_disable_common();
1617 int common_cpu_die(unsigned int cpu)
1621 /* We don't do anything here: idle task is faking death itself. */
1623 /* They ack this in play_dead() by setting CPU_DEAD */
1624 if (cpu_wait_death(cpu, 5)) {
1625 if (system_state == SYSTEM_RUNNING)
1626 pr_info("CPU %u is now offline\n", cpu);
1628 pr_err("CPU %u didn't die...\n", cpu);
1635 void native_cpu_die(unsigned int cpu)
1637 common_cpu_die(cpu);
1640 void play_dead_common(void)
1645 (void)cpu_report_death();
1648 * With physical CPU hotplug, we should halt the cpu
1650 local_irq_disable();
1653 static bool wakeup_cpu0(void)
1655 if (smp_processor_id() == 0 && enable_start_cpu0)
1662 * We need to flush the caches before going to sleep, lest we have
1663 * dirty data in our caches when we come back up.
1665 static inline void mwait_play_dead(void)
1667 unsigned int eax, ebx, ecx, edx;
1668 unsigned int highest_cstate = 0;
1669 unsigned int highest_subcstate = 0;
1673 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1674 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1676 if (!this_cpu_has(X86_FEATURE_MWAIT))
1678 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1680 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1683 eax = CPUID_MWAIT_LEAF;
1685 native_cpuid(&eax, &ebx, &ecx, &edx);
1688 * eax will be 0 if EDX enumeration is not valid.
1689 * Initialized below to cstate, sub_cstate value when EDX is valid.
1691 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1694 edx >>= MWAIT_SUBSTATE_SIZE;
1695 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1696 if (edx & MWAIT_SUBSTATE_MASK) {
1698 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1701 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1702 (highest_subcstate - 1);
1706 * This should be a memory location in a cache line which is
1707 * unlikely to be touched by other processors. The actual
1708 * content is immaterial as it is not actually modified in any way.
1710 mwait_ptr = ¤t_thread_info()->flags;
1716 * The CLFLUSH is a workaround for erratum AAI65 for
1717 * the Xeon 7400 series. It's not clear it is actually
1718 * needed, but it should be harmless in either case.
1719 * The WBINVD is insufficient due to the spurious-wakeup
1720 * case where we return around the loop.
1725 __monitor(mwait_ptr, 0, 0);
1729 * If NMI wants to wake up CPU0, start CPU0.
1736 void hlt_play_dead(void)
1738 if (__this_cpu_read(cpu_info.x86) >= 4)
1744 * If NMI wants to wake up CPU0, start CPU0.
1751 void native_play_dead(void)
1754 tboot_shutdown(TB_SHUTDOWN_WFS);
1756 mwait_play_dead(); /* Only returns on failure */
1757 if (cpuidle_play_dead())
1761 #else /* ... !CONFIG_HOTPLUG_CPU */
1762 int native_cpu_disable(void)
1767 void native_cpu_die(unsigned int cpu)
1769 /* We said "no" in __cpu_disable */
1773 void native_play_dead(void)
1781 * APERF/MPERF frequency ratio computation.
1783 * The scheduler wants to do frequency invariant accounting and needs a <1
1784 * ratio to account for the 'current' frequency, corresponding to
1785 * freq_curr / freq_max.
1787 * Since the frequency freq_curr on x86 is controlled by micro-controller and
1788 * our P-state setting is little more than a request/hint, we need to observe
1789 * the effective frequency 'BusyMHz', i.e. the average frequency over a time
1790 * interval after discarding idle time. This is given by:
1792 * BusyMHz = delta_APERF / delta_MPERF * freq_base
1794 * where freq_base is the max non-turbo P-state.
1796 * The freq_max term has to be set to a somewhat arbitrary value, because we
1797 * can't know which turbo states will be available at a given point in time:
1798 * it all depends on the thermal headroom of the entire package. We set it to
1799 * the turbo level with 4 cores active.
1801 * Benchmarks show that's a good compromise between the 1C turbo ratio
1802 * (freq_curr/freq_max would rarely reach 1) and something close to freq_base,
1803 * which would ignore the entire turbo range (a conspicuous part, making
1804 * freq_curr/freq_max always maxed out).
1806 * An exception to the heuristic above is the Atom uarch, where we choose the
1807 * highest turbo level for freq_max since Atom's are generally oriented towards
1810 * Setting freq_max to anything less than the 1C turbo ratio makes the ratio
1811 * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1.
1814 DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key);
1816 static DEFINE_PER_CPU(u64, arch_prev_aperf);
1817 static DEFINE_PER_CPU(u64, arch_prev_mperf);
1818 static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE;
1819 static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE;
1821 void arch_set_max_freq_ratio(bool turbo_disabled)
1823 arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE :
1824 arch_turbo_freq_ratio;
1827 static bool turbo_disabled(void)
1832 err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en);
1836 return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
1839 static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1843 err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq);
1847 err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq);
1851 *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */
1852 *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */
1857 #include <asm/cpu_device_id.h>
1858 #include <asm/intel-family.h>
1860 #define ICPU(model) \
1861 {X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF, 0}
1863 static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = {
1864 ICPU(INTEL_FAM6_XEON_PHI_KNL),
1865 ICPU(INTEL_FAM6_XEON_PHI_KNM),
1869 static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = {
1870 ICPU(INTEL_FAM6_SKYLAKE_X),
1874 static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = {
1875 ICPU(INTEL_FAM6_ATOM_GOLDMONT),
1876 ICPU(INTEL_FAM6_ATOM_GOLDMONT_D),
1877 ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS),
1881 static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq,
1882 int num_delta_fratio)
1884 int fratio, delta_fratio, found;
1888 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1892 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1894 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1898 fratio = (msr >> 8) & 0xFF;
1902 if (found >= num_delta_fratio) {
1903 *turbo_freq = fratio;
1907 delta_fratio = (msr >> (i + 5)) & 0x7;
1911 fratio -= delta_fratio;
1920 static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size)
1926 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1930 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1932 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios);
1936 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts);
1940 for (i = 0; i < 64; i += 8) {
1941 group_size = (counts >> i) & 0xFF;
1942 if (group_size >= size) {
1943 *turbo_freq = (ratios >> i) & 0xFF;
1951 static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1956 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1960 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1964 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1965 *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */
1967 /* The CPU may have less than 4 cores */
1969 *turbo_freq = msr & 0xFF; /* 1C turbo */
1974 static bool intel_set_max_freq_ratio(void)
1976 u64 base_freq, turbo_freq;
1978 if (slv_set_max_freq_ratio(&base_freq, &turbo_freq))
1981 if (x86_match_cpu(has_glm_turbo_ratio_limits) &&
1982 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
1985 if (x86_match_cpu(has_knl_turbo_ratio_limits) &&
1986 knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
1989 if (x86_match_cpu(has_skx_turbo_ratio_limits) &&
1990 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4))
1993 if (core_set_max_freq_ratio(&base_freq, &turbo_freq))
2000 * Some hypervisors advertise X86_FEATURE_APERFMPERF
2001 * but then fill all MSR's with zeroes.
2004 pr_debug("Couldn't determine cpu base frequency, necessary for scale-invariant accounting.\n");
2008 arch_turbo_freq_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE,
2010 arch_set_max_freq_ratio(turbo_disabled());
2014 static void init_counter_refs(void)
2018 rdmsrl(MSR_IA32_APERF, aperf);
2019 rdmsrl(MSR_IA32_MPERF, mperf);
2021 this_cpu_write(arch_prev_aperf, aperf);
2022 this_cpu_write(arch_prev_mperf, mperf);
2025 static void init_freq_invariance(bool secondary)
2029 if (!boot_cpu_has(X86_FEATURE_APERFMPERF))
2033 if (static_branch_likely(&arch_scale_freq_key)) {
2034 init_counter_refs();
2039 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2040 ret = intel_set_max_freq_ratio();
2043 init_counter_refs();
2044 static_branch_enable(&arch_scale_freq_key);
2046 pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n");
2050 DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE;
2052 void arch_scale_freq_tick(void)
2058 if (!arch_scale_freq_invariant())
2061 rdmsrl(MSR_IA32_APERF, aperf);
2062 rdmsrl(MSR_IA32_MPERF, mperf);
2064 acnt = aperf - this_cpu_read(arch_prev_aperf);
2065 mcnt = mperf - this_cpu_read(arch_prev_mperf);
2069 this_cpu_write(arch_prev_aperf, aperf);
2070 this_cpu_write(arch_prev_mperf, mperf);
2072 acnt <<= 2*SCHED_CAPACITY_SHIFT;
2073 mcnt *= arch_max_freq_ratio;
2075 freq_scale = div64_u64(acnt, mcnt);
2077 if (freq_scale > SCHED_CAPACITY_SCALE)
2078 freq_scale = SCHED_CAPACITY_SCALE;
2080 this_cpu_write(arch_freq_scale, freq_scale);