2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
79 #include <asm/qspinlock.h>
80 #include <asm/intel-family.h>
81 #include <asm/cpu_device_id.h>
83 /* Number of siblings per CPU package */
84 int smp_num_siblings = 1;
85 EXPORT_SYMBOL(smp_num_siblings);
87 /* Last level cache ID of each logical CPU */
88 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
90 /* representing HT siblings of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
92 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
94 /* representing HT and core siblings of each logical CPU */
95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
96 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
98 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
100 /* Per CPU bogomips and other parameters */
101 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
102 EXPORT_PER_CPU_SYMBOL(cpu_info);
104 /* Logical package management. We might want to allocate that dynamically */
105 unsigned int __max_logical_packages __read_mostly;
106 EXPORT_SYMBOL(__max_logical_packages);
107 static unsigned int logical_packages __read_mostly;
109 /* Maximum number of SMT threads on any online core */
110 int __read_mostly __max_smt_threads = 1;
112 /* Flag to indicate if a complete sched domain rebuild is required */
113 bool x86_topology_update;
115 int arch_update_cpu_topology(void)
117 int retval = x86_topology_update;
119 x86_topology_update = false;
123 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
127 spin_lock_irqsave(&rtc_lock, flags);
128 CMOS_WRITE(0xa, 0xf);
129 spin_unlock_irqrestore(&rtc_lock, flags);
130 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
132 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
136 static inline void smpboot_restore_warm_reset_vector(void)
141 * Paranoid: Set warm reset code and vector here back
144 spin_lock_irqsave(&rtc_lock, flags);
146 spin_unlock_irqrestore(&rtc_lock, flags);
148 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
152 * Report back to the Boot Processor during boot time or to the caller processor
155 static void smp_callin(void)
160 * If waken up by an INIT in an 82489DX configuration
161 * cpu_callout_mask guarantees we don't get here before
162 * an INIT_deassert IPI reaches our local APIC, so it is
163 * now safe to touch our local APIC.
165 cpuid = smp_processor_id();
168 * (This works even if the APIC is not enabled.)
170 phys_id = read_apic_id();
173 * the boot CPU has finished the init stage and is spinning
174 * on callin_map until we finish. We are free to set up this
175 * CPU, first the APIC. (this is probably redundant on most
181 * Save our processor parameters. Note: this information
182 * is needed for clock calibration.
184 smp_store_cpu_info(cpuid);
187 * The topology information must be up to date before
188 * calibrate_delay() and notify_cpu_starting().
190 set_cpu_sibling_map(raw_smp_processor_id());
194 * Update loops_per_jiffy in cpu_data. Previous call to
195 * smp_store_cpu_info() stored a value that is close but not as
196 * accurate as the value just calculated.
199 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
200 pr_debug("Stack at about %p\n", &cpuid);
204 notify_cpu_starting(cpuid);
207 * Allow the master to continue.
209 cpumask_set_cpu(cpuid, cpu_callin_mask);
212 static int cpu0_logical_apicid;
213 static int enable_start_cpu0;
215 * Activate a secondary processor.
217 static void notrace start_secondary(void *unused)
220 * Don't put *anything* except direct CPU state initialization
221 * before cpu_init(), SMP booting is too fragile that we want to
222 * limit the things done here to the most necessary things.
224 if (boot_cpu_has(X86_FEATURE_PCID))
225 __write_cr4(__read_cr4() | X86_CR4_PCIDE);
228 /* switch away from the initial page table */
229 load_cr3(swapper_pg_dir);
234 x86_cpuinit.early_percpu_clock_init();
238 enable_start_cpu0 = 0;
240 /* otherwise gcc will move up smp_processor_id before the cpu_init */
243 * Check TSC synchronization with the boot CPU:
245 check_tsc_sync_target();
248 * Lock vector_lock, set CPU online and bring the vector
249 * allocator online. Online must be set with vector_lock held
250 * to prevent a concurrent irq setup/teardown from seeing a
251 * half valid vector space.
254 set_cpu_online(smp_processor_id(), true);
256 unlock_vector_lock();
257 cpu_set_state_online(smp_processor_id());
258 x86_platform.nmi_init();
260 /* enable local interrupts */
263 /* to prevent fake stack check failure in clock setup */
264 boot_init_stack_canary();
266 x86_cpuinit.setup_percpu_clockev();
269 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
273 * topology_phys_to_logical_pkg - Map a physical package id to a logical
275 * Returns logical package id or -1 if not found
277 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
281 for_each_possible_cpu(cpu) {
282 struct cpuinfo_x86 *c = &cpu_data(cpu);
284 if (c->initialized && c->phys_proc_id == phys_pkg)
285 return c->logical_proc_id;
289 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
292 * topology_update_package_map - Update the physical to logical package map
293 * @pkg: The physical package id as retrieved via CPUID
294 * @cpu: The cpu for which this is updated
296 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
300 /* Already available somewhere? */
301 new = topology_phys_to_logical_pkg(pkg);
305 new = logical_packages++;
307 pr_info("CPU %u Converting physical %u to logical package %u\n",
311 cpu_data(cpu).logical_proc_id = new;
315 void __init smp_store_boot_cpu_info(void)
317 int id = 0; /* CPU 0 */
318 struct cpuinfo_x86 *c = &cpu_data(id);
322 topology_update_package_map(c->phys_proc_id, id);
323 c->initialized = true;
327 * The bootstrap kernel entry code has set these up. Save them for
330 void smp_store_cpu_info(int id)
332 struct cpuinfo_x86 *c = &cpu_data(id);
334 /* Copy boot_cpu_data only on the first bringup */
339 * During boot time, CPU0 has this setup already. Save the info when
340 * bringing up AP or offlined CPU0.
342 identify_secondary_cpu(c);
343 c->initialized = true;
347 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
349 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
351 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
355 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
357 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
359 return !WARN_ONCE(!topology_same_node(c, o),
360 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
361 "[node: %d != %d]. Ignoring dependency.\n",
362 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
365 #define link_mask(mfunc, c1, c2) \
367 cpumask_set_cpu((c1), mfunc(c2)); \
368 cpumask_set_cpu((c2), mfunc(c1)); \
371 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
373 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
374 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
376 if (c->phys_proc_id == o->phys_proc_id &&
377 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
378 if (c->cpu_core_id == o->cpu_core_id)
379 return topology_sane(c, o, "smt");
381 if ((c->cu_id != 0xff) &&
382 (o->cu_id != 0xff) &&
383 (c->cu_id == o->cu_id))
384 return topology_sane(c, o, "smt");
387 } else if (c->phys_proc_id == o->phys_proc_id &&
388 c->cpu_core_id == o->cpu_core_id) {
389 return topology_sane(c, o, "smt");
396 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
398 * These are Intel CPUs that enumerate an LLC that is shared by
399 * multiple NUMA nodes. The LLC on these systems is shared for
400 * off-package data access but private to the NUMA node (half
401 * of the package) for on-package access.
403 * CPUID (the source of the information about the LLC) can only
404 * enumerate the cache as being shared *or* unshared, but not
405 * this particular configuration. The CPU in this case enumerates
406 * the cache to be shared across the entire package (spanning both
410 static const struct x86_cpu_id snc_cpu[] = {
411 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
415 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
417 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
419 /* Do not match if we do not have a valid APICID for cpu: */
420 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
423 /* Do not match if LLC id does not match: */
424 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
428 * Allow the SNC topology without warning. Return of false
429 * means 'c' does not share the LLC of 'o'. This will be
430 * reflected to userspace.
432 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
435 return topology_sane(c, o, "llc");
439 * Unlike the other levels, we do not enforce keeping a
440 * multicore group inside a NUMA node. If this happens, we will
441 * discard the MC level of the topology later.
443 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
445 if (c->phys_proc_id == o->phys_proc_id)
450 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
451 static inline int x86_sched_itmt_flags(void)
453 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
456 #ifdef CONFIG_SCHED_MC
457 static int x86_core_flags(void)
459 return cpu_core_flags() | x86_sched_itmt_flags();
462 #ifdef CONFIG_SCHED_SMT
463 static int x86_smt_flags(void)
465 return cpu_smt_flags() | x86_sched_itmt_flags();
470 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
471 #ifdef CONFIG_SCHED_SMT
472 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
474 #ifdef CONFIG_SCHED_MC
475 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
480 static struct sched_domain_topology_level x86_topology[] = {
481 #ifdef CONFIG_SCHED_SMT
482 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
484 #ifdef CONFIG_SCHED_MC
485 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
487 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
492 * Set if a package/die has multiple NUMA nodes inside.
493 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
494 * Sub-NUMA Clustering have this.
496 static bool x86_has_numa_in_package;
498 void set_cpu_sibling_map(int cpu)
500 bool has_smt = smp_num_siblings > 1;
501 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
502 struct cpuinfo_x86 *c = &cpu_data(cpu);
503 struct cpuinfo_x86 *o;
506 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
509 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
510 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
511 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
516 for_each_cpu(i, cpu_sibling_setup_mask) {
519 if ((i == cpu) || (has_smt && match_smt(c, o)))
520 link_mask(topology_sibling_cpumask, cpu, i);
522 if ((i == cpu) || (has_mp && match_llc(c, o)))
523 link_mask(cpu_llc_shared_mask, cpu, i);
528 * This needs a separate iteration over the cpus because we rely on all
529 * topology_sibling_cpumask links to be set-up.
531 for_each_cpu(i, cpu_sibling_setup_mask) {
534 if ((i == cpu) || (has_mp && match_die(c, o))) {
535 link_mask(topology_core_cpumask, cpu, i);
538 * Does this new cpu bringup a new core?
541 topology_sibling_cpumask(cpu)) == 1) {
543 * for each core in package, increment
544 * the booted_cores for this new cpu
547 topology_sibling_cpumask(i)) == i)
550 * increment the core count for all
551 * the other cpus in this package
554 cpu_data(i).booted_cores++;
555 } else if (i != cpu && !c->booted_cores)
556 c->booted_cores = cpu_data(i).booted_cores;
558 if (match_die(c, o) && !topology_same_node(c, o))
559 x86_has_numa_in_package = true;
562 threads = cpumask_weight(topology_sibling_cpumask(cpu));
563 if (threads > __max_smt_threads)
564 __max_smt_threads = threads;
567 /* maps the cpu to the sched domain representing multi-core */
568 const struct cpumask *cpu_coregroup_mask(int cpu)
570 return cpu_llc_shared_mask(cpu);
573 static void impress_friends(void)
576 unsigned long bogosum = 0;
578 * Allow the user to impress friends.
580 pr_debug("Before bogomips\n");
581 for_each_possible_cpu(cpu)
582 if (cpumask_test_cpu(cpu, cpu_callout_mask))
583 bogosum += cpu_data(cpu).loops_per_jiffy;
584 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
587 (bogosum/(5000/HZ))%100);
589 pr_debug("Before bogocount - setting activated=1\n");
592 void __inquire_remote_apic(int apicid)
594 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
595 const char * const names[] = { "ID", "VERSION", "SPIV" };
599 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
601 for (i = 0; i < ARRAY_SIZE(regs); i++) {
602 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
607 status = safe_apic_wait_icr_idle();
609 pr_cont("a previous APIC delivery may have failed\n");
611 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
616 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
617 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
620 case APIC_ICR_RR_VALID:
621 status = apic_read(APIC_RRR);
622 pr_cont("%08x\n", status);
631 * The Multiprocessor Specification 1.4 (1997) example code suggests
632 * that there should be a 10ms delay between the BSP asserting INIT
633 * and de-asserting INIT, when starting a remote processor.
634 * But that slows boot and resume on modern processors, which include
635 * many cores and don't require that delay.
637 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
638 * Modern processor families are quirked to remove the delay entirely.
640 #define UDELAY_10MS_DEFAULT 10000
642 static unsigned int init_udelay = UINT_MAX;
644 static int __init cpu_init_udelay(char *str)
646 get_option(&str, &init_udelay);
650 early_param("cpu_init_udelay", cpu_init_udelay);
652 static void __init smp_quirk_init_udelay(void)
654 /* if cmdline changed it from default, leave it alone */
655 if (init_udelay != UINT_MAX)
658 /* if modern processor, use no delay */
659 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
660 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
664 /* else, use legacy delay */
665 init_udelay = UDELAY_10MS_DEFAULT;
669 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
670 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
671 * won't ... remember to clear down the APIC, etc later.
674 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
676 unsigned long send_status, accept_status = 0;
680 /* Boot on the stack */
681 /* Kick the second */
682 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
684 pr_debug("Waiting for send to finish...\n");
685 send_status = safe_apic_wait_icr_idle();
688 * Give the other CPU some time to accept the IPI.
691 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
692 maxlvt = lapic_get_maxlvt();
693 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
694 apic_write(APIC_ESR, 0);
695 accept_status = (apic_read(APIC_ESR) & 0xEF);
697 pr_debug("NMI sent\n");
700 pr_err("APIC never delivered???\n");
702 pr_err("APIC delivery error (%lx)\n", accept_status);
704 return (send_status | accept_status);
708 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
710 unsigned long send_status = 0, accept_status = 0;
711 int maxlvt, num_starts, j;
713 maxlvt = lapic_get_maxlvt();
716 * Be paranoid about clearing APIC errors.
718 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
719 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
720 apic_write(APIC_ESR, 0);
724 pr_debug("Asserting INIT\n");
727 * Turn INIT on target chip
732 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
735 pr_debug("Waiting for send to finish...\n");
736 send_status = safe_apic_wait_icr_idle();
740 pr_debug("Deasserting INIT\n");
744 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
746 pr_debug("Waiting for send to finish...\n");
747 send_status = safe_apic_wait_icr_idle();
752 * Should we send STARTUP IPIs ?
754 * Determine this based on the APIC version.
755 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
757 if (APIC_INTEGRATED(boot_cpu_apic_version))
763 * Run STARTUP IPI loop.
765 pr_debug("#startup loops: %d\n", num_starts);
767 for (j = 1; j <= num_starts; j++) {
768 pr_debug("Sending STARTUP #%d\n", j);
769 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
770 apic_write(APIC_ESR, 0);
772 pr_debug("After apic_write\n");
779 /* Boot on the stack */
780 /* Kick the second */
781 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
785 * Give the other CPU some time to accept the IPI.
787 if (init_udelay == 0)
792 pr_debug("Startup point 1\n");
794 pr_debug("Waiting for send to finish...\n");
795 send_status = safe_apic_wait_icr_idle();
798 * Give the other CPU some time to accept the IPI.
800 if (init_udelay == 0)
805 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
806 apic_write(APIC_ESR, 0);
807 accept_status = (apic_read(APIC_ESR) & 0xEF);
808 if (send_status || accept_status)
811 pr_debug("After Startup\n");
814 pr_err("APIC never delivered???\n");
816 pr_err("APIC delivery error (%lx)\n", accept_status);
818 return (send_status | accept_status);
821 /* reduce the number of lines printed when booting a large cpu count system */
822 static void announce_cpu(int cpu, int apicid)
824 static int current_node = -1;
825 int node = early_cpu_to_node(cpu);
826 static int width, node_width;
829 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
832 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
835 printk(KERN_INFO "x86: Booting SMP configuration:\n");
837 if (system_state < SYSTEM_RUNNING) {
838 if (node != current_node) {
839 if (current_node > (-1))
843 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
844 node_width - num_digits(node), " ", node);
847 /* Add padding for the BSP */
849 pr_cont("%*s", width + 1, " ");
851 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
854 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
858 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
862 cpu = smp_processor_id();
863 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
870 * Wake up AP by INIT, INIT, STARTUP sequence.
872 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
873 * boot-strap code which is not a desired behavior for waking up BSP. To
874 * void the boot-strap code, wake up CPU0 by NMI instead.
876 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
877 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
878 * We'll change this code in the future to wake up hard offlined CPU0 if
879 * real platform and request are available.
882 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
883 int *cpu0_nmi_registered)
891 * Wake up AP by INIT, INIT, STARTUP sequence.
894 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
899 * Wake up BSP by nmi.
901 * Register a NMI handler to help wake up CPU0.
903 boot_error = register_nmi_handler(NMI_LOCAL,
904 wakeup_cpu0_nmi, 0, "wake_cpu0");
907 enable_start_cpu0 = 1;
908 *cpu0_nmi_registered = 1;
909 if (apic->dest_logical == APIC_DEST_LOGICAL)
910 id = cpu0_logical_apicid;
913 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
922 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
924 /* Just in case we booted with a single CPU. */
925 alternatives_enable_smp();
927 per_cpu(current_task, cpu) = idle;
930 /* Stack for startup_32 can be just as for start_secondary onwards */
932 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
934 initial_gs = per_cpu_offset(cpu);
939 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
940 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
941 * Returns zero if CPU booted OK, else error code from
942 * ->wakeup_secondary_cpu.
944 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
945 int *cpu0_nmi_registered)
947 volatile u32 *trampoline_status =
948 (volatile u32 *) __va(real_mode_header->trampoline_status);
949 /* start_ip had better be page-aligned! */
950 unsigned long start_ip = real_mode_header->trampoline_start;
952 unsigned long boot_error = 0;
953 unsigned long timeout;
955 idle->thread.sp = (unsigned long)task_pt_regs(idle);
956 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
957 initial_code = (unsigned long)start_secondary;
958 initial_stack = idle->thread.sp;
960 /* Enable the espfix hack for this CPU */
963 /* So we see what's up */
964 announce_cpu(cpu, apicid);
967 * This grunge runs the startup process for
968 * the targeted processor.
971 if (x86_platform.legacy.warm_reset) {
973 pr_debug("Setting warm reset code and vector.\n");
975 smpboot_setup_warm_reset_vector(start_ip);
977 * Be paranoid about clearing APIC errors.
979 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
980 apic_write(APIC_ESR, 0);
986 * AP might wait on cpu_callout_mask in cpu_init() with
987 * cpu_initialized_mask set if previous attempt to online
988 * it timed-out. Clear cpu_initialized_mask so that after
989 * INIT/SIPI it could start with a clean state.
991 cpumask_clear_cpu(cpu, cpu_initialized_mask);
995 * Wake up a CPU in difference cases:
996 * - Use the method in the APIC driver if it's defined
998 * - Use an INIT boot APIC message for APs or NMI for BSP.
1000 if (apic->wakeup_secondary_cpu)
1001 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1003 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1004 cpu0_nmi_registered);
1008 * Wait 10s total for first sign of life from AP
1011 timeout = jiffies + 10*HZ;
1012 while (time_before(jiffies, timeout)) {
1013 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1015 * Tell AP to proceed with initialization
1017 cpumask_set_cpu(cpu, cpu_callout_mask);
1027 * Wait till AP completes initial initialization
1029 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1031 * Allow other tasks to run while we wait for the
1032 * AP to come online. This also gives a chance
1033 * for the MTRR work(triggered by the AP coming online)
1034 * to be completed in the stop machine context.
1040 /* mark "stuck" area as not stuck */
1041 *trampoline_status = 0;
1043 if (x86_platform.legacy.warm_reset) {
1045 * Cleanup possible dangling ends...
1047 smpboot_restore_warm_reset_vector();
1053 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1055 int apicid = apic->cpu_present_to_apicid(cpu);
1056 int cpu0_nmi_registered = 0;
1057 unsigned long flags;
1060 lockdep_assert_irqs_enabled();
1062 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1064 if (apicid == BAD_APICID ||
1065 !physid_isset(apicid, phys_cpu_present_map) ||
1066 !apic->apic_id_valid(apicid)) {
1067 pr_err("%s: bad cpu %d\n", __func__, cpu);
1072 * Already booted CPU?
1074 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1075 pr_debug("do_boot_cpu %d Already started\n", cpu);
1080 * Save current MTRR state in case it was changed since early boot
1081 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1085 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1086 err = cpu_check_up_prepare(cpu);
1087 if (err && err != -EBUSY)
1090 /* the FPU context is blank, nobody can own it */
1091 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1093 common_cpu_up(cpu, tidle);
1095 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1097 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1103 * Check TSC synchronization with the AP (keep irqs disabled
1106 local_irq_save(flags);
1107 check_tsc_sync_source(cpu);
1108 local_irq_restore(flags);
1110 while (!cpu_online(cpu)) {
1112 touch_nmi_watchdog();
1117 * Clean up the nmi handler. Do this after the callin and callout sync
1118 * to avoid impact of possible long unregister time.
1120 if (cpu0_nmi_registered)
1121 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1127 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1129 void arch_disable_smp_support(void)
1131 disable_ioapic_support();
1135 * Fall back to non SMP mode after errors.
1137 * RED-PEN audit/test this more. I bet there is more state messed up here.
1139 static __init void disable_smp(void)
1141 pr_info("SMP disabled\n");
1143 disable_ioapic_support();
1145 init_cpu_present(cpumask_of(0));
1146 init_cpu_possible(cpumask_of(0));
1148 if (smp_found_config)
1149 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1151 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1152 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1153 cpumask_set_cpu(0, topology_core_cpumask(0));
1157 * Various sanity checks.
1159 static void __init smp_sanity_check(void)
1163 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1164 if (def_to_bigsmp && nr_cpu_ids > 8) {
1168 pr_warn("More than 8 CPUs detected - skipping them\n"
1169 "Use CONFIG_X86_BIGSMP\n");
1172 for_each_present_cpu(cpu) {
1174 set_cpu_present(cpu, false);
1179 for_each_possible_cpu(cpu) {
1181 set_cpu_possible(cpu, false);
1189 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1190 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1191 hard_smp_processor_id());
1193 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1197 * Should not be necessary because the MP table should list the boot
1198 * CPU too, but we do it for the sake of robustness anyway.
1200 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1201 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1202 boot_cpu_physical_apicid);
1203 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1208 static void __init smp_cpu_index_default(void)
1211 struct cpuinfo_x86 *c;
1213 for_each_possible_cpu(i) {
1215 /* mark all to hotplug */
1216 c->cpu_index = nr_cpu_ids;
1220 static void __init smp_get_logical_apicid(void)
1223 cpu0_logical_apicid = apic_read(APIC_LDR);
1225 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1229 * Prepare for SMP bootup.
1230 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1231 * for common interface support.
1233 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1237 smp_cpu_index_default();
1240 * Setup boot CPU information
1242 smp_store_boot_cpu_info(); /* Final full version of the data */
1243 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1246 for_each_possible_cpu(i) {
1247 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1248 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1249 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1253 * Set 'default' x86 topology, this matches default_topology() in that
1254 * it has NUMA nodes as a topology level. See also
1255 * native_smp_cpus_done().
1257 * Must be done before set_cpus_sibling_map() is ran.
1259 set_sched_topology(x86_topology);
1261 set_cpu_sibling_map(0);
1265 switch (apic_intr_mode) {
1267 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1270 case APIC_SYMMETRIC_IO_NO_ROUTING:
1272 /* Setup local timer */
1273 x86_init.timers.setup_percpu_clockev();
1275 case APIC_VIRTUAL_WIRE:
1276 case APIC_SYMMETRIC_IO:
1280 /* Setup local timer */
1281 x86_init.timers.setup_percpu_clockev();
1283 smp_get_logical_apicid();
1286 print_cpu_info(&cpu_data(0));
1288 native_pv_lock_init();
1292 set_mtrr_aps_delayed_init();
1294 smp_quirk_init_udelay();
1297 void arch_enable_nonboot_cpus_begin(void)
1299 set_mtrr_aps_delayed_init();
1302 void arch_enable_nonboot_cpus_end(void)
1308 * Early setup to make printk work.
1310 void __init native_smp_prepare_boot_cpu(void)
1312 int me = smp_processor_id();
1313 switch_to_new_gdt(me);
1314 /* already set me in cpu_online_mask in boot_cpu_init() */
1315 cpumask_set_cpu(me, cpu_callout_mask);
1316 cpu_set_state_online(me);
1319 void __init calculate_max_logical_packages(void)
1324 * Today neither Intel nor AMD support heterogenous systems so
1325 * extrapolate the boot cpu's data to all packages.
1327 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1328 __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus);
1329 pr_info("Max logical packages: %u\n", __max_logical_packages);
1332 void __init native_smp_cpus_done(unsigned int max_cpus)
1334 pr_debug("Boot done\n");
1336 calculate_max_logical_packages();
1338 if (x86_has_numa_in_package)
1339 set_sched_topology(x86_numa_in_package_topology);
1346 static int __initdata setup_possible_cpus = -1;
1347 static int __init _setup_possible_cpus(char *str)
1349 get_option(&str, &setup_possible_cpus);
1352 early_param("possible_cpus", _setup_possible_cpus);
1356 * cpu_possible_mask should be static, it cannot change as cpu's
1357 * are onlined, or offlined. The reason is per-cpu data-structures
1358 * are allocated by some modules at init time, and dont expect to
1359 * do this dynamically on cpu arrival/departure.
1360 * cpu_present_mask on the other hand can change dynamically.
1361 * In case when cpu_hotplug is not compiled, then we resort to current
1362 * behaviour, which is cpu_possible == cpu_present.
1365 * Three ways to find out the number of additional hotplug CPUs:
1366 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1367 * - The user can overwrite it with possible_cpus=NUM
1368 * - Otherwise don't reserve additional CPUs.
1369 * We do this because additional CPUs waste a lot of memory.
1372 __init void prefill_possible_map(void)
1376 /* No boot processor was found in mptable or ACPI MADT */
1377 if (!num_processors) {
1378 if (boot_cpu_has(X86_FEATURE_APIC)) {
1379 int apicid = boot_cpu_physical_apicid;
1380 int cpu = hard_smp_processor_id();
1382 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1384 /* Make sure boot cpu is enumerated */
1385 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1386 apic->apic_id_valid(apicid))
1387 generic_processor_info(apicid, boot_cpu_apic_version);
1390 if (!num_processors)
1394 i = setup_max_cpus ?: 1;
1395 if (setup_possible_cpus == -1) {
1396 possible = num_processors;
1397 #ifdef CONFIG_HOTPLUG_CPU
1399 possible += disabled_cpus;
1405 possible = setup_possible_cpus;
1407 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1409 /* nr_cpu_ids could be reduced via nr_cpus= */
1410 if (possible > nr_cpu_ids) {
1411 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1412 possible, nr_cpu_ids);
1413 possible = nr_cpu_ids;
1416 #ifdef CONFIG_HOTPLUG_CPU
1417 if (!setup_max_cpus)
1420 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1421 possible, setup_max_cpus);
1425 nr_cpu_ids = possible;
1427 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1428 possible, max_t(int, possible - num_processors, 0));
1430 reset_cpu_possible_mask();
1432 for (i = 0; i < possible; i++)
1433 set_cpu_possible(i, true);
1436 #ifdef CONFIG_HOTPLUG_CPU
1438 /* Recompute SMT state for all CPUs on offline */
1439 static void recompute_smt_state(void)
1441 int max_threads, cpu;
1444 for_each_online_cpu (cpu) {
1445 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1447 if (threads > max_threads)
1448 max_threads = threads;
1450 __max_smt_threads = max_threads;
1453 static void remove_siblinginfo(int cpu)
1456 struct cpuinfo_x86 *c = &cpu_data(cpu);
1458 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1459 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1461 * last thread sibling in this cpu core going down
1463 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1464 cpu_data(sibling).booted_cores--;
1467 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1468 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1469 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1470 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1471 cpumask_clear(cpu_llc_shared_mask(cpu));
1472 cpumask_clear(topology_sibling_cpumask(cpu));
1473 cpumask_clear(topology_core_cpumask(cpu));
1475 c->booted_cores = 0;
1476 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1477 recompute_smt_state();
1480 static void remove_cpu_from_maps(int cpu)
1482 set_cpu_online(cpu, false);
1483 cpumask_clear_cpu(cpu, cpu_callout_mask);
1484 cpumask_clear_cpu(cpu, cpu_callin_mask);
1485 /* was set by cpu_init() */
1486 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1487 numa_remove_cpu(cpu);
1490 void cpu_disable_common(void)
1492 int cpu = smp_processor_id();
1494 remove_siblinginfo(cpu);
1496 /* It's now safe to remove this processor from the online map */
1498 remove_cpu_from_maps(cpu);
1499 unlock_vector_lock();
1504 int native_cpu_disable(void)
1508 ret = lapic_can_unplug_cpu();
1513 cpu_disable_common();
1518 int common_cpu_die(unsigned int cpu)
1522 /* We don't do anything here: idle task is faking death itself. */
1524 /* They ack this in play_dead() by setting CPU_DEAD */
1525 if (cpu_wait_death(cpu, 5)) {
1526 if (system_state == SYSTEM_RUNNING)
1527 pr_info("CPU %u is now offline\n", cpu);
1529 pr_err("CPU %u didn't die...\n", cpu);
1536 void native_cpu_die(unsigned int cpu)
1538 common_cpu_die(cpu);
1541 void play_dead_common(void)
1546 (void)cpu_report_death();
1549 * With physical CPU hotplug, we should halt the cpu
1551 local_irq_disable();
1554 static bool wakeup_cpu0(void)
1556 if (smp_processor_id() == 0 && enable_start_cpu0)
1563 * We need to flush the caches before going to sleep, lest we have
1564 * dirty data in our caches when we come back up.
1566 static inline void mwait_play_dead(void)
1568 unsigned int eax, ebx, ecx, edx;
1569 unsigned int highest_cstate = 0;
1570 unsigned int highest_subcstate = 0;
1574 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1576 if (!this_cpu_has(X86_FEATURE_MWAIT))
1578 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1580 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1583 eax = CPUID_MWAIT_LEAF;
1585 native_cpuid(&eax, &ebx, &ecx, &edx);
1588 * eax will be 0 if EDX enumeration is not valid.
1589 * Initialized below to cstate, sub_cstate value when EDX is valid.
1591 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1594 edx >>= MWAIT_SUBSTATE_SIZE;
1595 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1596 if (edx & MWAIT_SUBSTATE_MASK) {
1598 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1601 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1602 (highest_subcstate - 1);
1606 * This should be a memory location in a cache line which is
1607 * unlikely to be touched by other processors. The actual
1608 * content is immaterial as it is not actually modified in any way.
1610 mwait_ptr = ¤t_thread_info()->flags;
1616 * The CLFLUSH is a workaround for erratum AAI65 for
1617 * the Xeon 7400 series. It's not clear it is actually
1618 * needed, but it should be harmless in either case.
1619 * The WBINVD is insufficient due to the spurious-wakeup
1620 * case where we return around the loop.
1625 __monitor(mwait_ptr, 0, 0);
1629 * If NMI wants to wake up CPU0, start CPU0.
1636 void hlt_play_dead(void)
1638 if (__this_cpu_read(cpu_info.x86) >= 4)
1644 * If NMI wants to wake up CPU0, start CPU0.
1651 void native_play_dead(void)
1654 tboot_shutdown(TB_SHUTDOWN_WFS);
1656 mwait_play_dead(); /* Only returns on failure */
1657 if (cpuidle_play_dead())
1661 #else /* ... !CONFIG_HOTPLUG_CPU */
1662 int native_cpu_disable(void)
1667 void native_cpu_die(unsigned int cpu)
1669 /* We said "no" in __cpu_disable */
1673 void native_play_dead(void)