1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 SMP booting functions
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
56 #include <linux/numa.h>
57 #include <linux/pgtable.h>
58 #include <linux/overflow.h>
59 #include <linux/syscore_ops.h>
65 #include <asm/realmode.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
79 #include <asm/qspinlock.h>
80 #include <asm/intel-family.h>
81 #include <asm/cpu_device_id.h>
82 #include <asm/spec-ctrl.h>
83 #include <asm/hw_irq.h>
84 #include <asm/stackprotector.h>
86 #ifdef CONFIG_ACPI_CPPC_LIB
87 #include <acpi/cppc_acpi.h>
90 /* representing HT siblings of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
92 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
94 /* representing HT and core siblings of each logical CPU */
95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
96 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
98 /* representing HT, core, and die siblings of each logical CPU */
99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
100 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
102 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
104 /* Per CPU bogomips and other parameters */
105 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
106 EXPORT_PER_CPU_SYMBOL(cpu_info);
108 /* Logical package management. We might want to allocate that dynamically */
109 unsigned int __max_logical_packages __read_mostly;
110 EXPORT_SYMBOL(__max_logical_packages);
111 static unsigned int logical_packages __read_mostly;
112 static unsigned int logical_die __read_mostly;
114 /* Maximum number of SMT threads on any online core */
115 int __read_mostly __max_smt_threads = 1;
117 /* Flag to indicate if a complete sched domain rebuild is required */
118 bool x86_topology_update;
120 int arch_update_cpu_topology(void)
122 int retval = x86_topology_update;
124 x86_topology_update = false;
128 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
132 spin_lock_irqsave(&rtc_lock, flags);
133 CMOS_WRITE(0xa, 0xf);
134 spin_unlock_irqrestore(&rtc_lock, flags);
135 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
137 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
141 static inline void smpboot_restore_warm_reset_vector(void)
146 * Paranoid: Set warm reset code and vector here back
149 spin_lock_irqsave(&rtc_lock, flags);
151 spin_unlock_irqrestore(&rtc_lock, flags);
153 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
156 static void init_freq_invariance(bool secondary, bool cppc_ready);
159 * Report back to the Boot Processor during boot time or to the caller processor
162 static void smp_callin(void)
167 * If waken up by an INIT in an 82489DX configuration
168 * cpu_callout_mask guarantees we don't get here before
169 * an INIT_deassert IPI reaches our local APIC, so it is
170 * now safe to touch our local APIC.
172 cpuid = smp_processor_id();
175 * the boot CPU has finished the init stage and is spinning
176 * on callin_map until we finish. We are free to set up this
177 * CPU, first the APIC. (this is probably redundant on most
183 * Save our processor parameters. Note: this information
184 * is needed for clock calibration.
186 smp_store_cpu_info(cpuid);
189 * The topology information must be up to date before
190 * calibrate_delay() and notify_cpu_starting().
192 set_cpu_sibling_map(raw_smp_processor_id());
194 init_freq_invariance(true, false);
198 * Update loops_per_jiffy in cpu_data. Previous call to
199 * smp_store_cpu_info() stored a value that is close but not as
200 * accurate as the value just calculated.
203 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
204 pr_debug("Stack at about %p\n", &cpuid);
208 notify_cpu_starting(cpuid);
211 * Allow the master to continue.
213 cpumask_set_cpu(cpuid, cpu_callin_mask);
216 static int cpu0_logical_apicid;
217 static int enable_start_cpu0;
219 * Activate a secondary processor.
221 static void notrace start_secondary(void *unused)
224 * Don't put *anything* except direct CPU state initialization
225 * before cpu_init(), SMP booting is too fragile that we want to
226 * limit the things done here to the most necessary things.
231 /* switch away from the initial page table */
232 load_cr3(swapper_pg_dir);
235 cpu_init_exception_handling();
237 rcu_cpu_starting(raw_smp_processor_id());
238 x86_cpuinit.early_percpu_clock_init();
242 enable_start_cpu0 = 0;
244 /* otherwise gcc will move up smp_processor_id before the cpu_init */
247 * Check TSC synchronization with the boot CPU:
249 check_tsc_sync_target();
251 speculative_store_bypass_ht_init();
254 * Lock vector_lock, set CPU online and bring the vector
255 * allocator online. Online must be set with vector_lock held
256 * to prevent a concurrent irq setup/teardown from seeing a
257 * half valid vector space.
260 set_cpu_online(smp_processor_id(), true);
262 unlock_vector_lock();
263 cpu_set_state_online(smp_processor_id());
264 x86_platform.nmi_init();
266 /* enable local interrupts */
269 x86_cpuinit.setup_percpu_clockev();
272 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
276 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
279 bool topology_is_primary_thread(unsigned int cpu)
281 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
285 * topology_smt_supported - Check whether SMT is supported by the CPUs
287 bool topology_smt_supported(void)
289 return smp_num_siblings > 1;
293 * topology_phys_to_logical_pkg - Map a physical package id to a logical
295 * Returns logical package id or -1 if not found
297 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
301 for_each_possible_cpu(cpu) {
302 struct cpuinfo_x86 *c = &cpu_data(cpu);
304 if (c->initialized && c->phys_proc_id == phys_pkg)
305 return c->logical_proc_id;
309 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
311 * topology_phys_to_logical_die - Map a physical die id to logical
313 * Returns logical die id or -1 if not found
315 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
318 int proc_id = cpu_data(cur_cpu).phys_proc_id;
320 for_each_possible_cpu(cpu) {
321 struct cpuinfo_x86 *c = &cpu_data(cpu);
323 if (c->initialized && c->cpu_die_id == die_id &&
324 c->phys_proc_id == proc_id)
325 return c->logical_die_id;
329 EXPORT_SYMBOL(topology_phys_to_logical_die);
332 * topology_update_package_map - Update the physical to logical package map
333 * @pkg: The physical package id as retrieved via CPUID
334 * @cpu: The cpu for which this is updated
336 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
340 /* Already available somewhere? */
341 new = topology_phys_to_logical_pkg(pkg);
345 new = logical_packages++;
347 pr_info("CPU %u Converting physical %u to logical package %u\n",
351 cpu_data(cpu).logical_proc_id = new;
355 * topology_update_die_map - Update the physical to logical die map
356 * @die: The die id as retrieved via CPUID
357 * @cpu: The cpu for which this is updated
359 int topology_update_die_map(unsigned int die, unsigned int cpu)
363 /* Already available somewhere? */
364 new = topology_phys_to_logical_die(die, cpu);
370 pr_info("CPU %u Converting physical %u to logical die %u\n",
374 cpu_data(cpu).logical_die_id = new;
378 void __init smp_store_boot_cpu_info(void)
380 int id = 0; /* CPU 0 */
381 struct cpuinfo_x86 *c = &cpu_data(id);
385 topology_update_package_map(c->phys_proc_id, id);
386 topology_update_die_map(c->cpu_die_id, id);
387 c->initialized = true;
391 * The bootstrap kernel entry code has set these up. Save them for
394 void smp_store_cpu_info(int id)
396 struct cpuinfo_x86 *c = &cpu_data(id);
398 /* Copy boot_cpu_data only on the first bringup */
403 * During boot time, CPU0 has this setup already. Save the info when
404 * bringing up AP or offlined CPU0.
406 identify_secondary_cpu(c);
407 c->initialized = true;
411 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
413 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
415 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
419 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
421 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
423 return !WARN_ONCE(!topology_same_node(c, o),
424 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
425 "[node: %d != %d]. Ignoring dependency.\n",
426 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
429 #define link_mask(mfunc, c1, c2) \
431 cpumask_set_cpu((c1), mfunc(c2)); \
432 cpumask_set_cpu((c2), mfunc(c1)); \
435 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
437 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
438 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
440 if (c->phys_proc_id == o->phys_proc_id &&
441 c->cpu_die_id == o->cpu_die_id &&
442 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
443 if (c->cpu_core_id == o->cpu_core_id)
444 return topology_sane(c, o, "smt");
446 if ((c->cu_id != 0xff) &&
447 (o->cu_id != 0xff) &&
448 (c->cu_id == o->cu_id))
449 return topology_sane(c, o, "smt");
452 } else if (c->phys_proc_id == o->phys_proc_id &&
453 c->cpu_die_id == o->cpu_die_id &&
454 c->cpu_core_id == o->cpu_core_id) {
455 return topology_sane(c, o, "smt");
462 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
464 * These are Intel CPUs that enumerate an LLC that is shared by
465 * multiple NUMA nodes. The LLC on these systems is shared for
466 * off-package data access but private to the NUMA node (half
467 * of the package) for on-package access.
469 * CPUID (the source of the information about the LLC) can only
470 * enumerate the cache as being shared *or* unshared, but not
471 * this particular configuration. The CPU in this case enumerates
472 * the cache to be shared across the entire package (spanning both
476 static const struct x86_cpu_id snc_cpu[] = {
477 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL),
481 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
483 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
485 /* Do not match if we do not have a valid APICID for cpu: */
486 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
489 /* Do not match if LLC id does not match: */
490 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
494 * Allow the SNC topology without warning. Return of false
495 * means 'c' does not share the LLC of 'o'. This will be
496 * reflected to userspace.
498 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
501 return topology_sane(c, o, "llc");
505 * Unlike the other levels, we do not enforce keeping a
506 * multicore group inside a NUMA node. If this happens, we will
507 * discard the MC level of the topology later.
509 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
511 if (c->phys_proc_id == o->phys_proc_id)
516 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
518 if ((c->phys_proc_id == o->phys_proc_id) &&
519 (c->cpu_die_id == o->cpu_die_id))
525 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
526 static inline int x86_sched_itmt_flags(void)
528 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
531 #ifdef CONFIG_SCHED_MC
532 static int x86_core_flags(void)
534 return cpu_core_flags() | x86_sched_itmt_flags();
537 #ifdef CONFIG_SCHED_SMT
538 static int x86_smt_flags(void)
540 return cpu_smt_flags() | x86_sched_itmt_flags();
545 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
546 #ifdef CONFIG_SCHED_SMT
547 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
549 #ifdef CONFIG_SCHED_MC
550 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
555 static struct sched_domain_topology_level x86_topology[] = {
556 #ifdef CONFIG_SCHED_SMT
557 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
559 #ifdef CONFIG_SCHED_MC
560 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
562 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
567 * Set if a package/die has multiple NUMA nodes inside.
568 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
569 * Sub-NUMA Clustering have this.
571 static bool x86_has_numa_in_package;
573 void set_cpu_sibling_map(int cpu)
575 bool has_smt = smp_num_siblings > 1;
576 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
577 struct cpuinfo_x86 *c = &cpu_data(cpu);
578 struct cpuinfo_x86 *o;
581 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
584 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
585 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
586 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
587 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
592 for_each_cpu(i, cpu_sibling_setup_mask) {
595 if ((i == cpu) || (has_smt && match_smt(c, o)))
596 link_mask(topology_sibling_cpumask, cpu, i);
598 if ((i == cpu) || (has_mp && match_llc(c, o)))
599 link_mask(cpu_llc_shared_mask, cpu, i);
604 * This needs a separate iteration over the cpus because we rely on all
605 * topology_sibling_cpumask links to be set-up.
607 for_each_cpu(i, cpu_sibling_setup_mask) {
610 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
611 link_mask(topology_core_cpumask, cpu, i);
614 * Does this new cpu bringup a new core?
617 topology_sibling_cpumask(cpu)) == 1) {
619 * for each core in package, increment
620 * the booted_cores for this new cpu
623 topology_sibling_cpumask(i)) == i)
626 * increment the core count for all
627 * the other cpus in this package
630 cpu_data(i).booted_cores++;
631 } else if (i != cpu && !c->booted_cores)
632 c->booted_cores = cpu_data(i).booted_cores;
634 if (match_pkg(c, o) && !topology_same_node(c, o))
635 x86_has_numa_in_package = true;
637 if ((i == cpu) || (has_mp && match_die(c, o)))
638 link_mask(topology_die_cpumask, cpu, i);
641 threads = cpumask_weight(topology_sibling_cpumask(cpu));
642 if (threads > __max_smt_threads)
643 __max_smt_threads = threads;
646 /* maps the cpu to the sched domain representing multi-core */
647 const struct cpumask *cpu_coregroup_mask(int cpu)
649 return cpu_llc_shared_mask(cpu);
652 static void impress_friends(void)
655 unsigned long bogosum = 0;
657 * Allow the user to impress friends.
659 pr_debug("Before bogomips\n");
660 for_each_possible_cpu(cpu)
661 if (cpumask_test_cpu(cpu, cpu_callout_mask))
662 bogosum += cpu_data(cpu).loops_per_jiffy;
663 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
666 (bogosum/(5000/HZ))%100);
668 pr_debug("Before bogocount - setting activated=1\n");
671 void __inquire_remote_apic(int apicid)
673 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
674 const char * const names[] = { "ID", "VERSION", "SPIV" };
678 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
680 for (i = 0; i < ARRAY_SIZE(regs); i++) {
681 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
686 status = safe_apic_wait_icr_idle();
688 pr_cont("a previous APIC delivery may have failed\n");
690 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
695 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
696 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
699 case APIC_ICR_RR_VALID:
700 status = apic_read(APIC_RRR);
701 pr_cont("%08x\n", status);
710 * The Multiprocessor Specification 1.4 (1997) example code suggests
711 * that there should be a 10ms delay between the BSP asserting INIT
712 * and de-asserting INIT, when starting a remote processor.
713 * But that slows boot and resume on modern processors, which include
714 * many cores and don't require that delay.
716 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
717 * Modern processor families are quirked to remove the delay entirely.
719 #define UDELAY_10MS_DEFAULT 10000
721 static unsigned int init_udelay = UINT_MAX;
723 static int __init cpu_init_udelay(char *str)
725 get_option(&str, &init_udelay);
729 early_param("cpu_init_udelay", cpu_init_udelay);
731 static void __init smp_quirk_init_udelay(void)
733 /* if cmdline changed it from default, leave it alone */
734 if (init_udelay != UINT_MAX)
737 /* if modern processor, use no delay */
738 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
739 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
740 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
744 /* else, use legacy delay */
745 init_udelay = UDELAY_10MS_DEFAULT;
749 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
750 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
751 * won't ... remember to clear down the APIC, etc later.
754 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
756 u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
757 unsigned long send_status, accept_status = 0;
761 /* Boot on the stack */
762 /* Kick the second */
763 apic_icr_write(APIC_DM_NMI | dm, apicid);
765 pr_debug("Waiting for send to finish...\n");
766 send_status = safe_apic_wait_icr_idle();
769 * Give the other CPU some time to accept the IPI.
772 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
773 maxlvt = lapic_get_maxlvt();
774 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
775 apic_write(APIC_ESR, 0);
776 accept_status = (apic_read(APIC_ESR) & 0xEF);
778 pr_debug("NMI sent\n");
781 pr_err("APIC never delivered???\n");
783 pr_err("APIC delivery error (%lx)\n", accept_status);
785 return (send_status | accept_status);
789 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
791 unsigned long send_status = 0, accept_status = 0;
792 int maxlvt, num_starts, j;
794 maxlvt = lapic_get_maxlvt();
797 * Be paranoid about clearing APIC errors.
799 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
800 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
801 apic_write(APIC_ESR, 0);
805 pr_debug("Asserting INIT\n");
808 * Turn INIT on target chip
813 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
816 pr_debug("Waiting for send to finish...\n");
817 send_status = safe_apic_wait_icr_idle();
821 pr_debug("Deasserting INIT\n");
825 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
827 pr_debug("Waiting for send to finish...\n");
828 send_status = safe_apic_wait_icr_idle();
833 * Should we send STARTUP IPIs ?
835 * Determine this based on the APIC version.
836 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
838 if (APIC_INTEGRATED(boot_cpu_apic_version))
844 * Run STARTUP IPI loop.
846 pr_debug("#startup loops: %d\n", num_starts);
848 for (j = 1; j <= num_starts; j++) {
849 pr_debug("Sending STARTUP #%d\n", j);
850 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
851 apic_write(APIC_ESR, 0);
853 pr_debug("After apic_write\n");
860 /* Boot on the stack */
861 /* Kick the second */
862 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
866 * Give the other CPU some time to accept the IPI.
868 if (init_udelay == 0)
873 pr_debug("Startup point 1\n");
875 pr_debug("Waiting for send to finish...\n");
876 send_status = safe_apic_wait_icr_idle();
879 * Give the other CPU some time to accept the IPI.
881 if (init_udelay == 0)
886 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
887 apic_write(APIC_ESR, 0);
888 accept_status = (apic_read(APIC_ESR) & 0xEF);
889 if (send_status || accept_status)
892 pr_debug("After Startup\n");
895 pr_err("APIC never delivered???\n");
897 pr_err("APIC delivery error (%lx)\n", accept_status);
899 return (send_status | accept_status);
902 /* reduce the number of lines printed when booting a large cpu count system */
903 static void announce_cpu(int cpu, int apicid)
905 static int current_node = NUMA_NO_NODE;
906 int node = early_cpu_to_node(cpu);
907 static int width, node_width;
910 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
913 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
916 printk(KERN_INFO "x86: Booting SMP configuration:\n");
918 if (system_state < SYSTEM_RUNNING) {
919 if (node != current_node) {
920 if (current_node > (-1))
924 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
925 node_width - num_digits(node), " ", node);
928 /* Add padding for the BSP */
930 pr_cont("%*s", width + 1, " ");
932 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
935 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
939 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
943 cpu = smp_processor_id();
944 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
951 * Wake up AP by INIT, INIT, STARTUP sequence.
953 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
954 * boot-strap code which is not a desired behavior for waking up BSP. To
955 * void the boot-strap code, wake up CPU0 by NMI instead.
957 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
958 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
959 * We'll change this code in the future to wake up hard offlined CPU0 if
960 * real platform and request are available.
963 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
964 int *cpu0_nmi_registered)
972 * Wake up AP by INIT, INIT, STARTUP sequence.
975 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
980 * Wake up BSP by nmi.
982 * Register a NMI handler to help wake up CPU0.
984 boot_error = register_nmi_handler(NMI_LOCAL,
985 wakeup_cpu0_nmi, 0, "wake_cpu0");
988 enable_start_cpu0 = 1;
989 *cpu0_nmi_registered = 1;
990 id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid;
991 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
1000 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
1004 /* Just in case we booted with a single CPU. */
1005 alternatives_enable_smp();
1007 per_cpu(current_task, cpu) = idle;
1008 cpu_init_stack_canary(cpu, idle);
1010 /* Initialize the interrupt stack(s) */
1011 ret = irq_init_percpu_irqstack(cpu);
1015 #ifdef CONFIG_X86_32
1016 /* Stack for startup_32 can be just as for start_secondary onwards */
1017 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1019 initial_gs = per_cpu_offset(cpu);
1025 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1026 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1027 * Returns zero if CPU booted OK, else error code from
1028 * ->wakeup_secondary_cpu.
1030 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1031 int *cpu0_nmi_registered)
1033 /* start_ip had better be page-aligned! */
1034 unsigned long start_ip = real_mode_header->trampoline_start;
1036 unsigned long boot_error = 0;
1037 unsigned long timeout;
1039 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1040 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1041 initial_code = (unsigned long)start_secondary;
1042 initial_stack = idle->thread.sp;
1044 /* Enable the espfix hack for this CPU */
1045 init_espfix_ap(cpu);
1047 /* So we see what's up */
1048 announce_cpu(cpu, apicid);
1051 * This grunge runs the startup process for
1052 * the targeted processor.
1055 if (x86_platform.legacy.warm_reset) {
1057 pr_debug("Setting warm reset code and vector.\n");
1059 smpboot_setup_warm_reset_vector(start_ip);
1061 * Be paranoid about clearing APIC errors.
1063 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1064 apic_write(APIC_ESR, 0);
1065 apic_read(APIC_ESR);
1070 * AP might wait on cpu_callout_mask in cpu_init() with
1071 * cpu_initialized_mask set if previous attempt to online
1072 * it timed-out. Clear cpu_initialized_mask so that after
1073 * INIT/SIPI it could start with a clean state.
1075 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1079 * Wake up a CPU in difference cases:
1080 * - Use the method in the APIC driver if it's defined
1082 * - Use an INIT boot APIC message for APs or NMI for BSP.
1084 if (apic->wakeup_secondary_cpu)
1085 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1087 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1088 cpu0_nmi_registered);
1092 * Wait 10s total for first sign of life from AP
1095 timeout = jiffies + 10*HZ;
1096 while (time_before(jiffies, timeout)) {
1097 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1099 * Tell AP to proceed with initialization
1101 cpumask_set_cpu(cpu, cpu_callout_mask);
1111 * Wait till AP completes initial initialization
1113 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1115 * Allow other tasks to run while we wait for the
1116 * AP to come online. This also gives a chance
1117 * for the MTRR work(triggered by the AP coming online)
1118 * to be completed in the stop machine context.
1124 if (x86_platform.legacy.warm_reset) {
1126 * Cleanup possible dangling ends...
1128 smpboot_restore_warm_reset_vector();
1134 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1136 int apicid = apic->cpu_present_to_apicid(cpu);
1137 int cpu0_nmi_registered = 0;
1138 unsigned long flags;
1141 lockdep_assert_irqs_enabled();
1143 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1145 if (apicid == BAD_APICID ||
1146 !physid_isset(apicid, phys_cpu_present_map) ||
1147 !apic->apic_id_valid(apicid)) {
1148 pr_err("%s: bad cpu %d\n", __func__, cpu);
1153 * Already booted CPU?
1155 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1156 pr_debug("do_boot_cpu %d Already started\n", cpu);
1161 * Save current MTRR state in case it was changed since early boot
1162 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1166 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1167 err = cpu_check_up_prepare(cpu);
1168 if (err && err != -EBUSY)
1171 /* the FPU context is blank, nobody can own it */
1172 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1174 err = common_cpu_up(cpu, tidle);
1178 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1180 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1186 * Check TSC synchronization with the AP (keep irqs disabled
1189 local_irq_save(flags);
1190 check_tsc_sync_source(cpu);
1191 local_irq_restore(flags);
1193 while (!cpu_online(cpu)) {
1195 touch_nmi_watchdog();
1200 * Clean up the nmi handler. Do this after the callin and callout sync
1201 * to avoid impact of possible long unregister time.
1203 if (cpu0_nmi_registered)
1204 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1210 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1212 void arch_disable_smp_support(void)
1214 disable_ioapic_support();
1218 * Fall back to non SMP mode after errors.
1220 * RED-PEN audit/test this more. I bet there is more state messed up here.
1222 static __init void disable_smp(void)
1224 pr_info("SMP disabled\n");
1226 disable_ioapic_support();
1228 init_cpu_present(cpumask_of(0));
1229 init_cpu_possible(cpumask_of(0));
1231 if (smp_found_config)
1232 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1234 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1235 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1236 cpumask_set_cpu(0, topology_core_cpumask(0));
1237 cpumask_set_cpu(0, topology_die_cpumask(0));
1241 * Various sanity checks.
1243 static void __init smp_sanity_check(void)
1247 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1248 if (def_to_bigsmp && nr_cpu_ids > 8) {
1252 pr_warn("More than 8 CPUs detected - skipping them\n"
1253 "Use CONFIG_X86_BIGSMP\n");
1256 for_each_present_cpu(cpu) {
1258 set_cpu_present(cpu, false);
1263 for_each_possible_cpu(cpu) {
1265 set_cpu_possible(cpu, false);
1273 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1274 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1275 hard_smp_processor_id());
1277 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1281 * Should not be necessary because the MP table should list the boot
1282 * CPU too, but we do it for the sake of robustness anyway.
1284 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1285 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1286 boot_cpu_physical_apicid);
1287 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1292 static void __init smp_cpu_index_default(void)
1295 struct cpuinfo_x86 *c;
1297 for_each_possible_cpu(i) {
1299 /* mark all to hotplug */
1300 c->cpu_index = nr_cpu_ids;
1304 static void __init smp_get_logical_apicid(void)
1307 cpu0_logical_apicid = apic_read(APIC_LDR);
1309 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1313 * Prepare for SMP bootup.
1314 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1315 * for common interface support.
1317 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1321 smp_cpu_index_default();
1324 * Setup boot CPU information
1326 smp_store_boot_cpu_info(); /* Final full version of the data */
1327 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1330 for_each_possible_cpu(i) {
1331 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1332 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1333 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1334 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1338 * Set 'default' x86 topology, this matches default_topology() in that
1339 * it has NUMA nodes as a topology level. See also
1340 * native_smp_cpus_done().
1342 * Must be done before set_cpus_sibling_map() is ran.
1344 set_sched_topology(x86_topology);
1346 set_cpu_sibling_map(0);
1347 init_freq_invariance(false, false);
1350 switch (apic_intr_mode) {
1352 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1355 case APIC_SYMMETRIC_IO_NO_ROUTING:
1357 /* Setup local timer */
1358 x86_init.timers.setup_percpu_clockev();
1360 case APIC_VIRTUAL_WIRE:
1361 case APIC_SYMMETRIC_IO:
1365 /* Setup local timer */
1366 x86_init.timers.setup_percpu_clockev();
1368 smp_get_logical_apicid();
1371 print_cpu_info(&cpu_data(0));
1375 set_mtrr_aps_delayed_init();
1377 smp_quirk_init_udelay();
1379 speculative_store_bypass_ht_init();
1382 void arch_thaw_secondary_cpus_begin(void)
1384 set_mtrr_aps_delayed_init();
1387 void arch_thaw_secondary_cpus_end(void)
1393 * Early setup to make printk work.
1395 void __init native_smp_prepare_boot_cpu(void)
1397 int me = smp_processor_id();
1398 switch_to_new_gdt(me);
1399 /* already set me in cpu_online_mask in boot_cpu_init() */
1400 cpumask_set_cpu(me, cpu_callout_mask);
1401 cpu_set_state_online(me);
1402 native_pv_lock_init();
1405 void __init calculate_max_logical_packages(void)
1410 * Today neither Intel nor AMD support heterogenous systems so
1411 * extrapolate the boot cpu's data to all packages.
1413 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1414 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1415 pr_info("Max logical packages: %u\n", __max_logical_packages);
1418 void __init native_smp_cpus_done(unsigned int max_cpus)
1420 pr_debug("Boot done\n");
1422 calculate_max_logical_packages();
1424 if (x86_has_numa_in_package)
1425 set_sched_topology(x86_numa_in_package_topology);
1432 static int __initdata setup_possible_cpus = -1;
1433 static int __init _setup_possible_cpus(char *str)
1435 get_option(&str, &setup_possible_cpus);
1438 early_param("possible_cpus", _setup_possible_cpus);
1442 * cpu_possible_mask should be static, it cannot change as cpu's
1443 * are onlined, or offlined. The reason is per-cpu data-structures
1444 * are allocated by some modules at init time, and don't expect to
1445 * do this dynamically on cpu arrival/departure.
1446 * cpu_present_mask on the other hand can change dynamically.
1447 * In case when cpu_hotplug is not compiled, then we resort to current
1448 * behaviour, which is cpu_possible == cpu_present.
1451 * Three ways to find out the number of additional hotplug CPUs:
1452 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1453 * - The user can overwrite it with possible_cpus=NUM
1454 * - Otherwise don't reserve additional CPUs.
1455 * We do this because additional CPUs waste a lot of memory.
1458 __init void prefill_possible_map(void)
1462 /* No boot processor was found in mptable or ACPI MADT */
1463 if (!num_processors) {
1464 if (boot_cpu_has(X86_FEATURE_APIC)) {
1465 int apicid = boot_cpu_physical_apicid;
1466 int cpu = hard_smp_processor_id();
1468 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1470 /* Make sure boot cpu is enumerated */
1471 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1472 apic->apic_id_valid(apicid))
1473 generic_processor_info(apicid, boot_cpu_apic_version);
1476 if (!num_processors)
1480 i = setup_max_cpus ?: 1;
1481 if (setup_possible_cpus == -1) {
1482 possible = num_processors;
1483 #ifdef CONFIG_HOTPLUG_CPU
1485 possible += disabled_cpus;
1491 possible = setup_possible_cpus;
1493 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1495 /* nr_cpu_ids could be reduced via nr_cpus= */
1496 if (possible > nr_cpu_ids) {
1497 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1498 possible, nr_cpu_ids);
1499 possible = nr_cpu_ids;
1502 #ifdef CONFIG_HOTPLUG_CPU
1503 if (!setup_max_cpus)
1506 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1507 possible, setup_max_cpus);
1511 nr_cpu_ids = possible;
1513 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1514 possible, max_t(int, possible - num_processors, 0));
1516 reset_cpu_possible_mask();
1518 for (i = 0; i < possible; i++)
1519 set_cpu_possible(i, true);
1522 #ifdef CONFIG_HOTPLUG_CPU
1524 /* Recompute SMT state for all CPUs on offline */
1525 static void recompute_smt_state(void)
1527 int max_threads, cpu;
1530 for_each_online_cpu (cpu) {
1531 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1533 if (threads > max_threads)
1534 max_threads = threads;
1536 __max_smt_threads = max_threads;
1539 static void remove_siblinginfo(int cpu)
1542 struct cpuinfo_x86 *c = &cpu_data(cpu);
1544 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1545 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1547 * last thread sibling in this cpu core going down
1549 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1550 cpu_data(sibling).booted_cores--;
1553 for_each_cpu(sibling, topology_die_cpumask(cpu))
1554 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1555 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1556 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1557 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1558 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1559 cpumask_clear(cpu_llc_shared_mask(cpu));
1560 cpumask_clear(topology_sibling_cpumask(cpu));
1561 cpumask_clear(topology_core_cpumask(cpu));
1562 cpumask_clear(topology_die_cpumask(cpu));
1564 c->booted_cores = 0;
1565 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1566 recompute_smt_state();
1569 static void remove_cpu_from_maps(int cpu)
1571 set_cpu_online(cpu, false);
1572 cpumask_clear_cpu(cpu, cpu_callout_mask);
1573 cpumask_clear_cpu(cpu, cpu_callin_mask);
1574 /* was set by cpu_init() */
1575 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1576 numa_remove_cpu(cpu);
1579 void cpu_disable_common(void)
1581 int cpu = smp_processor_id();
1583 remove_siblinginfo(cpu);
1585 /* It's now safe to remove this processor from the online map */
1587 remove_cpu_from_maps(cpu);
1588 unlock_vector_lock();
1593 int native_cpu_disable(void)
1597 ret = lapic_can_unplug_cpu();
1601 cpu_disable_common();
1604 * Disable the local APIC. Otherwise IPI broadcasts will reach
1605 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1608 * Disabling the APIC must happen after cpu_disable_common()
1609 * which invokes fixup_irqs().
1611 * Disabling the APIC preserves already set bits in IRR, but
1612 * an interrupt arriving after disabling the local APIC does not
1613 * set the corresponding IRR bit.
1615 * fixup_irqs() scans IRR for set bits so it can raise a not
1616 * yet handled interrupt on the new destination CPU via an IPI
1617 * but obviously it can't do so for IRR bits which are not set.
1618 * IOW, interrupts arriving after disabling the local APIC will
1621 apic_soft_disable();
1626 int common_cpu_die(unsigned int cpu)
1630 /* We don't do anything here: idle task is faking death itself. */
1632 /* They ack this in play_dead() by setting CPU_DEAD */
1633 if (cpu_wait_death(cpu, 5)) {
1634 if (system_state == SYSTEM_RUNNING)
1635 pr_info("CPU %u is now offline\n", cpu);
1637 pr_err("CPU %u didn't die...\n", cpu);
1644 void native_cpu_die(unsigned int cpu)
1646 common_cpu_die(cpu);
1649 void play_dead_common(void)
1654 (void)cpu_report_death();
1657 * With physical CPU hotplug, we should halt the cpu
1659 local_irq_disable();
1662 static bool wakeup_cpu0(void)
1664 if (smp_processor_id() == 0 && enable_start_cpu0)
1671 * We need to flush the caches before going to sleep, lest we have
1672 * dirty data in our caches when we come back up.
1674 static inline void mwait_play_dead(void)
1676 unsigned int eax, ebx, ecx, edx;
1677 unsigned int highest_cstate = 0;
1678 unsigned int highest_subcstate = 0;
1682 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1683 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1685 if (!this_cpu_has(X86_FEATURE_MWAIT))
1687 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1689 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1692 eax = CPUID_MWAIT_LEAF;
1694 native_cpuid(&eax, &ebx, &ecx, &edx);
1697 * eax will be 0 if EDX enumeration is not valid.
1698 * Initialized below to cstate, sub_cstate value when EDX is valid.
1700 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1703 edx >>= MWAIT_SUBSTATE_SIZE;
1704 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1705 if (edx & MWAIT_SUBSTATE_MASK) {
1707 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1710 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1711 (highest_subcstate - 1);
1715 * This should be a memory location in a cache line which is
1716 * unlikely to be touched by other processors. The actual
1717 * content is immaterial as it is not actually modified in any way.
1719 mwait_ptr = ¤t_thread_info()->flags;
1725 * The CLFLUSH is a workaround for erratum AAI65 for
1726 * the Xeon 7400 series. It's not clear it is actually
1727 * needed, but it should be harmless in either case.
1728 * The WBINVD is insufficient due to the spurious-wakeup
1729 * case where we return around the loop.
1734 __monitor(mwait_ptr, 0, 0);
1738 * If NMI wants to wake up CPU0, start CPU0.
1745 void hlt_play_dead(void)
1747 if (__this_cpu_read(cpu_info.x86) >= 4)
1753 * If NMI wants to wake up CPU0, start CPU0.
1760 void native_play_dead(void)
1763 tboot_shutdown(TB_SHUTDOWN_WFS);
1765 mwait_play_dead(); /* Only returns on failure */
1766 if (cpuidle_play_dead())
1770 #else /* ... !CONFIG_HOTPLUG_CPU */
1771 int native_cpu_disable(void)
1776 void native_cpu_die(unsigned int cpu)
1778 /* We said "no" in __cpu_disable */
1782 void native_play_dead(void)
1789 #ifdef CONFIG_X86_64
1791 * APERF/MPERF frequency ratio computation.
1793 * The scheduler wants to do frequency invariant accounting and needs a <1
1794 * ratio to account for the 'current' frequency, corresponding to
1795 * freq_curr / freq_max.
1797 * Since the frequency freq_curr on x86 is controlled by micro-controller and
1798 * our P-state setting is little more than a request/hint, we need to observe
1799 * the effective frequency 'BusyMHz', i.e. the average frequency over a time
1800 * interval after discarding idle time. This is given by:
1802 * BusyMHz = delta_APERF / delta_MPERF * freq_base
1804 * where freq_base is the max non-turbo P-state.
1806 * The freq_max term has to be set to a somewhat arbitrary value, because we
1807 * can't know which turbo states will be available at a given point in time:
1808 * it all depends on the thermal headroom of the entire package. We set it to
1809 * the turbo level with 4 cores active.
1811 * Benchmarks show that's a good compromise between the 1C turbo ratio
1812 * (freq_curr/freq_max would rarely reach 1) and something close to freq_base,
1813 * which would ignore the entire turbo range (a conspicuous part, making
1814 * freq_curr/freq_max always maxed out).
1816 * An exception to the heuristic above is the Atom uarch, where we choose the
1817 * highest turbo level for freq_max since Atom's are generally oriented towards
1820 * Setting freq_max to anything less than the 1C turbo ratio makes the ratio
1821 * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1.
1824 DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key);
1826 static DEFINE_PER_CPU(u64, arch_prev_aperf);
1827 static DEFINE_PER_CPU(u64, arch_prev_mperf);
1828 static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE;
1829 static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE;
1831 void arch_set_max_freq_ratio(bool turbo_disabled)
1833 arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE :
1834 arch_turbo_freq_ratio;
1836 EXPORT_SYMBOL_GPL(arch_set_max_freq_ratio);
1838 static bool turbo_disabled(void)
1843 err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en);
1847 return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
1850 static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1854 err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq);
1858 err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq);
1862 *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */
1863 *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */
1868 #include <asm/cpu_device_id.h>
1869 #include <asm/intel-family.h>
1871 #define X86_MATCH(model) \
1872 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \
1873 INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL)
1875 static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = {
1876 X86_MATCH(XEON_PHI_KNL),
1877 X86_MATCH(XEON_PHI_KNM),
1881 static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = {
1882 X86_MATCH(SKYLAKE_X),
1886 static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = {
1887 X86_MATCH(ATOM_GOLDMONT),
1888 X86_MATCH(ATOM_GOLDMONT_D),
1889 X86_MATCH(ATOM_GOLDMONT_PLUS),
1893 static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq,
1894 int num_delta_fratio)
1896 int fratio, delta_fratio, found;
1900 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1904 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1906 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1910 fratio = (msr >> 8) & 0xFF;
1914 if (found >= num_delta_fratio) {
1915 *turbo_freq = fratio;
1919 delta_fratio = (msr >> (i + 5)) & 0x7;
1923 fratio -= delta_fratio;
1932 static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size)
1938 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1942 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1944 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios);
1948 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts);
1952 for (i = 0; i < 64; i += 8) {
1953 group_size = (counts >> i) & 0xFF;
1954 if (group_size >= size) {
1955 *turbo_freq = (ratios >> i) & 0xFF;
1963 static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq)
1968 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq);
1972 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr);
1976 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */
1977 *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */
1979 /* The CPU may have less than 4 cores */
1981 *turbo_freq = msr & 0xFF; /* 1C turbo */
1986 static bool intel_set_max_freq_ratio(void)
1988 u64 base_freq, turbo_freq;
1991 if (slv_set_max_freq_ratio(&base_freq, &turbo_freq))
1994 if (x86_match_cpu(has_glm_turbo_ratio_limits) &&
1995 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
1998 if (x86_match_cpu(has_knl_turbo_ratio_limits) &&
1999 knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1))
2002 if (x86_match_cpu(has_skx_turbo_ratio_limits) &&
2003 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4))
2006 if (core_set_max_freq_ratio(&base_freq, &turbo_freq))
2013 * Some hypervisors advertise X86_FEATURE_APERFMPERF
2014 * but then fill all MSR's with zeroes.
2015 * Some CPUs have turbo boost but don't declare any turbo ratio
2016 * in MSR_TURBO_RATIO_LIMIT.
2018 if (!base_freq || !turbo_freq) {
2019 pr_debug("Couldn't determine cpu base or turbo frequency, necessary for scale-invariant accounting.\n");
2023 turbo_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, base_freq);
2025 pr_debug("Non-zero turbo and base frequencies led to a 0 ratio.\n");
2029 arch_turbo_freq_ratio = turbo_ratio;
2030 arch_set_max_freq_ratio(turbo_disabled());
2035 #ifdef CONFIG_ACPI_CPPC_LIB
2036 static bool amd_set_max_freq_ratio(void)
2038 struct cppc_perf_caps perf_caps;
2039 u64 highest_perf, nominal_perf;
2043 rc = cppc_get_perf_caps(0, &perf_caps);
2045 pr_debug("Could not retrieve perf counters (%d)\n", rc);
2049 highest_perf = perf_caps.highest_perf;
2050 nominal_perf = perf_caps.nominal_perf;
2052 if (!highest_perf || !nominal_perf) {
2053 pr_debug("Could not retrieve highest or nominal performance\n");
2057 perf_ratio = div_u64(highest_perf * SCHED_CAPACITY_SCALE, nominal_perf);
2058 /* midpoint between max_boost and max_P */
2059 perf_ratio = (perf_ratio + SCHED_CAPACITY_SCALE) >> 1;
2061 pr_debug("Non-zero highest/nominal perf values led to a 0 ratio\n");
2065 arch_turbo_freq_ratio = perf_ratio;
2066 arch_set_max_freq_ratio(false);
2071 static bool amd_set_max_freq_ratio(void)
2077 static void init_counter_refs(void)
2081 rdmsrl(MSR_IA32_APERF, aperf);
2082 rdmsrl(MSR_IA32_MPERF, mperf);
2084 this_cpu_write(arch_prev_aperf, aperf);
2085 this_cpu_write(arch_prev_mperf, mperf);
2088 #ifdef CONFIG_PM_SLEEP
2089 static struct syscore_ops freq_invariance_syscore_ops = {
2090 .resume = init_counter_refs,
2093 static void register_freq_invariance_syscore_ops(void)
2095 /* Bail out if registered already. */
2096 if (freq_invariance_syscore_ops.node.prev)
2099 register_syscore_ops(&freq_invariance_syscore_ops);
2102 static inline void register_freq_invariance_syscore_ops(void) {}
2105 static void init_freq_invariance(bool secondary, bool cppc_ready)
2109 if (!boot_cpu_has(X86_FEATURE_APERFMPERF))
2113 if (static_branch_likely(&arch_scale_freq_key)) {
2114 init_counter_refs();
2119 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2120 ret = intel_set_max_freq_ratio();
2121 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
2125 ret = amd_set_max_freq_ratio();
2129 init_counter_refs();
2130 static_branch_enable(&arch_scale_freq_key);
2131 register_freq_invariance_syscore_ops();
2132 pr_info("Estimated ratio of average max frequency by base frequency (times 1024): %llu\n", arch_max_freq_ratio);
2134 pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n");
2138 #ifdef CONFIG_ACPI_CPPC_LIB
2139 static DEFINE_MUTEX(freq_invariance_lock);
2141 void init_freq_invariance_cppc(void)
2143 static bool secondary;
2145 mutex_lock(&freq_invariance_lock);
2147 init_freq_invariance(secondary, true);
2150 mutex_unlock(&freq_invariance_lock);
2154 static void disable_freq_invariance_workfn(struct work_struct *work)
2156 static_branch_disable(&arch_scale_freq_key);
2159 static DECLARE_WORK(disable_freq_invariance_work,
2160 disable_freq_invariance_workfn);
2162 DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE;
2164 void arch_scale_freq_tick(void)
2166 u64 freq_scale = SCHED_CAPACITY_SCALE;
2170 if (!arch_scale_freq_invariant())
2173 rdmsrl(MSR_IA32_APERF, aperf);
2174 rdmsrl(MSR_IA32_MPERF, mperf);
2176 acnt = aperf - this_cpu_read(arch_prev_aperf);
2177 mcnt = mperf - this_cpu_read(arch_prev_mperf);
2179 this_cpu_write(arch_prev_aperf, aperf);
2180 this_cpu_write(arch_prev_mperf, mperf);
2182 if (check_shl_overflow(acnt, 2*SCHED_CAPACITY_SHIFT, &acnt))
2185 if (check_mul_overflow(mcnt, arch_max_freq_ratio, &mcnt) || !mcnt)
2188 freq_scale = div64_u64(acnt, mcnt);
2192 if (freq_scale > SCHED_CAPACITY_SCALE)
2193 freq_scale = SCHED_CAPACITY_SCALE;
2195 this_cpu_write(arch_freq_scale, freq_scale);
2199 pr_warn("Scheduler frequency invariance went wobbly, disabling!\n");
2200 schedule_work(&disable_freq_invariance_work);
2203 static inline void init_freq_invariance(bool secondary, bool cppc_ready)
2206 #endif /* CONFIG_X86_64 */