1 // SPDX-License-Identifier: GPL-2.0
3 * AMD Encrypted Register State Support
5 * Author: Joerg Roedel <jroedel@suse.de>
7 * This file is not compiled stand-alone. It contains code shared
8 * between the pre-decompression boot code and the running Linux kernel
9 * and is included directly into both code-bases.
13 * Boot VC Handler - This is the first VC handler during boot, there is no GHCB
14 * page yet, so it only supports the MSR based communication with the
15 * hypervisor and only the CPUID exit-code.
17 void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code)
19 unsigned int fn = lower_bits(regs->ax, 32);
22 /* Only CPUID is supported via MSR protocol */
23 if (exit_code != SVM_EXIT_CPUID)
26 sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EAX));
28 val = sev_es_rd_ghcb_msr();
29 if (GHCB_SEV_GHCB_RESP_CODE(val) != GHCB_SEV_CPUID_RESP)
33 sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EBX));
35 val = sev_es_rd_ghcb_msr();
36 if (GHCB_SEV_GHCB_RESP_CODE(val) != GHCB_SEV_CPUID_RESP)
40 sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_ECX));
42 val = sev_es_rd_ghcb_msr();
43 if (GHCB_SEV_GHCB_RESP_CODE(val) != GHCB_SEV_CPUID_RESP)
47 sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EDX));
49 val = sev_es_rd_ghcb_msr();
50 if (GHCB_SEV_GHCB_RESP_CODE(val) != GHCB_SEV_CPUID_RESP)
54 /* Skip over the CPUID two-byte opcode */
60 sev_es_wr_ghcb_msr(GHCB_SEV_TERMINATE);
63 /* Shouldn't get here - if we do halt the machine */
65 asm volatile("hlt\n");