2 * Copyright (C) 1995 Linus Torvalds
6 * This file handles the architecture-dependent parts of initialization
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/a.out.h>
19 #include <linux/screen_info.h>
20 #include <linux/ioport.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/initrd.h>
24 #include <linux/highmem.h>
25 #include <linux/bootmem.h>
26 #include <linux/module.h>
27 #include <asm/processor.h>
28 #include <linux/console.h>
29 #include <linux/seq_file.h>
30 #include <linux/crash_dump.h>
31 #include <linux/root_dev.h>
32 #include <linux/pci.h>
33 #include <linux/efi.h>
34 #include <linux/acpi.h>
35 #include <linux/kallsyms.h>
36 #include <linux/edd.h>
37 #include <linux/mmzone.h>
38 #include <linux/kexec.h>
39 #include <linux/cpufreq.h>
40 #include <linux/dmi.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/ctype.h>
43 #include <linux/uaccess.h>
44 #include <linux/init_ohci1394_dma.h>
47 #include <asm/uaccess.h>
48 #include <asm/system.h>
49 #include <asm/vsyscall.h>
54 #include <video/edid.h>
58 #include <asm/mpspec.h>
59 #include <asm/mmu_context.h>
60 #include <asm/proto.h>
61 #include <asm/setup.h>
62 #include <asm/mach_apic.h>
64 #include <asm/sections.h>
66 #include <asm/cacheflush.h>
69 #include <asm/topology.h>
71 #ifdef CONFIG_PARAVIRT
72 #include <asm/paravirt.h>
81 struct cpuinfo_x86 boot_cpu_data __read_mostly;
82 EXPORT_SYMBOL(boot_cpu_data);
84 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
86 unsigned long mmu_cr4_features;
88 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
91 unsigned long saved_video_mode;
93 int force_mwait __cpuinitdata;
99 char dmi_alloc_data[DMI_MAX_DATA];
104 struct screen_info screen_info;
105 EXPORT_SYMBOL(screen_info);
106 struct sys_desc_table_struct {
107 unsigned short length;
108 unsigned char table[0];
111 struct edid_info edid_info;
112 EXPORT_SYMBOL_GPL(edid_info);
114 extern int root_mountflags;
116 char __initdata command_line[COMMAND_LINE_SIZE];
118 struct resource standard_io_resources[] = {
119 { .name = "dma1", .start = 0x00, .end = 0x1f,
120 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
121 { .name = "pic1", .start = 0x20, .end = 0x21,
122 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
123 { .name = "timer0", .start = 0x40, .end = 0x43,
124 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
125 { .name = "timer1", .start = 0x50, .end = 0x53,
126 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
127 { .name = "keyboard", .start = 0x60, .end = 0x6f,
128 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
129 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
130 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
131 { .name = "pic2", .start = 0xa0, .end = 0xa1,
132 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
133 { .name = "dma2", .start = 0xc0, .end = 0xdf,
134 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
135 { .name = "fpu", .start = 0xf0, .end = 0xff,
136 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
139 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
141 static struct resource data_resource = {
142 .name = "Kernel data",
145 .flags = IORESOURCE_RAM,
147 static struct resource code_resource = {
148 .name = "Kernel code",
151 .flags = IORESOURCE_RAM,
153 static struct resource bss_resource = {
154 .name = "Kernel bss",
157 .flags = IORESOURCE_RAM,
160 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
162 #ifdef CONFIG_PROC_VMCORE
163 /* elfcorehdr= specifies the location of elf core header
164 * stored by the crashed kernel. This option will be passed
165 * by kexec loader to the capture kernel.
167 static int __init setup_elfcorehdr(char *arg)
172 elfcorehdr_addr = memparse(arg, &end);
173 return end > arg ? 0 : -EINVAL;
175 early_param("elfcorehdr", setup_elfcorehdr);
180 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
182 unsigned long bootmap_size, bootmap;
184 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
185 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
188 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
189 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
190 e820_register_active_regions(0, start_pfn, end_pfn);
191 free_bootmem_with_active_regions(0, end_pfn);
192 reserve_bootmem(bootmap, bootmap_size);
196 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
198 #ifdef CONFIG_EDD_MODULE
202 * copy_edd() - Copy the BIOS EDD information
203 * from boot_params into a safe place.
206 static inline void copy_edd(void)
208 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
209 sizeof(edd.mbr_signature));
210 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
211 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
212 edd.edd_info_nr = boot_params.eddbuf_entries;
215 static inline void copy_edd(void)
221 static void __init reserve_crashkernel(void)
223 unsigned long long free_mem;
224 unsigned long long crash_size, crash_base;
228 ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
230 ret = parse_crashkernel(boot_command_line, free_mem,
231 &crash_size, &crash_base);
232 if (ret == 0 && crash_size) {
233 if (crash_base > 0) {
234 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
235 "for crashkernel (System RAM: %ldMB)\n",
236 (unsigned long)(crash_size >> 20),
237 (unsigned long)(crash_base >> 20),
238 (unsigned long)(free_mem >> 20));
239 crashk_res.start = crash_base;
240 crashk_res.end = crash_base + crash_size - 1;
241 reserve_bootmem(crash_base, crash_size);
243 printk(KERN_INFO "crashkernel reservation failed - "
244 "you have to specify a base address\n");
248 static inline void __init reserve_crashkernel(void)
252 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
253 void __attribute__((weak)) __init memory_setup(void)
255 machine_specific_memory_setup();
259 * setup_arch - architecture-specific boot-time initializations
261 * Note: On x86_64, fixmaps are ready for use even before this is called.
263 void __init setup_arch(char **cmdline_p)
267 printk(KERN_INFO "Command line: %s\n", boot_command_line);
269 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
270 screen_info = boot_params.screen_info;
271 edid_info = boot_params.edid_info;
272 saved_video_mode = boot_params.hdr.vid_mode;
273 bootloader_type = boot_params.hdr.type_of_loader;
275 #ifdef CONFIG_BLK_DEV_RAM
276 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
277 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
278 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
281 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
291 if (!boot_params.hdr.root_flags)
292 root_mountflags &= ~MS_RDONLY;
293 init_mm.start_code = (unsigned long) &_text;
294 init_mm.end_code = (unsigned long) &_etext;
295 init_mm.end_data = (unsigned long) &_edata;
296 init_mm.brk = (unsigned long) &_end;
298 code_resource.start = virt_to_phys(&_text);
299 code_resource.end = virt_to_phys(&_etext)-1;
300 data_resource.start = virt_to_phys(&_etext);
301 data_resource.end = virt_to_phys(&_edata)-1;
302 bss_resource.start = virt_to_phys(&__bss_start);
303 bss_resource.end = virt_to_phys(&__bss_stop)-1;
305 early_identify_cpu(&boot_cpu_data);
307 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
308 *cmdline_p = command_line;
312 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
313 if (init_ohci1394_dma_early)
314 init_ohci1394_dma_on_all_controllers();
317 finish_e820_parsing();
319 early_gart_iommu_check();
321 e820_register_active_regions(0, 0, -1UL);
323 * partially used pages are not usable - thus
324 * we are rounding upwards:
326 end_pfn = e820_end_of_ram();
327 /* update e820 for memory not covered by WB MTRRs */
329 if (mtrr_trim_uncached_memory(end_pfn)) {
330 e820_register_active_regions(0, 0, -1UL);
331 end_pfn = e820_end_of_ram();
334 num_physpages = end_pfn;
338 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
347 /* setup to use the early static init tables during kernel startup */
348 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
349 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
351 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
357 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
358 * Call this early for SRAT node setup.
360 acpi_boot_table_init();
363 /* How many end-of-memory variables you have, grandma! */
364 max_low_pfn = end_pfn;
366 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
368 /* Remove active ranges so rediscovery with NUMA-awareness happens */
369 remove_all_active_ranges();
371 #ifdef CONFIG_ACPI_NUMA
373 * Parse SRAT to discover nodes.
379 numa_initmem_init(0, end_pfn);
381 contig_initmem_init(0, end_pfn);
384 early_res_to_bootmem();
386 #ifdef CONFIG_ACPI_SLEEP
388 * Reserve low memory region for sleep support.
390 acpi_reserve_bootmem();
394 efi_reserve_bootmem();
397 * Find and reserve possible boot-time SMP configuration:
400 #ifdef CONFIG_BLK_DEV_INITRD
401 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
402 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
403 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
404 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
405 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
407 if (ramdisk_end <= end_of_mem) {
408 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
409 initrd_start = ramdisk_image + PAGE_OFFSET;
410 initrd_end = initrd_start+ramdisk_size;
412 /* Assumes everything on node 0 */
413 free_bootmem(ramdisk_image, ramdisk_size);
414 printk(KERN_ERR "initrd extends beyond end of memory "
415 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
416 ramdisk_end, end_of_mem);
421 reserve_crashkernel();
429 * Read APIC and some other early information from ACPI tables.
437 * get boot-time SMP configuration:
439 if (smp_found_config)
441 init_apic_mappings();
442 ioapic_init_mappings();
445 * We trust e820 completely. No explicit ROM probing in memory.
447 e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
448 e820_mark_nosave_regions();
450 /* request I/O space for devices used on all i[345]86 PCs */
451 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
452 request_resource(&ioport_resource, &standard_io_resources[i]);
457 #if defined(CONFIG_VGA_CONSOLE)
458 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
459 conswitchp = &vga_con;
460 #elif defined(CONFIG_DUMMY_CONSOLE)
461 conswitchp = &dummy_con;
466 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
470 if (c->extended_cpuid_level < 0x80000004)
473 v = (unsigned int *) c->x86_model_id;
474 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
475 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
476 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
477 c->x86_model_id[48] = 0;
482 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
484 unsigned int n, dummy, eax, ebx, ecx, edx;
486 n = c->extended_cpuid_level;
488 if (n >= 0x80000005) {
489 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
490 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
491 "D cache %dK (%d bytes/line)\n",
492 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
493 c->x86_cache_size = (ecx>>24) + (edx>>24);
494 /* On K8 L1 TLB is inclusive, so don't count it */
498 if (n >= 0x80000006) {
499 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
500 ecx = cpuid_ecx(0x80000006);
501 c->x86_cache_size = ecx >> 16;
502 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
504 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
505 c->x86_cache_size, ecx & 0xFF);
507 if (n >= 0x80000008) {
508 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
509 c->x86_virt_bits = (eax >> 8) & 0xff;
510 c->x86_phys_bits = eax & 0xff;
515 static int nearby_node(int apicid)
519 for (i = apicid - 1; i >= 0; i--) {
520 node = apicid_to_node[i];
521 if (node != NUMA_NO_NODE && node_online(node))
524 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
525 node = apicid_to_node[i];
526 if (node != NUMA_NO_NODE && node_online(node))
529 return first_node(node_online_map); /* Shouldn't happen */
534 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
535 * Assumes number of cores is a power of two.
537 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
542 int cpu = smp_processor_id();
544 unsigned apicid = hard_smp_processor_id();
546 bits = c->x86_coreid_bits;
548 /* Low order bits define the core id (index of core in socket) */
549 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
550 /* Convert the APIC ID into the socket ID */
551 c->phys_proc_id = phys_pkg_id(bits);
554 node = c->phys_proc_id;
555 if (apicid_to_node[apicid] != NUMA_NO_NODE)
556 node = apicid_to_node[apicid];
557 if (!node_online(node)) {
558 /* Two possibilities here:
559 - The CPU is missing memory and no node was created.
560 In that case try picking one from a nearby CPU
561 - The APIC IDs differ from the HyperTransport node IDs
562 which the K8 northbridge parsing fills in.
563 Assume they are all increased by a constant offset,
564 but in the same order as the HT nodeids.
565 If that doesn't result in a usable node fall back to the
566 path for the previous case. */
568 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
570 if (ht_nodeid >= 0 &&
571 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
572 node = apicid_to_node[ht_nodeid];
573 /* Pick a nearby node */
574 if (!node_online(node))
575 node = nearby_node(apicid);
577 numa_set_node(cpu, node);
579 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
584 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
589 /* Multi core CPU? */
590 if (c->extended_cpuid_level < 0x80000008)
593 ecx = cpuid_ecx(0x80000008);
595 c->x86_max_cores = (ecx & 0xff) + 1;
597 /* CPU telling us the core id bits shift? */
598 bits = (ecx >> 12) & 0xF;
600 /* Otherwise recompute */
602 while ((1 << bits) < c->x86_max_cores)
606 c->x86_coreid_bits = bits;
611 #define ENABLE_C1E_MASK 0x18000000
612 #define CPUID_PROCESSOR_SIGNATURE 1
613 #define CPUID_XFAM 0x0ff00000
614 #define CPUID_XFAM_K8 0x00000000
615 #define CPUID_XFAM_10H 0x00100000
616 #define CPUID_XFAM_11H 0x00200000
617 #define CPUID_XMOD 0x000f0000
618 #define CPUID_XMOD_REV_F 0x00040000
620 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
621 static __cpuinit int amd_apic_timer_broken(void)
623 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
625 switch (eax & CPUID_XFAM) {
627 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
631 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
632 if (lo & ENABLE_C1E_MASK)
636 /* err on the side of caution */
642 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
644 early_init_amd_mc(c);
646 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
647 if (c->x86_power & (1<<8))
648 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
651 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
659 * Disable TLB flush filter by setting HWCR.FFDIS on K8
660 * bit 6 of msr C001_0015
662 * Errata 63 for SH-B3 steppings
663 * Errata 122 for all steppings (F+ have it disabled by default)
666 rdmsrl(MSR_K8_HWCR, value);
668 wrmsrl(MSR_K8_HWCR, value);
672 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
673 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
674 clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
676 /* On C+ stepping K8 rep microcode works well for copy/memset */
677 level = cpuid_eax(1);
678 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
680 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
681 if (c->x86 == 0x10 || c->x86 == 0x11)
682 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
684 /* Enable workaround for FXSAVE leak */
686 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
688 level = get_model_name(c);
692 /* Should distinguish Models here, but this is only
693 a fallback anyways. */
694 strcpy(c->x86_model_id, "Hammer");
698 display_cacheinfo(c);
700 /* Multi core CPU? */
701 if (c->extended_cpuid_level >= 0x80000008)
704 if (c->extended_cpuid_level >= 0x80000006 &&
705 (cpuid_edx(0x80000006) & 0xf000))
706 num_cache_leaves = 4;
708 num_cache_leaves = 3;
710 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
711 set_cpu_cap(c, X86_FEATURE_K8);
713 /* MFENCE stops RDTSC speculation */
714 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
716 if (amd_apic_timer_broken())
717 disable_apic_timer = 1;
720 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
723 u32 eax, ebx, ecx, edx;
724 int index_msb, core_bits;
726 cpuid(1, &eax, &ebx, &ecx, &edx);
729 if (!cpu_has(c, X86_FEATURE_HT))
731 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
734 smp_num_siblings = (ebx & 0xff0000) >> 16;
736 if (smp_num_siblings == 1) {
737 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
738 } else if (smp_num_siblings > 1) {
740 if (smp_num_siblings > NR_CPUS) {
741 printk(KERN_WARNING "CPU: Unsupported number of "
742 "siblings %d", smp_num_siblings);
743 smp_num_siblings = 1;
747 index_msb = get_count_order(smp_num_siblings);
748 c->phys_proc_id = phys_pkg_id(index_msb);
750 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
752 index_msb = get_count_order(smp_num_siblings);
754 core_bits = get_count_order(c->x86_max_cores);
756 c->cpu_core_id = phys_pkg_id(index_msb) &
757 ((1 << core_bits) - 1);
760 if ((c->x86_max_cores * smp_num_siblings) > 1) {
761 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
763 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
771 * find out the number of processor cores on the die
773 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
777 if (c->cpuid_level < 4)
780 cpuid_count(4, 0, &eax, &t, &t, &t);
783 return ((eax >> 26) + 1);
788 static void srat_detect_node(void)
792 int cpu = smp_processor_id();
793 int apicid = hard_smp_processor_id();
795 /* Don't do the funky fallback heuristics the AMD version employs
797 node = apicid_to_node[apicid];
798 if (node == NUMA_NO_NODE)
799 node = first_node(node_online_map);
800 numa_set_node(cpu, node);
802 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
806 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
808 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
809 (c->x86 == 0x6 && c->x86_model >= 0x0e))
810 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
813 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
818 init_intel_cacheinfo(c);
819 if (c->cpuid_level > 9) {
820 unsigned eax = cpuid_eax(10);
821 /* Check for version and the number of counters */
822 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
823 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
828 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
830 set_cpu_cap(c, X86_FEATURE_BTS);
832 set_cpu_cap(c, X86_FEATURE_PEBS);
839 n = c->extended_cpuid_level;
840 if (n >= 0x80000008) {
841 unsigned eax = cpuid_eax(0x80000008);
842 c->x86_virt_bits = (eax >> 8) & 0xff;
843 c->x86_phys_bits = eax & 0xff;
844 /* CPUID workaround for Intel 0F34 CPU */
845 if (c->x86_vendor == X86_VENDOR_INTEL &&
846 c->x86 == 0xF && c->x86_model == 0x3 &&
848 c->x86_phys_bits = 36;
852 c->x86_cache_alignment = c->x86_clflush_size * 2;
853 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
854 (c->x86 == 0x6 && c->x86_model >= 0x0e))
855 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
857 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
858 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
859 c->x86_max_cores = intel_num_cpu_cores(c);
864 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
866 char *v = c->x86_vendor_id;
868 if (!strcmp(v, "AuthenticAMD"))
869 c->x86_vendor = X86_VENDOR_AMD;
870 else if (!strcmp(v, "GenuineIntel"))
871 c->x86_vendor = X86_VENDOR_INTEL;
873 c->x86_vendor = X86_VENDOR_UNKNOWN;
876 /* Do some early cpuid on the boot CPU to get some parameter that are
877 needed before check_bugs. Everything advanced is in identify_cpu
879 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
883 c->loops_per_jiffy = loops_per_jiffy;
884 c->x86_cache_size = -1;
885 c->x86_vendor = X86_VENDOR_UNKNOWN;
886 c->x86_model = c->x86_mask = 0; /* So far unknown... */
887 c->x86_vendor_id[0] = '\0'; /* Unset */
888 c->x86_model_id[0] = '\0'; /* Unset */
889 c->x86_clflush_size = 64;
890 c->x86_cache_alignment = c->x86_clflush_size;
891 c->x86_max_cores = 1;
892 c->x86_coreid_bits = 0;
893 c->extended_cpuid_level = 0;
894 memset(&c->x86_capability, 0, sizeof c->x86_capability);
896 /* Get vendor name */
897 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
898 (unsigned int *)&c->x86_vendor_id[0],
899 (unsigned int *)&c->x86_vendor_id[8],
900 (unsigned int *)&c->x86_vendor_id[4]);
904 /* Initialize the standard set of capabilities */
905 /* Note that the vendor-specific code below might override */
907 /* Intel-defined flags: level 0x00000001 */
908 if (c->cpuid_level >= 0x00000001) {
910 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
911 &c->x86_capability[0]);
912 c->x86 = (tfms >> 8) & 0xf;
913 c->x86_model = (tfms >> 4) & 0xf;
914 c->x86_mask = tfms & 0xf;
916 c->x86 += (tfms >> 20) & 0xff;
918 c->x86_model += ((tfms >> 16) & 0xF) << 4;
919 if (c->x86_capability[0] & (1<<19))
920 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
922 /* Have CPUID level 0 only - unheard of */
927 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
929 /* AMD-defined flags: level 0x80000001 */
930 xlvl = cpuid_eax(0x80000000);
931 c->extended_cpuid_level = xlvl;
932 if ((xlvl & 0xffff0000) == 0x80000000) {
933 if (xlvl >= 0x80000001) {
934 c->x86_capability[1] = cpuid_edx(0x80000001);
935 c->x86_capability[6] = cpuid_ecx(0x80000001);
937 if (xlvl >= 0x80000004)
938 get_model_name(c); /* Default name */
941 /* Transmeta-defined flags: level 0x80860001 */
942 xlvl = cpuid_eax(0x80860000);
943 if ((xlvl & 0xffff0000) == 0x80860000) {
944 /* Don't set x86_cpuid_level here for now to not confuse. */
945 if (xlvl >= 0x80860001)
946 c->x86_capability[2] = cpuid_edx(0x80860001);
949 c->extended_cpuid_level = cpuid_eax(0x80000000);
950 if (c->extended_cpuid_level >= 0x80000007)
951 c->x86_power = cpuid_edx(0x80000007);
953 switch (c->x86_vendor) {
957 case X86_VENDOR_INTEL:
965 * This does the hard work of actually picking apart the CPU stuff...
967 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
971 early_identify_cpu(c);
973 init_scattered_cpuid_features(c);
975 c->apicid = phys_pkg_id(0);
978 * Vendor-specific initialization. In this section we
979 * canonicalize the feature flags, meaning if there are
980 * features a certain CPU supports which CPUID doesn't
981 * tell us, CPUID claiming incorrect flags, or other bugs,
982 * we handle them here.
984 * At the end of this section, c->x86_capability better
985 * indicate the features this CPU genuinely supports!
987 switch (c->x86_vendor) {
992 case X86_VENDOR_INTEL:
996 case X86_VENDOR_UNKNOWN:
998 display_cacheinfo(c);
1005 * On SMP, boot_cpu_data holds the common feature set between
1006 * all CPUs; so make sure that we indicate which features are
1007 * common between the CPUs. The first time this routine gets
1008 * executed, c == &boot_cpu_data.
1010 if (c != &boot_cpu_data) {
1011 /* AND the already accumulated flags with these */
1012 for (i = 0; i < NCAPINTS; i++)
1013 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1016 /* Clear all flags overriden by options */
1017 for (i = 0; i < NCAPINTS; i++)
1018 c->x86_capability[i] ^= cleared_cpu_caps[i];
1020 #ifdef CONFIG_X86_MCE
1023 select_idle_routine(c);
1025 if (c != &boot_cpu_data)
1028 numa_add_cpu(smp_processor_id());
1033 static __init int setup_noclflush(char *arg)
1035 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1038 __setup("noclflush", setup_noclflush);
1040 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1042 if (c->x86_model_id[0])
1043 printk(KERN_INFO "%s", c->x86_model_id);
1045 if (c->x86_mask || c->cpuid_level >= 0)
1046 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1048 printk(KERN_CONT "\n");
1051 static __init int setup_disablecpuid(char *arg)
1054 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1055 setup_clear_cpu_cap(bit);
1060 __setup("clearcpuid=", setup_disablecpuid);
1063 * Get CPU information for use by the procfs.
1066 static int show_cpuinfo(struct seq_file *m, void *v)
1068 struct cpuinfo_x86 *c = v;
1072 * These flag bits must match the definitions in <asm/cpufeature.h>.
1073 * NULL means this bit is undefined or reserved; either way it doesn't
1074 * have meaning as far as Linux is concerned. Note that it's important
1075 * to realize there is a difference between this table and CPUID -- if
1076 * applications want to get the raw CPUID data, they should access
1077 * /dev/cpu/<cpu_nr>/cpuid instead.
1079 static const char *const x86_cap_flags[] = {
1081 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1082 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1083 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1084 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
1087 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1088 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1089 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1090 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
1091 "3dnowext", "3dnow",
1093 /* Transmeta-defined */
1094 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1095 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1096 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1097 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1099 /* Other (Linux-defined) */
1100 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
1101 NULL, NULL, NULL, NULL,
1102 "constant_tsc", "up", NULL, "arch_perfmon",
1103 "pebs", "bts", NULL, "sync_rdtsc",
1104 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1107 /* Intel-defined (#2) */
1108 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1109 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
1110 NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
1111 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1113 /* VIA/Cyrix/Centaur-defined */
1114 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1115 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1116 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1119 /* AMD-defined (#2) */
1120 "lahf_lm", "cmp_legacy", "svm", "extapic",
1121 "cr8_legacy", "abm", "sse4a", "misalignsse",
1122 "3dnowprefetch", "osvw", "ibs", "sse5",
1123 "skinit", "wdt", NULL, NULL,
1124 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1125 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1127 /* Auxiliary (Linux-defined) */
1128 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1129 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1130 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1131 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1133 static const char *const x86_power_flags[] = {
1134 "ts", /* temperature sensor */
1135 "fid", /* frequency id control */
1136 "vid", /* voltage id control */
1137 "ttp", /* thermal trip */
1142 "", /* tsc invariant mapped to constant_tsc */
1151 seq_printf(m, "processor\t: %u\n"
1153 "cpu family\t: %d\n"
1155 "model name\t: %s\n",
1157 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1160 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1162 if (c->x86_mask || c->cpuid_level >= 0)
1163 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1165 seq_printf(m, "stepping\t: unknown\n");
1167 if (cpu_has(c, X86_FEATURE_TSC)) {
1168 unsigned int freq = cpufreq_quick_get((unsigned)cpu);
1172 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1173 freq / 1000, (freq % 1000));
1177 if (c->x86_cache_size >= 0)
1178 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1181 if (smp_num_siblings * c->x86_max_cores > 1) {
1182 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1183 seq_printf(m, "siblings\t: %d\n",
1184 cpus_weight(per_cpu(cpu_core_map, cpu)));
1185 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1186 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1192 "fpu_exception\t: yes\n"
1193 "cpuid level\t: %d\n"
1198 for (i = 0; i < 32*NCAPINTS; i++)
1199 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1200 seq_printf(m, " %s", x86_cap_flags[i]);
1202 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1203 c->loops_per_jiffy/(500000/HZ),
1204 (c->loops_per_jiffy/(5000/HZ)) % 100);
1206 if (c->x86_tlbsize > 0)
1207 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1208 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1209 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1211 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1212 c->x86_phys_bits, c->x86_virt_bits);
1214 seq_printf(m, "power management:");
1215 for (i = 0; i < 32; i++) {
1216 if (c->x86_power & (1 << i)) {
1217 if (i < ARRAY_SIZE(x86_power_flags) &&
1219 seq_printf(m, "%s%s",
1220 x86_power_flags[i][0]?" ":"",
1221 x86_power_flags[i]);
1223 seq_printf(m, " [%d]", i);
1227 seq_printf(m, "\n\n");
1232 static void *c_start(struct seq_file *m, loff_t *pos)
1234 if (*pos == 0) /* just in case, cpu 0 is not the first */
1235 *pos = first_cpu(cpu_online_map);
1236 if ((*pos) < NR_CPUS && cpu_online(*pos))
1237 return &cpu_data(*pos);
1241 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1243 *pos = next_cpu(*pos, cpu_online_map);
1244 return c_start(m, pos);
1247 static void c_stop(struct seq_file *m, void *v)
1251 const struct seq_operations cpuinfo_op = {
1255 .show = show_cpuinfo,