2 * Copyright (C) 1995 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
9 * This file handles the architecture-dependent parts of process handling..
12 #include <linux/cpu.h>
13 #include <linux/errno.h>
14 #include <linux/sched.h>
16 #include <linux/kernel.h>
18 #include <linux/elfcore.h>
19 #include <linux/smp.h>
20 #include <linux/stddef.h>
21 #include <linux/slab.h>
22 #include <linux/vmalloc.h>
23 #include <linux/user.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/reboot.h>
27 #include <linux/mc146818rtc.h>
28 #include <linux/export.h>
29 #include <linux/kallsyms.h>
30 #include <linux/ptrace.h>
31 #include <linux/personality.h>
32 #include <linux/percpu.h>
33 #include <linux/prctl.h>
34 #include <linux/ftrace.h>
35 #include <linux/uaccess.h>
37 #include <linux/kdebug.h>
39 #include <asm/pgtable.h>
41 #include <asm/processor.h>
42 #include <asm/fpu/internal.h>
44 #ifdef CONFIG_MATH_EMULATION
45 #include <asm/math_emu.h>
48 #include <linux/err.h>
50 #include <asm/tlbflush.h>
53 #include <asm/syscalls.h>
54 #include <asm/debugreg.h>
55 #include <asm/switch_to.h>
57 #include <asm/intel_rdt.h>
59 void __show_regs(struct pt_regs *regs, int all)
61 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
62 unsigned long d0, d1, d2, d3, d6, d7;
64 unsigned short ss, gs;
66 if (user_mode(regs)) {
68 ss = regs->ss & 0xffff;
69 gs = get_user_gs(regs);
71 sp = kernel_stack_pointer(regs);
76 printk(KERN_DEFAULT "EIP: %04x:[<%08lx>] EFLAGS: %08lx CPU: %d\n",
77 (u16)regs->cs, regs->ip, regs->flags,
79 print_symbol("EIP is at %s\n", regs->ip);
81 printk(KERN_DEFAULT "EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
82 regs->ax, regs->bx, regs->cx, regs->dx);
83 printk(KERN_DEFAULT "ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
84 regs->si, regs->di, regs->bp, sp);
85 printk(KERN_DEFAULT " DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
86 (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, ss);
95 printk(KERN_DEFAULT "CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
105 /* Only print out debug registers if they are in their non-default state. */
106 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
107 (d6 == DR6_RESERVED) && (d7 == 0x400))
110 printk(KERN_DEFAULT "DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
112 printk(KERN_DEFAULT "DR6: %08lx DR7: %08lx\n",
116 void release_thread(struct task_struct *dead_task)
118 BUG_ON(dead_task->mm);
119 release_vm86_irqs(dead_task);
122 int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
123 unsigned long arg, struct task_struct *p, unsigned long tls)
125 struct pt_regs *childregs = task_pt_regs(p);
126 struct fork_frame *fork_frame = container_of(childregs, struct fork_frame, regs);
127 struct inactive_task_frame *frame = &fork_frame->frame;
128 struct task_struct *tsk;
132 frame->ret_addr = (unsigned long) ret_from_fork;
133 p->thread.sp = (unsigned long) fork_frame;
134 p->thread.sp0 = (unsigned long) (childregs+1);
135 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
137 if (unlikely(p->flags & PF_KTHREAD)) {
139 memset(childregs, 0, sizeof(struct pt_regs));
140 frame->bx = sp; /* function */
142 p->thread.io_bitmap_ptr = NULL;
146 *childregs = *current_pt_regs();
151 task_user_gs(p) = get_user_gs(current_pt_regs());
153 p->thread.io_bitmap_ptr = NULL;
157 if (unlikely(test_tsk_thread_flag(tsk, TIF_IO_BITMAP))) {
158 p->thread.io_bitmap_ptr = kmemdup(tsk->thread.io_bitmap_ptr,
159 IO_BITMAP_BYTES, GFP_KERNEL);
160 if (!p->thread.io_bitmap_ptr) {
161 p->thread.io_bitmap_max = 0;
164 set_tsk_thread_flag(p, TIF_IO_BITMAP);
170 * Set a new TLS for the child thread?
172 if (clone_flags & CLONE_SETTLS)
173 err = do_set_thread_area(p, -1,
174 (struct user_desc __user *)tls, 0);
176 if (err && p->thread.io_bitmap_ptr) {
177 kfree(p->thread.io_bitmap_ptr);
178 p->thread.io_bitmap_max = 0;
184 start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
186 set_user_gs(regs, 0);
188 regs->ds = __USER_DS;
189 regs->es = __USER_DS;
190 regs->ss = __USER_DS;
191 regs->cs = __USER_CS;
194 regs->flags = X86_EFLAGS_IF;
197 EXPORT_SYMBOL_GPL(start_thread);
201 * switch_to(x,y) should switch tasks from x to y.
203 * We fsave/fwait so that an exception goes off at the right time
204 * (as a call from the fsave or fwait in effect) rather than to
205 * the wrong process. Lazy FP saving no longer makes any sense
206 * with modern CPU's, and this simplifies a lot of things (SMP
207 * and UP become the same).
209 * NOTE! We used to use the x86 hardware context switching. The
210 * reason for not using it any more becomes apparent when you
211 * try to recover gracefully from saved state that is no longer
212 * valid (stale segment register values in particular). With the
213 * hardware task-switch, there is no way to fix up bad state in
214 * a reasonable manner.
216 * The fact that Intel documents the hardware task-switching to
217 * be slow is a fairly red herring - this code is not noticeably
218 * faster. However, there _is_ some room for improvement here,
219 * so the performance issues may eventually be a valid point.
220 * More important, however, is the fact that this allows us much
223 * The return value (in %ax) will be the "prev" task after
224 * the task-switch, and shows up in ret_from_fork in entry.S,
227 __visible __notrace_funcgraph struct task_struct *
228 __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
230 struct thread_struct *prev = &prev_p->thread,
231 *next = &next_p->thread;
232 struct fpu *prev_fpu = &prev->fpu;
233 struct fpu *next_fpu = &next->fpu;
234 int cpu = smp_processor_id();
235 struct tss_struct *tss = &per_cpu(cpu_tss, cpu);
236 fpu_switch_t fpu_switch;
238 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
240 fpu_switch = switch_fpu_prepare(prev_fpu, next_fpu, cpu);
243 * Save away %gs. No need to save %fs, as it was saved on the
244 * stack on entry. No need to save %es and %ds, as those are
245 * always kernel segments while inside the kernel. Doing this
246 * before setting the new TLS descriptors avoids the situation
247 * where we temporarily have non-reloadable segments in %fs
248 * and %gs. This could be an issue if the NMI handler ever
249 * used %fs or %gs (it does not today), or if the kernel is
250 * running inside of a hypervisor layer.
252 lazy_save_gs(prev->gs);
255 * Load the per-thread Thread-Local Storage descriptor.
260 * Restore IOPL if needed. In normal use, the flags restore
261 * in the switch assembly will handle this. But if the kernel
262 * is running virtualized at a non-zero CPL, the popf will
263 * not restore flags, so it must be done in a separate step.
265 if (get_kernel_rpl() && unlikely(prev->iopl != next->iopl))
266 set_iopl_mask(next->iopl);
269 * Now maybe handle debug registers and/or IO bitmaps
271 if (unlikely(task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV ||
272 task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT))
273 __switch_to_xtra(prev_p, next_p, tss);
276 * Leave lazy mode, flushing any hypercalls made here.
277 * This must be done before restoring TLS segments so
278 * the GDT and LDT are properly updated, and must be
279 * done before fpu__restore(), so the TS bit is up
282 arch_end_context_switch(next_p);
285 * Reload esp0 and cpu_current_top_of_stack. This changes
286 * current_thread_info().
289 this_cpu_write(cpu_current_top_of_stack,
290 (unsigned long)task_stack_page(next_p) +
294 * Restore %gs if needed (which is common)
296 if (prev->gs | next->gs)
297 lazy_load_gs(next->gs);
299 switch_fpu_finish(next_fpu, fpu_switch);
301 this_cpu_write(current_task, next_p);
303 /* Load the Intel cache allocation PQR MSR. */
304 intel_rdt_sched_in();