1 // SPDX-License-Identifier: GPL-2.0
2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
4 #include <linux/errno.h>
5 #include <linux/kernel.h>
8 #include <linux/prctl.h>
9 #include <linux/slab.h>
10 #include <linux/sched.h>
11 #include <linux/sched/idle.h>
12 #include <linux/sched/debug.h>
13 #include <linux/sched/task.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/init.h>
16 #include <linux/export.h>
18 #include <linux/tick.h>
19 #include <linux/random.h>
20 #include <linux/user-return-notifier.h>
21 #include <linux/dmi.h>
22 #include <linux/utsname.h>
23 #include <linux/stackprotector.h>
24 #include <linux/cpuidle.h>
25 #include <linux/acpi.h>
26 #include <linux/elf-randomize.h>
27 #include <trace/events/power.h>
28 #include <linux/hw_breakpoint.h>
31 #include <linux/uaccess.h>
32 #include <asm/mwait.h>
33 #include <asm/fpu/internal.h>
34 #include <asm/debugreg.h>
36 #include <asm/tlbflush.h>
39 #include <asm/switch_to.h>
41 #include <asm/prctl.h>
42 #include <asm/spec-ctrl.h>
43 #include <asm/io_bitmap.h>
44 #include <asm/proto.h>
49 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
50 * no more per-task TSS's. The TSS size is kept cacheline-aligned
51 * so they are allowed to end up in the .data..cacheline_aligned
52 * section. Since TSS's are completely CPU-local, we want them
53 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
55 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
58 * .sp0 is only used when entering ring 0 from a lower
59 * privilege level. Since the init task never runs anything
60 * but ring 0 code, there is no need for a valid value here.
63 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
66 * .sp1 is cpu_current_top_of_stack. The init task never
67 * runs user code, but cpu_current_top_of_stack should still
68 * be well defined before the first context switch.
70 .sp1 = TOP_OF_INIT_STACK,
76 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
79 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
81 DEFINE_PER_CPU(bool, __tss_limit_invalid);
82 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
85 * this gets called so that we can store lazy state into memory and copy the
86 * current task into the new thread.
88 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
90 memcpy(dst, src, arch_task_struct_size);
92 dst->thread.vm86 = NULL;
95 return fpu__copy(dst, src);
99 * Free thread data structures etc..
101 void exit_thread(struct task_struct *tsk)
103 struct thread_struct *t = &tsk->thread;
104 struct fpu *fpu = &t->fpu;
106 if (test_thread_flag(TIF_IO_BITMAP))
114 static int set_new_tls(struct task_struct *p, unsigned long tls)
116 struct user_desc __user *utls = (struct user_desc __user *)tls;
118 if (in_ia32_syscall())
119 return do_set_thread_area(p, -1, utls, 0);
121 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
124 int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg,
125 struct task_struct *p, unsigned long tls)
127 struct inactive_task_frame *frame;
128 struct fork_frame *fork_frame;
129 struct pt_regs *childregs;
132 childregs = task_pt_regs(p);
133 fork_frame = container_of(childregs, struct fork_frame, regs);
134 frame = &fork_frame->frame;
137 frame->ret_addr = (unsigned long) ret_from_fork;
138 p->thread.sp = (unsigned long) fork_frame;
139 p->thread.io_bitmap = NULL;
140 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
144 p->thread.fsindex = current->thread.fsindex;
145 p->thread.fsbase = current->thread.fsbase;
146 p->thread.gsindex = current->thread.gsindex;
147 p->thread.gsbase = current->thread.gsbase;
149 savesegment(es, p->thread.es);
150 savesegment(ds, p->thread.ds);
152 p->thread.sp0 = (unsigned long) (childregs + 1);
154 * Clear all status flags including IF and set fixed bit. 64bit
155 * does not have this initialization as the frame does not contain
156 * flags. The flags consistency (especially vs. AC) is there
157 * ensured via objtool, which lacks 32bit support.
159 frame->flags = X86_EFLAGS_FIXED;
162 /* Kernel thread ? */
163 if (unlikely(p->flags & PF_KTHREAD)) {
164 memset(childregs, 0, sizeof(struct pt_regs));
165 kthread_frame_init(frame, sp, arg);
170 *childregs = *current_pt_regs();
176 task_user_gs(p) = get_user_gs(current_pt_regs());
179 /* Set a new TLS for the child thread? */
180 if (clone_flags & CLONE_SETTLS)
181 ret = set_new_tls(p, tls);
183 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
189 void flush_thread(void)
191 struct task_struct *tsk = current;
193 flush_ptrace_hw_breakpoint(tsk);
194 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
196 fpu__clear_all(&tsk->thread.fpu);
199 void disable_TSC(void)
202 if (!test_and_set_thread_flag(TIF_NOTSC))
204 * Must flip the CPU state synchronously with
205 * TIF_NOTSC in the current running context.
207 cr4_set_bits(X86_CR4_TSD);
211 static void enable_TSC(void)
214 if (test_and_clear_thread_flag(TIF_NOTSC))
216 * Must flip the CPU state synchronously with
217 * TIF_NOTSC in the current running context.
219 cr4_clear_bits(X86_CR4_TSD);
223 int get_tsc_mode(unsigned long adr)
227 if (test_thread_flag(TIF_NOTSC))
228 val = PR_TSC_SIGSEGV;
232 return put_user(val, (unsigned int __user *)adr);
235 int set_tsc_mode(unsigned int val)
237 if (val == PR_TSC_SIGSEGV)
239 else if (val == PR_TSC_ENABLE)
247 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
249 static void set_cpuid_faulting(bool on)
253 msrval = this_cpu_read(msr_misc_features_shadow);
254 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
255 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
256 this_cpu_write(msr_misc_features_shadow, msrval);
257 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
260 static void disable_cpuid(void)
263 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
265 * Must flip the CPU state synchronously with
266 * TIF_NOCPUID in the current running context.
268 set_cpuid_faulting(true);
273 static void enable_cpuid(void)
276 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
278 * Must flip the CPU state synchronously with
279 * TIF_NOCPUID in the current running context.
281 set_cpuid_faulting(false);
286 static int get_cpuid_mode(void)
288 return !test_thread_flag(TIF_NOCPUID);
291 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
293 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
305 * Called immediately after a successful exec.
307 void arch_setup_new_exec(void)
309 /* If cpuid was previously disabled for this task, re-enable it. */
310 if (test_thread_flag(TIF_NOCPUID))
314 * Don't inherit TIF_SSBD across exec boundary when
315 * PR_SPEC_DISABLE_NOEXEC is used.
317 if (test_thread_flag(TIF_SSBD) &&
318 task_spec_ssb_noexec(current)) {
319 clear_thread_flag(TIF_SSBD);
320 task_clear_spec_ssb_disable(current);
321 task_clear_spec_ssb_noexec(current);
322 speculation_ctrl_update(task_thread_info(current)->flags);
326 #ifdef CONFIG_X86_IOPL_IOPERM
327 static inline void switch_to_bitmap(unsigned long tifp)
330 * Invalidate I/O bitmap if the previous task used it. This prevents
331 * any possible leakage of an active I/O bitmap.
333 * If the next task has an I/O bitmap it will handle it on exit to
336 if (tifp & _TIF_IO_BITMAP)
337 tss_invalidate_io_bitmap();
340 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
343 * Copy at least the byte range of the incoming tasks bitmap which
344 * covers the permitted I/O ports.
346 * If the previous task which used an I/O bitmap had more bits
347 * permitted, then the copy needs to cover those as well so they
350 memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
351 max(tss->io_bitmap.prev_max, iobm->max));
354 * Store the new max and the sequence number of this bitmap
355 * and a pointer to the bitmap itself.
357 tss->io_bitmap.prev_max = iobm->max;
358 tss->io_bitmap.prev_sequence = iobm->sequence;
362 * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
364 void native_tss_update_io_bitmap(void)
366 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
367 struct thread_struct *t = ¤t->thread;
368 u16 *base = &tss->x86_tss.io_bitmap_base;
370 if (!test_thread_flag(TIF_IO_BITMAP)) {
371 native_tss_invalidate_io_bitmap();
375 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
376 *base = IO_BITMAP_OFFSET_VALID_ALL;
378 struct io_bitmap *iobm = t->io_bitmap;
381 * Only copy bitmap data when the sequence number differs. The
382 * update time is accounted to the incoming task.
384 if (tss->io_bitmap.prev_sequence != iobm->sequence)
385 tss_copy_io_bitmap(tss, iobm);
387 /* Enable the bitmap */
388 *base = IO_BITMAP_OFFSET_VALID_MAP;
392 * Make sure that the TSS limit is covering the IO bitmap. It might have
393 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
394 * access from user space to trigger a #GP because tbe bitmap is outside
399 #else /* CONFIG_X86_IOPL_IOPERM */
400 static inline void switch_to_bitmap(unsigned long tifp) { }
406 struct ssb_state *shared_state;
408 unsigned int disable_state;
409 unsigned long local_state;
414 static DEFINE_PER_CPU(struct ssb_state, ssb_state);
416 void speculative_store_bypass_ht_init(void)
418 struct ssb_state *st = this_cpu_ptr(&ssb_state);
419 unsigned int this_cpu = smp_processor_id();
425 * Shared state setup happens once on the first bringup
426 * of the CPU. It's not destroyed on CPU hotunplug.
428 if (st->shared_state)
431 raw_spin_lock_init(&st->lock);
434 * Go over HT siblings and check whether one of them has set up the
435 * shared state pointer already.
437 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
441 if (!per_cpu(ssb_state, cpu).shared_state)
444 /* Link it to the state of the sibling: */
445 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
450 * First HT sibling to come up on the core. Link shared state of
451 * the first HT sibling to itself. The siblings on the same core
452 * which come up later will see the shared state pointer and link
453 * themself to the state of this CPU.
455 st->shared_state = st;
459 * Logic is: First HT sibling enables SSBD for both siblings in the core
460 * and last sibling to disable it, disables it for the whole core. This how
461 * MSR_SPEC_CTRL works in "hardware":
463 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
465 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
467 struct ssb_state *st = this_cpu_ptr(&ssb_state);
468 u64 msr = x86_amd_ls_cfg_base;
470 if (!static_cpu_has(X86_FEATURE_ZEN)) {
471 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
472 wrmsrl(MSR_AMD64_LS_CFG, msr);
476 if (tifn & _TIF_SSBD) {
478 * Since this can race with prctl(), block reentry on the
481 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
484 msr |= x86_amd_ls_cfg_ssbd_mask;
486 raw_spin_lock(&st->shared_state->lock);
487 /* First sibling enables SSBD: */
488 if (!st->shared_state->disable_state)
489 wrmsrl(MSR_AMD64_LS_CFG, msr);
490 st->shared_state->disable_state++;
491 raw_spin_unlock(&st->shared_state->lock);
493 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
496 raw_spin_lock(&st->shared_state->lock);
497 st->shared_state->disable_state--;
498 if (!st->shared_state->disable_state)
499 wrmsrl(MSR_AMD64_LS_CFG, msr);
500 raw_spin_unlock(&st->shared_state->lock);
504 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
506 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
508 wrmsrl(MSR_AMD64_LS_CFG, msr);
512 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
515 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
516 * so ssbd_tif_to_spec_ctrl() just works.
518 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
522 * Update the MSRs managing speculation control, during context switch.
524 * tifp: Previous task's thread flags
525 * tifn: Next task's thread flags
527 static __always_inline void __speculation_ctrl_update(unsigned long tifp,
530 unsigned long tif_diff = tifp ^ tifn;
531 u64 msr = x86_spec_ctrl_base;
534 lockdep_assert_irqs_disabled();
536 /* Handle change of TIF_SSBD depending on the mitigation method. */
537 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
538 if (tif_diff & _TIF_SSBD)
539 amd_set_ssb_virt_state(tifn);
540 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
541 if (tif_diff & _TIF_SSBD)
542 amd_set_core_ssb_state(tifn);
543 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
544 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
545 updmsr |= !!(tif_diff & _TIF_SSBD);
546 msr |= ssbd_tif_to_spec_ctrl(tifn);
549 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
550 if (IS_ENABLED(CONFIG_SMP) &&
551 static_branch_unlikely(&switch_to_cond_stibp)) {
552 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
553 msr |= stibp_tif_to_spec_ctrl(tifn);
557 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
560 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
562 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
563 if (task_spec_ssb_disable(tsk))
564 set_tsk_thread_flag(tsk, TIF_SSBD);
566 clear_tsk_thread_flag(tsk, TIF_SSBD);
568 if (task_spec_ib_disable(tsk))
569 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
571 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
573 /* Return the updated threadinfo flags*/
574 return task_thread_info(tsk)->flags;
577 void speculation_ctrl_update(unsigned long tif)
581 /* Forced update. Make sure all relevant TIF flags are different */
582 local_irq_save(flags);
583 __speculation_ctrl_update(~tif, tif);
584 local_irq_restore(flags);
587 /* Called from seccomp/prctl update */
588 void speculation_ctrl_update_current(void)
591 speculation_ctrl_update(speculation_ctrl_update_tif(current));
595 static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
597 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
601 this_cpu_write(cpu_tlbstate.cr4, newval);
606 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
608 unsigned long tifp, tifn;
610 tifn = READ_ONCE(task_thread_info(next_p)->flags);
611 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
613 switch_to_bitmap(tifp);
615 propagate_user_return_notify(prev_p, next_p);
617 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
618 arch_has_block_step()) {
619 unsigned long debugctl, msk;
621 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
622 debugctl &= ~DEBUGCTLMSR_BTF;
623 msk = tifn & _TIF_BLOCKSTEP;
624 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
625 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
628 if ((tifp ^ tifn) & _TIF_NOTSC)
629 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
631 if ((tifp ^ tifn) & _TIF_NOCPUID)
632 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
634 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
635 __speculation_ctrl_update(tifp, tifn);
637 speculation_ctrl_update_tif(prev_p);
638 tifn = speculation_ctrl_update_tif(next_p);
640 /* Enforce MSR update to ensure consistent state */
641 __speculation_ctrl_update(~tifn, tifn);
644 if ((tifp ^ tifn) & _TIF_SLD)
649 * Idle related variables and functions
651 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
652 EXPORT_SYMBOL(boot_option_idle_override);
654 static void (*x86_idle)(void);
657 static inline void play_dead(void)
663 void arch_cpu_idle_enter(void)
665 tsc_verify_tsc_adjust(false);
669 void arch_cpu_idle_dead(void)
675 * Called from the generic idle code.
677 void arch_cpu_idle(void)
683 * We use this if we don't have any better idle routine..
685 void __cpuidle default_idle(void)
689 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
690 EXPORT_SYMBOL(default_idle);
694 bool xen_set_default_idle(void)
696 bool ret = !!x86_idle;
698 x86_idle = default_idle;
704 void stop_this_cpu(void *dummy)
710 set_cpu_online(smp_processor_id(), false);
711 disable_local_APIC();
712 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
715 * Use wbinvd on processors that support SME. This provides support
716 * for performing a successful kexec when going from SME inactive
717 * to SME active (or vice-versa). The cache must be cleared so that
718 * if there are entries with the same physical address, both with and
719 * without the encryption bit, they don't race each other when flushed
720 * and potentially end up with the wrong entry being committed to
723 if (boot_cpu_has(X86_FEATURE_SME))
727 * Use native_halt() so that memory contents don't change
728 * (stack usage and variables) after possibly issuing the
729 * native_wbinvd() above.
736 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
737 * states (local apic timer and TSC stop).
739 static void amd_e400_idle(void)
742 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
743 * gets set after static_cpu_has() places have been converted via
746 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
751 tick_broadcast_enter();
756 * The switch back from broadcast mode needs to be called with
757 * interrupts disabled.
760 tick_broadcast_exit();
765 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
766 * We can't rely on cpuidle installing MWAIT, because it will not load
767 * on systems that support only C1 -- so the boot default must be MWAIT.
769 * Some AMD machines are the opposite, they depend on using HALT.
771 * So for default C1, which is used during boot until cpuidle loads,
772 * use MWAIT-C1 on Intel HW that has it, else use HALT.
774 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
776 if (c->x86_vendor != X86_VENDOR_INTEL)
779 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
786 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
787 * with interrupts enabled and no flags, which is backwards compatible with the
788 * original MWAIT implementation.
790 static __cpuidle void mwait_idle(void)
792 if (!current_set_polling_and_test()) {
793 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
795 clflush((void *)¤t_thread_info()->flags);
799 __monitor((void *)¤t_thread_info()->flags, 0, 0);
807 __current_clr_polling();
810 void select_idle_routine(const struct cpuinfo_x86 *c)
813 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
814 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
816 if (x86_idle || boot_option_idle_override == IDLE_POLL)
819 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
820 pr_info("using AMD E400 aware idle routine\n");
821 x86_idle = amd_e400_idle;
822 } else if (prefer_mwait_c1_over_halt(c)) {
823 pr_info("using mwait in idle threads\n");
824 x86_idle = mwait_idle;
826 x86_idle = default_idle;
829 void amd_e400_c1e_apic_setup(void)
831 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
832 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
834 tick_broadcast_force();
839 void __init arch_post_acpi_subsys_init(void)
843 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
847 * AMD E400 detection needs to happen after ACPI has been enabled. If
848 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
849 * MSR_K8_INT_PENDING_MSG.
851 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
852 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
855 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
857 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
858 mark_tsc_unstable("TSC halt in AMD C1E");
859 pr_info("System has AMD C1E enabled\n");
862 static int __init idle_setup(char *str)
867 if (!strcmp(str, "poll")) {
868 pr_info("using polling idle threads\n");
869 boot_option_idle_override = IDLE_POLL;
870 cpu_idle_poll_ctrl(true);
871 } else if (!strcmp(str, "halt")) {
873 * When the boot option of idle=halt is added, halt is
874 * forced to be used for CPU idle. In such case CPU C2/C3
875 * won't be used again.
876 * To continue to load the CPU idle driver, don't touch
877 * the boot_option_idle_override.
879 x86_idle = default_idle;
880 boot_option_idle_override = IDLE_HALT;
881 } else if (!strcmp(str, "nomwait")) {
883 * If the boot option of "idle=nomwait" is added,
884 * it means that mwait will be disabled for CPU C2/C3
885 * states. In such case it won't touch the variable
886 * of boot_option_idle_override.
888 boot_option_idle_override = IDLE_NOMWAIT;
894 early_param("idle", idle_setup);
896 unsigned long arch_align_stack(unsigned long sp)
898 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
899 sp -= get_random_int() % 8192;
903 unsigned long arch_randomize_brk(struct mm_struct *mm)
905 return randomize_page(mm->brk, 0x02000000);
909 * Called from fs/proc with a reference on @p to find the function
910 * which called into schedule(). This needs to be done carefully
911 * because the task might wake up and we might look at a stack
914 unsigned long get_wchan(struct task_struct *p)
916 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
919 if (p == current || p->state == TASK_RUNNING)
922 if (!try_get_task_stack(p))
925 start = (unsigned long)task_stack_page(p);
930 * Layout of the stack page:
932 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
934 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
936 * ----------- bottom = start
938 * The tasks stack pointer points at the location where the
939 * framepointer is stored. The data on the stack is:
940 * ... IP FP ... IP FP
942 * We need to read FP and IP, so we need to adjust the upper
943 * bound by another unsigned long.
945 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
946 top -= 2 * sizeof(unsigned long);
949 sp = READ_ONCE(p->thread.sp);
950 if (sp < bottom || sp > top)
953 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
955 if (fp < bottom || fp > top)
957 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
958 if (!in_sched_functions(ip)) {
962 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
963 } while (count++ < 16 && p->state != TASK_RUNNING);
970 long do_arch_prctl_common(struct task_struct *task, int option,
971 unsigned long cpuid_enabled)
975 return get_cpuid_mode();
977 return set_cpuid_mode(task, cpuid_enabled);