1 // SPDX-License-Identifier: GPL-2.0-only
3 * Interrupt descriptor table related code
5 #include <linux/interrupt.h>
7 #include <asm/cpu_entry_area.h>
8 #include <asm/set_memory.h>
10 #include <asm/proto.h>
12 #include <asm/hw_irq.h>
24 #define DEFAULT_STACK 0
26 #define G(_vector, _addr, _ist, _type, _dpl, _segment) \
34 .segment = _segment, \
38 #define INTG(_vector, _addr) \
39 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)
41 /* System interrupt gate */
42 #define SYSG(_vector, _addr) \
43 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)
46 * Interrupt gate with interrupt stack. The _ist index is the index in
47 * the tss.ist[] array, but for the descriptor it needs to start at 1.
49 #define ISTG(_vector, _addr, _ist) \
50 G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS)
53 #define TSKG(_vector, _gdt) \
54 G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
56 #define IDT_TABLE_SIZE (IDT_ENTRIES * sizeof(gate_desc))
58 static bool idt_setup_done __initdata;
61 * Early traps running on the DEFAULT_STACK because the other interrupt
62 * stacks work only after cpu_init().
64 static const __initconst struct idt_data early_idts[] = {
65 INTG(X86_TRAP_DB, asm_exc_debug),
66 SYSG(X86_TRAP_BP, asm_exc_int3),
70 * Not possible on 64-bit. See idt_setup_early_pf() for details.
72 INTG(X86_TRAP_PF, asm_exc_page_fault),
77 * The default IDT entries which are set up in trap_init() before
78 * cpu_init() is invoked. Interrupt stacks cannot be used at that point and
79 * the traps which use them are reinitialized with IST after cpu_init() has
82 static const __initconst struct idt_data def_idts[] = {
83 INTG(X86_TRAP_DE, asm_exc_divide_error),
84 INTG(X86_TRAP_NMI, asm_exc_nmi),
85 INTG(X86_TRAP_BR, asm_exc_bounds),
86 INTG(X86_TRAP_UD, asm_exc_invalid_op),
87 INTG(X86_TRAP_NM, asm_exc_device_not_available),
88 INTG(X86_TRAP_OLD_MF, asm_exc_coproc_segment_overrun),
89 INTG(X86_TRAP_TS, asm_exc_invalid_tss),
90 INTG(X86_TRAP_NP, asm_exc_segment_not_present),
91 INTG(X86_TRAP_SS, asm_exc_stack_segment),
92 INTG(X86_TRAP_GP, asm_exc_general_protection),
93 INTG(X86_TRAP_SPURIOUS, asm_exc_spurious_interrupt_bug),
94 INTG(X86_TRAP_MF, asm_exc_coprocessor_error),
95 INTG(X86_TRAP_AC, asm_exc_alignment_check),
96 INTG(X86_TRAP_XF, asm_exc_simd_coprocessor_error),
99 TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS),
101 INTG(X86_TRAP_DF, asm_exc_double_fault),
103 INTG(X86_TRAP_DB, asm_exc_debug),
105 #ifdef CONFIG_X86_MCE
106 INTG(X86_TRAP_MC, asm_exc_machine_check),
109 SYSG(X86_TRAP_OF, asm_exc_overflow),
110 #if defined(CONFIG_IA32_EMULATION)
111 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_compat),
112 #elif defined(CONFIG_X86_32)
113 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32),
118 * The APIC and SMP idt entries
120 static const __initconst struct idt_data apic_idts[] = {
122 INTG(RESCHEDULE_VECTOR, asm_sysvec_reschedule_ipi),
123 INTG(CALL_FUNCTION_VECTOR, asm_sysvec_call_function),
124 INTG(CALL_FUNCTION_SINGLE_VECTOR, asm_sysvec_call_function_single),
125 INTG(IRQ_MOVE_CLEANUP_VECTOR, asm_sysvec_irq_move_cleanup),
126 INTG(REBOOT_VECTOR, asm_sysvec_reboot),
129 #ifdef CONFIG_X86_THERMAL_VECTOR
130 INTG(THERMAL_APIC_VECTOR, asm_sysvec_thermal),
133 #ifdef CONFIG_X86_MCE_THRESHOLD
134 INTG(THRESHOLD_APIC_VECTOR, asm_sysvec_threshold),
137 #ifdef CONFIG_X86_MCE_AMD
138 INTG(DEFERRED_ERROR_VECTOR, asm_sysvec_deferred_error),
141 #ifdef CONFIG_X86_LOCAL_APIC
142 INTG(LOCAL_TIMER_VECTOR, asm_sysvec_apic_timer_interrupt),
143 INTG(X86_PLATFORM_IPI_VECTOR, asm_sysvec_x86_platform_ipi),
144 # ifdef CONFIG_HAVE_KVM
145 INTG(POSTED_INTR_VECTOR, asm_sysvec_kvm_posted_intr_ipi),
146 INTG(POSTED_INTR_WAKEUP_VECTOR, asm_sysvec_kvm_posted_intr_wakeup_ipi),
147 INTG(POSTED_INTR_NESTED_VECTOR, asm_sysvec_kvm_posted_intr_nested_ipi),
149 # ifdef CONFIG_IRQ_WORK
150 INTG(IRQ_WORK_VECTOR, asm_sysvec_irq_work),
152 # ifdef CONFIG_X86_UV
153 INTG(UV_BAU_MESSAGE, asm_sysvec_uv_bau_message),
155 INTG(SPURIOUS_APIC_VECTOR, asm_sysvec_spurious_apic_interrupt),
156 INTG(ERROR_APIC_VECTOR, asm_sysvec_error_interrupt),
160 /* Must be page-aligned because the real IDT is used in the cpu entry area */
161 static gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss;
163 static struct desc_ptr idt_descr __ro_after_init = {
164 .size = IDT_TABLE_SIZE - 1,
165 .address = (unsigned long) idt_table,
168 void load_current_idt(void)
170 lockdep_assert_irqs_disabled();
171 load_idt(&idt_descr);
174 #ifdef CONFIG_X86_F00F_BUG
175 bool idt_is_f00f_address(unsigned long address)
177 return ((address - idt_descr.address) >> 3) == 6;
181 static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d)
183 unsigned long addr = (unsigned long) d->addr;
185 gate->offset_low = (u16) addr;
186 gate->segment = (u16) d->segment;
187 gate->bits = d->bits;
188 gate->offset_middle = (u16) (addr >> 16);
190 gate->offset_high = (u32) (addr >> 32);
196 idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys)
200 for (; size > 0; t++, size--) {
201 idt_init_desc(&desc, t);
202 write_idt_entry(idt, t->vector, &desc);
204 set_bit(t->vector, system_vectors);
208 static __init void set_intr_gate(unsigned int n, const void *addr)
210 struct idt_data data;
214 memset(&data, 0, sizeof(data));
217 data.segment = __KERNEL_CS;
218 data.bits.type = GATE_INTERRUPT;
221 idt_setup_from_table(idt_table, &data, 1, false);
225 * idt_setup_early_traps - Initialize the idt table with early traps
227 * On X8664 these traps do not use interrupt stacks as they can't work
228 * before cpu_init() is invoked and sets up TSS. The IST variants are
229 * installed after that.
231 void __init idt_setup_early_traps(void)
233 idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts),
235 load_idt(&idt_descr);
239 * idt_setup_traps - Initialize the idt table with default traps
241 void __init idt_setup_traps(void)
243 idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true);
248 * Early traps running on the DEFAULT_STACK because the other interrupt
249 * stacks work only after cpu_init().
251 static const __initconst struct idt_data early_pf_idts[] = {
252 INTG(X86_TRAP_PF, asm_exc_page_fault),
256 * The exceptions which use Interrupt stacks. They are setup after
257 * cpu_init() when the TSS has been initialized.
259 static const __initconst struct idt_data ist_idts[] = {
260 ISTG(X86_TRAP_DB, asm_exc_debug, IST_INDEX_DB),
261 ISTG(X86_TRAP_NMI, asm_exc_nmi, IST_INDEX_NMI),
262 ISTG(X86_TRAP_DF, asm_exc_double_fault, IST_INDEX_DF),
263 #ifdef CONFIG_X86_MCE
264 ISTG(X86_TRAP_MC, asm_exc_machine_check, IST_INDEX_MCE),
269 * idt_setup_early_pf - Initialize the idt table with early pagefault handler
271 * On X8664 this does not use interrupt stacks as they can't work before
272 * cpu_init() is invoked and sets up TSS. The IST variant is installed
275 * Note, that X86_64 cannot install the real #PF handler in
276 * idt_setup_early_traps() because the memory intialization needs the #PF
277 * handler from the early_idt_handler_array to initialize the early page
280 void __init idt_setup_early_pf(void)
282 idt_setup_from_table(idt_table, early_pf_idts,
283 ARRAY_SIZE(early_pf_idts), true);
287 * idt_setup_ist_traps - Initialize the idt table with traps using IST
289 void __init idt_setup_ist_traps(void)
291 idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts), true);
295 static void __init idt_map_in_cea(void)
298 * Set the IDT descriptor to a fixed read-only location in the cpu
299 * entry area, so that the "sidt" instruction will not leak the
300 * location of the kernel, and to defend the IDT against arbitrary
301 * memory write vulnerabilities.
303 cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table),
305 idt_descr.address = CPU_ENTRY_AREA_RO_IDT;
309 * idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates
311 void __init idt_setup_apic_and_irq_gates(void)
313 int i = FIRST_EXTERNAL_VECTOR;
316 idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true);
318 for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) {
319 entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR);
320 set_intr_gate(i, entry);
323 #ifdef CONFIG_X86_LOCAL_APIC
324 for_each_clear_bit_from(i, system_vectors, NR_VECTORS) {
326 * Don't set the non assigned system vectors in the
327 * system_vectors bitmap. Otherwise they show up in
330 entry = spurious_entries_start + 8 * (i - FIRST_SYSTEM_VECTOR);
331 set_intr_gate(i, entry);
334 /* Map IDT into CPU entry area and reload it. */
336 load_idt(&idt_descr);
338 /* Make the IDT table read only */
339 set_memory_ro((unsigned long)&idt_table, 1);
341 idt_setup_done = true;
345 * idt_setup_early_handler - Initializes the idt table with early handlers
347 void __init idt_setup_early_handler(void)
351 for (i = 0; i < NUM_EXCEPTION_VECTORS; i++)
352 set_intr_gate(i, early_idt_handler_array[i]);
354 for ( ; i < NR_VECTORS; i++)
355 set_intr_gate(i, early_ignore_irq);
357 load_idt(&idt_descr);
361 * idt_invalidate - Invalidate interrupt descriptor table
362 * @addr: The virtual address of the 'invalid' IDT
364 void idt_invalidate(void *addr)
366 struct desc_ptr idt = { .address = (unsigned long) addr, .size = 0 };
371 void __init alloc_intr_gate(unsigned int n, const void *addr)
373 if (WARN_ON(n < FIRST_SYSTEM_VECTOR))
376 if (WARN_ON(idt_setup_done))
379 if (!WARN_ON(test_and_set_bit(n, system_vectors)))
380 set_intr_gate(n, addr);