1 // SPDX-License-Identifier: GPL-2.0-only
3 * Interrupt descriptor table related code
5 #include <linux/interrupt.h>
7 #include <asm/cpu_entry_area.h>
8 #include <asm/set_memory.h>
10 #include <asm/proto.h>
12 #include <asm/hw_irq.h>
17 #define DEFAULT_STACK 0
19 #define G(_vector, _addr, _ist, _type, _dpl, _segment) \
27 .segment = _segment, \
31 #define INTG(_vector, _addr) \
32 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)
34 /* System interrupt gate */
35 #define SYSG(_vector, _addr) \
36 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)
39 * Interrupt gate with interrupt stack. The _ist index is the index in
40 * the tss.ist[] array, but for the descriptor it needs to start at 1.
42 #define ISTG(_vector, _addr, _ist) \
43 G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS)
46 #define TSKG(_vector, _gdt) \
47 G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
49 #define IDT_TABLE_SIZE (IDT_ENTRIES * sizeof(gate_desc))
51 static bool idt_setup_done __initdata;
54 * Early traps running on the DEFAULT_STACK because the other interrupt
55 * stacks work only after cpu_init().
57 static const __initconst struct idt_data early_idts[] = {
58 INTG(X86_TRAP_DB, asm_exc_debug),
59 SYSG(X86_TRAP_BP, asm_exc_int3),
63 * Not possible on 64-bit. See idt_setup_early_pf() for details.
65 INTG(X86_TRAP_PF, asm_exc_page_fault),
70 * The default IDT entries which are set up in trap_init() before
71 * cpu_init() is invoked. Interrupt stacks cannot be used at that point and
72 * the traps which use them are reinitialized with IST after cpu_init() has
75 static const __initconst struct idt_data def_idts[] = {
76 INTG(X86_TRAP_DE, asm_exc_divide_error),
77 INTG(X86_TRAP_NMI, asm_exc_nmi),
78 INTG(X86_TRAP_BR, asm_exc_bounds),
79 INTG(X86_TRAP_UD, asm_exc_invalid_op),
80 INTG(X86_TRAP_NM, asm_exc_device_not_available),
81 INTG(X86_TRAP_OLD_MF, asm_exc_coproc_segment_overrun),
82 INTG(X86_TRAP_TS, asm_exc_invalid_tss),
83 INTG(X86_TRAP_NP, asm_exc_segment_not_present),
84 INTG(X86_TRAP_SS, asm_exc_stack_segment),
85 INTG(X86_TRAP_GP, asm_exc_general_protection),
86 INTG(X86_TRAP_SPURIOUS, asm_exc_spurious_interrupt_bug),
87 INTG(X86_TRAP_MF, asm_exc_coprocessor_error),
88 INTG(X86_TRAP_AC, asm_exc_alignment_check),
89 INTG(X86_TRAP_XF, asm_exc_simd_coprocessor_error),
92 TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS),
94 INTG(X86_TRAP_DF, asm_exc_double_fault),
96 INTG(X86_TRAP_DB, asm_exc_debug),
99 INTG(X86_TRAP_MC, asm_exc_machine_check),
102 SYSG(X86_TRAP_OF, asm_exc_overflow),
103 #if defined(CONFIG_IA32_EMULATION)
104 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_compat),
105 #elif defined(CONFIG_X86_32)
106 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32),
111 * The APIC and SMP idt entries
113 static const __initconst struct idt_data apic_idts[] = {
115 INTG(RESCHEDULE_VECTOR, asm_sysvec_reschedule_ipi),
116 INTG(CALL_FUNCTION_VECTOR, asm_sysvec_call_function),
117 INTG(CALL_FUNCTION_SINGLE_VECTOR, asm_sysvec_call_function_single),
118 INTG(IRQ_MOVE_CLEANUP_VECTOR, asm_sysvec_irq_move_cleanup),
119 INTG(REBOOT_VECTOR, asm_sysvec_reboot),
122 #ifdef CONFIG_X86_THERMAL_VECTOR
123 INTG(THERMAL_APIC_VECTOR, asm_sysvec_thermal),
126 #ifdef CONFIG_X86_MCE_THRESHOLD
127 INTG(THRESHOLD_APIC_VECTOR, asm_sysvec_threshold),
130 #ifdef CONFIG_X86_MCE_AMD
131 INTG(DEFERRED_ERROR_VECTOR, asm_sysvec_deferred_error),
134 #ifdef CONFIG_X86_LOCAL_APIC
135 INTG(LOCAL_TIMER_VECTOR, asm_sysvec_apic_timer_interrupt),
136 INTG(X86_PLATFORM_IPI_VECTOR, asm_sysvec_x86_platform_ipi),
137 # ifdef CONFIG_HAVE_KVM
138 INTG(POSTED_INTR_VECTOR, asm_sysvec_kvm_posted_intr_ipi),
139 INTG(POSTED_INTR_WAKEUP_VECTOR, asm_sysvec_kvm_posted_intr_wakeup_ipi),
140 INTG(POSTED_INTR_NESTED_VECTOR, asm_sysvec_kvm_posted_intr_nested_ipi),
142 # ifdef CONFIG_IRQ_WORK
143 INTG(IRQ_WORK_VECTOR, asm_sysvec_irq_work),
145 # ifdef CONFIG_X86_UV
146 INTG(UV_BAU_MESSAGE, asm_sysvec_uv_bau_message),
148 INTG(SPURIOUS_APIC_VECTOR, asm_sysvec_spurious_apic_interrupt),
149 INTG(ERROR_APIC_VECTOR, asm_sysvec_error_interrupt),
153 /* Must be page-aligned because the real IDT is used in the cpu entry area */
154 static gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss;
156 static struct desc_ptr idt_descr __ro_after_init = {
157 .size = IDT_TABLE_SIZE - 1,
158 .address = (unsigned long) idt_table,
161 void load_current_idt(void)
163 lockdep_assert_irqs_disabled();
164 load_idt(&idt_descr);
167 #ifdef CONFIG_X86_F00F_BUG
168 bool idt_is_f00f_address(unsigned long address)
170 return ((address - idt_descr.address) >> 3) == 6;
175 idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys)
179 for (; size > 0; t++, size--) {
180 idt_init_desc(&desc, t);
181 write_idt_entry(idt, t->vector, &desc);
183 set_bit(t->vector, system_vectors);
187 static __init void set_intr_gate(unsigned int n, const void *addr)
189 struct idt_data data;
191 init_idt_data(&data, n, addr);
193 idt_setup_from_table(idt_table, &data, 1, false);
197 * idt_setup_early_traps - Initialize the idt table with early traps
199 * On X8664 these traps do not use interrupt stacks as they can't work
200 * before cpu_init() is invoked and sets up TSS. The IST variants are
201 * installed after that.
203 void __init idt_setup_early_traps(void)
205 idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts),
207 load_idt(&idt_descr);
211 * idt_setup_traps - Initialize the idt table with default traps
213 void __init idt_setup_traps(void)
215 idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true);
220 * Early traps running on the DEFAULT_STACK because the other interrupt
221 * stacks work only after cpu_init().
223 static const __initconst struct idt_data early_pf_idts[] = {
224 INTG(X86_TRAP_PF, asm_exc_page_fault),
228 * The exceptions which use Interrupt stacks. They are setup after
229 * cpu_init() when the TSS has been initialized.
231 static const __initconst struct idt_data ist_idts[] = {
232 ISTG(X86_TRAP_DB, asm_exc_debug, IST_INDEX_DB),
233 ISTG(X86_TRAP_NMI, asm_exc_nmi, IST_INDEX_NMI),
234 ISTG(X86_TRAP_DF, asm_exc_double_fault, IST_INDEX_DF),
235 #ifdef CONFIG_X86_MCE
236 ISTG(X86_TRAP_MC, asm_exc_machine_check, IST_INDEX_MCE),
238 #ifdef CONFIG_AMD_MEM_ENCRYPT
239 ISTG(X86_TRAP_VC, asm_exc_vmm_communication, IST_INDEX_VC),
244 * idt_setup_early_pf - Initialize the idt table with early pagefault handler
246 * On X8664 this does not use interrupt stacks as they can't work before
247 * cpu_init() is invoked and sets up TSS. The IST variant is installed
250 * Note, that X86_64 cannot install the real #PF handler in
251 * idt_setup_early_traps() because the memory intialization needs the #PF
252 * handler from the early_idt_handler_array to initialize the early page
255 void __init idt_setup_early_pf(void)
257 idt_setup_from_table(idt_table, early_pf_idts,
258 ARRAY_SIZE(early_pf_idts), true);
262 * idt_setup_ist_traps - Initialize the idt table with traps using IST
264 void __init idt_setup_ist_traps(void)
266 idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts), true);
270 static void __init idt_map_in_cea(void)
273 * Set the IDT descriptor to a fixed read-only location in the cpu
274 * entry area, so that the "sidt" instruction will not leak the
275 * location of the kernel, and to defend the IDT against arbitrary
276 * memory write vulnerabilities.
278 cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table),
280 idt_descr.address = CPU_ENTRY_AREA_RO_IDT;
284 * idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates
286 void __init idt_setup_apic_and_irq_gates(void)
288 int i = FIRST_EXTERNAL_VECTOR;
291 idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true);
293 for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) {
294 entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR);
295 set_intr_gate(i, entry);
298 #ifdef CONFIG_X86_LOCAL_APIC
299 for_each_clear_bit_from(i, system_vectors, NR_VECTORS) {
301 * Don't set the non assigned system vectors in the
302 * system_vectors bitmap. Otherwise they show up in
305 entry = spurious_entries_start + 8 * (i - FIRST_SYSTEM_VECTOR);
306 set_intr_gate(i, entry);
309 /* Map IDT into CPU entry area and reload it. */
311 load_idt(&idt_descr);
313 /* Make the IDT table read only */
314 set_memory_ro((unsigned long)&idt_table, 1);
316 idt_setup_done = true;
320 * idt_setup_early_handler - Initializes the idt table with early handlers
322 void __init idt_setup_early_handler(void)
326 for (i = 0; i < NUM_EXCEPTION_VECTORS; i++)
327 set_intr_gate(i, early_idt_handler_array[i]);
329 for ( ; i < NR_VECTORS; i++)
330 set_intr_gate(i, early_ignore_irq);
332 load_idt(&idt_descr);
336 * idt_invalidate - Invalidate interrupt descriptor table
337 * @addr: The virtual address of the 'invalid' IDT
339 void idt_invalidate(void *addr)
341 struct desc_ptr idt = { .address = (unsigned long) addr, .size = 0 };
346 void __init alloc_intr_gate(unsigned int n, const void *addr)
348 if (WARN_ON(n < FIRST_SYSTEM_VECTOR))
351 if (WARN_ON(idt_setup_done))
354 if (!WARN_ON(test_and_set_bit(n, system_vectors)))
355 set_intr_gate(n, addr);