1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2007 Alan Stern
5 * Copyright (C) 2009 IBM Corporation
6 * Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
8 * Authors: Alan Stern <stern@rowland.harvard.edu>
9 * K.Prasad <prasad@linux.vnet.ibm.com>
10 * Frederic Weisbecker <fweisbec@gmail.com>
14 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
15 * using the CPU's debug registers.
18 #include <linux/perf_event.h>
19 #include <linux/hw_breakpoint.h>
20 #include <linux/irqflags.h>
21 #include <linux/notifier.h>
22 #include <linux/kallsyms.h>
23 #include <linux/kprobes.h>
24 #include <linux/percpu.h>
25 #include <linux/kdebug.h>
26 #include <linux/kernel.h>
27 #include <linux/export.h>
28 #include <linux/sched.h>
29 #include <linux/smp.h>
31 #include <asm/hw_breakpoint.h>
32 #include <asm/processor.h>
33 #include <asm/debugreg.h>
37 /* Per cpu debug control register value */
38 DEFINE_PER_CPU(unsigned long, cpu_dr7);
39 EXPORT_PER_CPU_SYMBOL(cpu_dr7);
41 /* Per cpu debug address registers values */
42 static DEFINE_PER_CPU(unsigned long, cpu_debugreg[HBP_NUM]);
45 * Stores the breakpoints currently in use on each breakpoint address
46 * register for each cpus
48 static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);
51 static inline unsigned long
52 __encode_dr7(int drnum, unsigned int len, unsigned int type)
54 unsigned long bp_info;
56 bp_info = (len | type) & 0xf;
57 bp_info <<= (DR_CONTROL_SHIFT + drnum * DR_CONTROL_SIZE);
58 bp_info |= (DR_GLOBAL_ENABLE << (drnum * DR_ENABLE_SIZE));
64 * Encode the length, type, Exact, and Enable bits for a particular breakpoint
65 * as stored in debug register 7.
67 unsigned long encode_dr7(int drnum, unsigned int len, unsigned int type)
69 return __encode_dr7(drnum, len, type) | DR_GLOBAL_SLOWDOWN;
73 * Decode the length and type bits for a particular breakpoint as
74 * stored in debug register 7. Return the "enabled" status.
76 int decode_dr7(unsigned long dr7, int bpnum, unsigned *len, unsigned *type)
78 int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE);
80 *len = (bp_info & 0xc) | 0x40;
81 *type = (bp_info & 0x3) | 0x80;
83 return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3;
87 * Install a perf counter breakpoint.
89 * We seek a free debug address register and use it for this
90 * breakpoint. Eventually we enable it in the debug control register.
92 * Atomic: we hold the counter->ctx->lock and we only handle variables
93 * and registers local to this cpu.
95 int arch_install_hw_breakpoint(struct perf_event *bp)
97 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
101 for (i = 0; i < HBP_NUM; i++) {
102 struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
110 if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
113 set_debugreg(info->address, i);
114 __this_cpu_write(cpu_debugreg[i], info->address);
116 dr7 = this_cpu_ptr(&cpu_dr7);
117 *dr7 |= encode_dr7(i, info->len, info->type);
119 set_debugreg(*dr7, 7);
121 set_dr_addr_mask(info->mask, i);
127 * Uninstall the breakpoint contained in the given counter.
129 * First we search the debug address register it uses and then we disable
132 * Atomic: we hold the counter->ctx->lock and we only handle variables
133 * and registers local to this cpu.
135 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
137 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
141 for (i = 0; i < HBP_NUM; i++) {
142 struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
150 if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
153 dr7 = this_cpu_ptr(&cpu_dr7);
154 *dr7 &= ~__encode_dr7(i, info->len, info->type);
156 set_debugreg(*dr7, 7);
158 set_dr_addr_mask(0, i);
161 static int arch_bp_generic_len(int x86_len)
164 case X86_BREAKPOINT_LEN_1:
165 return HW_BREAKPOINT_LEN_1;
166 case X86_BREAKPOINT_LEN_2:
167 return HW_BREAKPOINT_LEN_2;
168 case X86_BREAKPOINT_LEN_4:
169 return HW_BREAKPOINT_LEN_4;
171 case X86_BREAKPOINT_LEN_8:
172 return HW_BREAKPOINT_LEN_8;
179 int arch_bp_generic_fields(int x86_len, int x86_type,
180 int *gen_len, int *gen_type)
186 case X86_BREAKPOINT_EXECUTE:
187 if (x86_len != X86_BREAKPOINT_LEN_X)
190 *gen_type = HW_BREAKPOINT_X;
191 *gen_len = sizeof(long);
193 case X86_BREAKPOINT_WRITE:
194 *gen_type = HW_BREAKPOINT_W;
196 case X86_BREAKPOINT_RW:
197 *gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
204 len = arch_bp_generic_len(x86_len);
213 * Check for virtual address in kernel space.
215 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
221 len = arch_bp_generic_len(hw->len);
222 WARN_ON_ONCE(len < 0);
225 * We don't need to worry about va + len - 1 overflowing:
226 * we already require that va is aligned to a multiple of len.
228 return (va >= TASK_SIZE_MAX) || ((va + len - 1) >= TASK_SIZE_MAX);
232 * Checks whether the range [addr, end], overlaps the area [base, base + size).
234 static inline bool within_area(unsigned long addr, unsigned long end,
235 unsigned long base, unsigned long size)
237 return end >= base && addr < (base + size);
241 * Checks whether the range from addr to end, inclusive, overlaps the fixed
242 * mapped CPU entry area range or other ranges used for CPU entry.
244 static inline bool within_cpu_entry(unsigned long addr, unsigned long end)
248 /* CPU entry erea is always used for CPU entry */
249 if (within_area(addr, end, CPU_ENTRY_AREA_BASE,
250 CPU_ENTRY_AREA_TOTAL_SIZE))
253 for_each_possible_cpu(cpu) {
254 /* The original rw GDT is being used after load_direct_gdt() */
255 if (within_area(addr, end, (unsigned long)get_cpu_gdt_rw(cpu),
260 * cpu_tss_rw is not directly referenced by hardware, but
261 * cpu_tss_rw is also used in CPU entry code,
263 if (within_area(addr, end,
264 (unsigned long)&per_cpu(cpu_tss_rw, cpu),
265 sizeof(struct tss_struct)))
272 static int arch_build_bp_info(struct perf_event *bp,
273 const struct perf_event_attr *attr,
274 struct arch_hw_breakpoint *hw)
276 unsigned long bp_end;
278 bp_end = attr->bp_addr + attr->bp_len - 1;
279 if (bp_end < attr->bp_addr)
283 * Prevent any breakpoint of any type that overlaps the CPU
284 * entry area and data. This protects the IST stacks and also
285 * reduces the chance that we ever find out what happens if
286 * there's a data breakpoint on the GDT, IDT, or TSS.
288 if (within_cpu_entry(attr->bp_addr, bp_end))
291 hw->address = attr->bp_addr;
295 switch (attr->bp_type) {
296 case HW_BREAKPOINT_W:
297 hw->type = X86_BREAKPOINT_WRITE;
299 case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
300 hw->type = X86_BREAKPOINT_RW;
302 case HW_BREAKPOINT_X:
304 * We don't allow kernel breakpoints in places that are not
305 * acceptable for kprobes. On non-kprobes kernels, we don't
306 * allow kernel breakpoints at all.
308 if (attr->bp_addr >= TASK_SIZE_MAX) {
309 if (within_kprobe_blacklist(attr->bp_addr))
313 hw->type = X86_BREAKPOINT_EXECUTE;
315 * x86 inst breakpoints need to have a specific undefined len.
316 * But we still need to check userspace is not trying to setup
317 * an unsupported length, to get a range breakpoint for example.
319 if (attr->bp_len == sizeof(long)) {
320 hw->len = X86_BREAKPOINT_LEN_X;
329 switch (attr->bp_len) {
330 case HW_BREAKPOINT_LEN_1:
331 hw->len = X86_BREAKPOINT_LEN_1;
333 case HW_BREAKPOINT_LEN_2:
334 hw->len = X86_BREAKPOINT_LEN_2;
336 case HW_BREAKPOINT_LEN_4:
337 hw->len = X86_BREAKPOINT_LEN_4;
340 case HW_BREAKPOINT_LEN_8:
341 hw->len = X86_BREAKPOINT_LEN_8;
345 /* AMD range breakpoint */
346 if (!is_power_of_2(attr->bp_len))
348 if (attr->bp_addr & (attr->bp_len - 1))
351 if (!boot_cpu_has(X86_FEATURE_BPEXT))
355 * It's impossible to use a range breakpoint to fake out
356 * user vs kernel detection because bp_len - 1 can't
357 * have the high bit set. If we ever allow range instruction
358 * breakpoints, then we'll have to check for kprobe-blacklisted
359 * addresses anywhere in the range.
361 hw->mask = attr->bp_len - 1;
362 hw->len = X86_BREAKPOINT_LEN_1;
369 * Validate the arch-specific HW Breakpoint register settings
371 int hw_breakpoint_arch_parse(struct perf_event *bp,
372 const struct perf_event_attr *attr,
373 struct arch_hw_breakpoint *hw)
379 ret = arch_build_bp_info(bp, attr, hw);
384 case X86_BREAKPOINT_LEN_1:
389 case X86_BREAKPOINT_LEN_2:
392 case X86_BREAKPOINT_LEN_4:
396 case X86_BREAKPOINT_LEN_8:
406 * Check that the low-order bits of the address are appropriate
407 * for the alignment implied by len.
409 if (hw->address & align)
416 * Dump the debug register contents to the user.
417 * We can't dump our per cpu values because it
418 * may contain cpu wide breakpoint, something that
419 * doesn't belong to the current task.
421 * TODO: include non-ptrace user breakpoints (perf)
423 void aout_dump_debugregs(struct user *dump)
427 struct perf_event *bp;
428 struct arch_hw_breakpoint *info;
429 struct thread_struct *thread = ¤t->thread;
431 for (i = 0; i < HBP_NUM; i++) {
432 bp = thread->ptrace_bps[i];
434 if (bp && !bp->attr.disabled) {
435 dump->u_debugreg[i] = bp->attr.bp_addr;
436 info = counter_arch_bp(bp);
437 dr7 |= encode_dr7(i, info->len, info->type);
439 dump->u_debugreg[i] = 0;
443 dump->u_debugreg[4] = 0;
444 dump->u_debugreg[5] = 0;
445 dump->u_debugreg[6] = current->thread.debugreg6;
447 dump->u_debugreg[7] = dr7;
449 EXPORT_SYMBOL_GPL(aout_dump_debugregs);
452 * Release the user breakpoints used by ptrace
454 void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
457 struct thread_struct *t = &tsk->thread;
459 for (i = 0; i < HBP_NUM; i++) {
460 unregister_hw_breakpoint(t->ptrace_bps[i]);
461 t->ptrace_bps[i] = NULL;
468 void hw_breakpoint_restore(void)
470 set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0);
471 set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1);
472 set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2);
473 set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3);
474 set_debugreg(current->thread.debugreg6, 6);
475 set_debugreg(__this_cpu_read(cpu_dr7), 7);
477 EXPORT_SYMBOL_GPL(hw_breakpoint_restore);
480 * Handle debug exception notifications.
482 * Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
484 * NOTIFY_DONE returned if one of the following conditions is true.
485 * i) When the causative address is from user-space and the exception
486 * is a valid one, i.e. not triggered as a result of lazy debug register
488 * ii) When there are more bits than trap<n> set in DR6 register (such
489 * as BD, BS or BT) indicating that more than one debug condition is
490 * met and requires some more action in do_debug().
492 * NOTIFY_STOP returned for all other cases
495 static int hw_breakpoint_handler(struct die_args *args)
497 int i, cpu, rc = NOTIFY_STOP;
498 struct perf_event *bp;
500 unsigned long *dr6_p;
502 /* The DR6 value is pointed by args->err */
503 dr6_p = (unsigned long *)ERR_PTR(args->err);
506 /* If it's a single step, TRAP bits are random */
510 /* Do an early return if no trap bits are set in DR6 */
511 if ((dr6 & DR_TRAP_BITS) == 0)
515 * Assert that local interrupts are disabled
516 * Reset the DRn bits in the virtualized register value.
517 * The ptrace trigger routine will add in whatever is needed.
519 current->thread.debugreg6 &= ~DR_TRAP_BITS;
522 /* Handle all the breakpoints that were triggered */
523 for (i = 0; i < HBP_NUM; ++i) {
524 if (likely(!(dr6 & (DR_TRAP0 << i))))
528 * The counter may be concurrently released but that can only
529 * occur from a call_rcu() path. We can then safely fetch
530 * the breakpoint, use its callback, touch its counter
531 * while we are in an rcu_read_lock() path.
535 bp = per_cpu(bp_per_reg[i], cpu);
537 * Reset the 'i'th TRAP bit in dr6 to denote completion of
540 (*dr6_p) &= ~(DR_TRAP0 << i);
542 * bp can be NULL due to lazy debug register switching
543 * or due to concurrent perf counter removing.
550 perf_bp_event(bp, args->regs);
553 * Set up resume flag to avoid breakpoint recursion when
554 * returning back to origin.
556 if (bp->hw.info.type == X86_BREAKPOINT_EXECUTE)
557 args->regs->flags |= X86_EFLAGS_RF;
562 * Further processing in do_debug() is needed for a) user-space
563 * breakpoints (to generate signals) and b) when the system has
564 * taken exception due to multiple causes
566 if ((current->thread.debugreg6 & DR_TRAP_BITS) ||
567 (dr6 & (~DR_TRAP_BITS)))
576 * Handle debug exception notifications.
578 int hw_breakpoint_exceptions_notify(
579 struct notifier_block *unused, unsigned long val, void *data)
581 if (val != DIE_DEBUG)
584 return hw_breakpoint_handler(data);
587 void hw_breakpoint_pmu_read(struct perf_event *bp)