1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
13 #include <linux/linkage.h>
14 #include <linux/threads.h>
15 #include <linux/init.h>
16 #include <linux/pgtable.h>
17 #include <asm/segment.h>
20 #include <asm/cache.h>
21 #include <asm/processor-flags.h>
22 #include <asm/percpu.h>
24 #include "../entry/calling.h"
25 #include <asm/export.h>
26 #include <asm/nospec-branch.h>
27 #include <asm/fixmap.h>
29 #ifdef CONFIG_PARAVIRT_XXL
30 #include <asm/asm-offsets.h>
31 #include <asm/paravirt.h>
32 #define GET_CR2_INTO(reg) GET_CR2_INTO_AX ; _ASM_MOV %_ASM_AX, reg
34 #define INTERRUPT_RETURN iretq
35 #define GET_CR2_INTO(reg) _ASM_MOV %cr2, reg
39 * We are not able to switch in one step to the final KERNEL ADDRESS SPACE
40 * because we need identity-mapped pages.
42 #define l4_index(x) (((x) >> 39) & 511)
43 #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
45 L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
46 L4_START_KERNEL = l4_index(__START_KERNEL_map)
48 L3_START_KERNEL = pud_index(__START_KERNEL_map)
53 SYM_CODE_START_NOALIGN(startup_64)
56 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
57 * and someone has loaded an identity mapped page table
58 * for us. These identity mapped page tables map all of the
59 * kernel pages and possibly all of memory.
61 * %rsi holds a physical pointer to real_mode_data.
63 * We come here either directly from a 64bit bootloader, or from
64 * arch/x86/boot/compressed/head_64.S.
66 * We only come here initially at boot nothing else comes here.
68 * Since we may be loaded at an address different from what we were
69 * compiled to run at we first fixup the physical addresses in our page
70 * tables and then reload them.
73 /* Set up the stack for verify_cpu(), similar to initial_stack below */
74 leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp
76 leaq _text(%rip), %rdi
78 call startup_64_setup_env
81 /* Now switch to __KERNEL_CS so IRET works reliably */
83 leaq .Lon_kernel_cs(%rip), %rax
90 /* Sanitize CPU configuration */
94 * Perform pagetable fixups. Additionally, if SME is active, encrypt
95 * the kernel and retrieve the modifier (SME encryption mask if SME
96 * is active) to be added to the initial pgdir entry that will be
97 * programmed into CR3.
99 leaq _text(%rip), %rdi
104 /* Form the CR3 value being sure to include the CR3 modifier */
105 addq $(early_top_pgt - __START_KERNEL_map), %rax
107 SYM_CODE_END(startup_64)
109 SYM_CODE_START(secondary_startup_64)
112 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
113 * and someone has loaded a mapped page table.
115 * %rsi holds a physical pointer to real_mode_data.
117 * We come here either from startup_64 (using physical addresses)
118 * or from trampoline.S (using virtual addresses).
120 * Using virtual addresses from trampoline.S removes the need
121 * to have any identity mapped pages in the kernel page table
122 * after the boot processor executes this code.
125 /* Sanitize CPU configuration */
129 * Retrieve the modifier (SME encryption mask if SME is active) to be
130 * added to the initial pgdir entry that will be programmed into CR3.
133 call __startup_secondary_64
136 /* Form the CR3 value being sure to include the CR3 modifier */
137 addq $(init_top_pgt - __START_KERNEL_map), %rax
140 /* Enable PAE mode, PGE and LA57 */
141 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
142 #ifdef CONFIG_X86_5LEVEL
143 testl $1, __pgtable_l5_enabled(%rip)
145 orl $X86_CR4_LA57, %ecx
150 /* Setup early boot stage 4-/5-level pagetables. */
151 addq phys_base(%rip), %rax
154 /* Ensure I am executing from virtual addresses */
156 ANNOTATE_RETPOLINE_SAFE
162 * We must switch to a new descriptor in kernel space for the GDT
163 * because soon the kernel won't have access anymore to the userspace
164 * addresses where we're currently running on. We have to do that here
165 * because in 32bit we couldn't load a 64bit linear address.
167 lgdt early_gdt_descr(%rip)
169 /* set up data segments */
176 * We don't really need to load %fs or %gs, but load them anyway
177 * to kill any stale realmode selectors. This allows execution
185 * The base of %gs always points to fixed_percpu_data. If the
186 * stack protector canary is enabled, it is located at %gs:40.
187 * Note that, on SMP, the boot cpu uses init data section until
188 * the per cpu areas are set up.
190 movl $MSR_GS_BASE,%ecx
191 movl initial_gs(%rip),%eax
192 movl initial_gs+4(%rip),%edx
195 /* Check if nx is implemented */
196 movl $0x80000001, %eax
200 /* Setup EFER (Extended Feature Enable Register) */
203 btsl $_EFER_SCE, %eax /* Enable System Call */
204 btl $20,%edi /* No Execute supported? */
207 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
208 1: wrmsr /* Make changes effective */
211 movl $CR0_STATE, %eax
212 /* Make changes effective */
215 /* Setup a boot time stack */
216 movq initial_stack(%rip), %rsp
218 /* zero EFLAGS after setting rsp */
222 /* rsi is pointer to real mode structure with interesting info.
228 * Jump to run C code and to be on a real kernel address.
229 * Since we are running on identity-mapped space we have to jump
230 * to the full 64bit address, this is only possible as indirect
231 * jump. In addition we need to ensure %cs is set so we make this
234 * Note: do not change to far jump indirect with 64bit offset.
236 * AMD does not support far jump indirect with 64bit offset.
237 * AMD64 Architecture Programmer's Manual, Volume 3: states only
238 * JMP FAR mem16:16 FF /5 Far jump indirect,
239 * with the target specified by a far pointer in memory.
240 * JMP FAR mem16:32 FF /5 Far jump indirect,
241 * with the target specified by a far pointer in memory.
243 * Intel64 does support 64bit offset.
244 * Software Developer Manual Vol 2: states:
245 * FF /5 JMP m16:16 Jump far, absolute indirect,
246 * address given in m16:16
247 * FF /5 JMP m16:32 Jump far, absolute indirect,
248 * address given in m16:32.
249 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
250 * address given in m16:64.
252 pushq $.Lafter_lret # put return address on stack for unwinder
253 xorl %ebp, %ebp # clear frame pointer
254 movq initial_code(%rip), %rax
255 pushq $__KERNEL_CS # set correct cs
256 pushq %rax # target address in negative space
259 SYM_CODE_END(secondary_startup_64)
261 #include "verify_cpu.S"
263 #ifdef CONFIG_HOTPLUG_CPU
265 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
266 * up already except stack. We just set up stack here. Then call
267 * start_secondary() via .Ljump_to_C_code.
269 SYM_CODE_START(start_cpu0)
271 movq initial_stack(%rip), %rsp
273 SYM_CODE_END(start_cpu0)
276 /* Both SMP bootup and ACPI suspend change these variables */
279 SYM_DATA(initial_code, .quad x86_64_start_kernel)
280 SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data))
283 * The SIZEOF_PTREGS gap is a convention which helps the in-kernel unwinder
284 * reliably detect the end of the stack.
286 SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS)
290 SYM_CODE_START(early_idt_handler_array)
292 .rept NUM_EXCEPTION_VECTORS
293 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
294 UNWIND_HINT_IRET_REGS
295 pushq $0 # Dummy error code, to make stack frame uniform
297 UNWIND_HINT_IRET_REGS offset=8
299 pushq $i # 72(%rsp) Vector number
300 jmp early_idt_handler_common
301 UNWIND_HINT_IRET_REGS
303 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
305 UNWIND_HINT_IRET_REGS offset=16
306 SYM_CODE_END(early_idt_handler_array)
308 SYM_CODE_START_LOCAL(early_idt_handler_common)
310 * The stack is the hardware frame, an error code or zero, and the
315 incl early_recursion_flag(%rip)
317 /* The vector number is currently in the pt_regs->di slot. */
318 pushq %rsi /* pt_regs->si */
319 movq 8(%rsp), %rsi /* RSI = vector number */
320 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
321 pushq %rdx /* pt_regs->dx */
322 pushq %rcx /* pt_regs->cx */
323 pushq %rax /* pt_regs->ax */
324 pushq %r8 /* pt_regs->r8 */
325 pushq %r9 /* pt_regs->r9 */
326 pushq %r10 /* pt_regs->r10 */
327 pushq %r11 /* pt_regs->r11 */
328 pushq %rbx /* pt_regs->bx */
329 pushq %rbp /* pt_regs->bp */
330 pushq %r12 /* pt_regs->r12 */
331 pushq %r13 /* pt_regs->r13 */
332 pushq %r14 /* pt_regs->r14 */
333 pushq %r15 /* pt_regs->r15 */
336 cmpq $14,%rsi /* Page fault? */
338 GET_CR2_INTO(%rdi) /* can clobber %rax if pv */
339 call early_make_pgtable
341 jz 20f /* All good */
344 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
345 call early_fixup_exception
348 decl early_recursion_flag(%rip)
349 jmp restore_regs_and_return_to_kernel
350 SYM_CODE_END(early_idt_handler_common)
353 #define SYM_DATA_START_PAGE_ALIGNED(name) \
354 SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE)
356 #ifdef CONFIG_PAGE_TABLE_ISOLATION
358 * Each PGD needs to be 8k long and 8k aligned. We do not
359 * ever go out to userspace with these, so we do not
360 * strictly *need* the second page, but this allows us to
361 * have a single set_pgd() implementation that does not
362 * need to worry about whether it has 4k or 8k to work
365 * This ensures PGDs are 8k long:
367 #define PTI_USER_PGD_FILL 512
368 /* This ensures they are 8k-aligned: */
369 #define SYM_DATA_START_PTI_ALIGNED(name) \
370 SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE)
372 #define SYM_DATA_START_PTI_ALIGNED(name) \
373 SYM_DATA_START_PAGE_ALIGNED(name)
374 #define PTI_USER_PGD_FILL 0
377 /* Automate the creation of 1 to 1 mapping pmd entries */
378 #define PMDS(START, PERM, COUNT) \
381 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
388 SYM_DATA_START_PTI_ALIGNED(early_top_pgt)
390 .fill PTI_USER_PGD_FILL,8,0
391 SYM_DATA_END(early_top_pgt)
393 SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts)
394 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
395 SYM_DATA_END(early_dynamic_pgts)
397 SYM_DATA(early_recursion_flag, .long 0)
401 #if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH)
402 SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
403 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
404 .org init_top_pgt + L4_PAGE_OFFSET*8, 0
405 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
406 .org init_top_pgt + L4_START_KERNEL*8, 0
407 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
408 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
409 .fill PTI_USER_PGD_FILL,8,0
410 SYM_DATA_END(init_top_pgt)
412 SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt)
413 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
415 SYM_DATA_END(level3_ident_pgt)
416 SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt)
418 * Since I easily can, map the first 1G.
419 * Don't set NX because code runs from these pages.
421 * Note: This sets _PAGE_GLOBAL despite whether
422 * the CPU supports it or it is enabled. But,
423 * the CPU should ignore the bit.
425 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
426 SYM_DATA_END(level2_ident_pgt)
428 SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
430 .fill PTI_USER_PGD_FILL,8,0
431 SYM_DATA_END(init_top_pgt)
434 #ifdef CONFIG_X86_5LEVEL
435 SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt)
437 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
438 SYM_DATA_END(level4_kernel_pgt)
441 SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt)
442 .fill L3_START_KERNEL,8,0
443 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
444 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
445 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
446 SYM_DATA_END(level3_kernel_pgt)
448 SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt)
450 * 512 MB kernel mapping. We spend a full page on this pagetable
453 * The kernel code+data+bss must not be bigger than that.
455 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
456 * If you want to increase this then increase MODULES_VADDR
459 * This table is eventually used by the kernel during normal
460 * runtime. Care must be taken to clear out undesired bits
461 * later, like _PAGE_RW or _PAGE_GLOBAL in some cases.
463 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
464 KERNEL_IMAGE_SIZE/PMD_SIZE)
465 SYM_DATA_END(level2_kernel_pgt)
467 SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt)
468 .fill (512 - 4 - FIXMAP_PMD_NUM),8,0
470 .rept (FIXMAP_PMD_NUM)
471 .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \
475 /* 6 MB reserved space + a 2MB hole */
477 SYM_DATA_END(level2_fixmap_pgt)
479 SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt)
480 .rept (FIXMAP_PMD_NUM)
483 SYM_DATA_END(level1_fixmap_pgt)
490 SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1)
491 SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page))
494 /* This must match the first entry in level2_kernel_pgt */
495 SYM_DATA(phys_base, .quad 0x0)
496 EXPORT_SYMBOL(phys_base)
498 #include "../../x86/xen/xen-head.S"
501 SYM_DATA_START_PAGE_ALIGNED(empty_zero_page)
503 SYM_DATA_END(empty_zero_page)
504 EXPORT_SYMBOL(empty_zero_page)