2 * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
8 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
12 #include <linux/linkage.h>
13 #include <linux/threads.h>
14 #include <linux/init.h>
15 #include <asm/segment.h>
16 #include <asm/pgtable.h>
19 #include <asm/cache.h>
20 #include <asm/processor-flags.h>
21 #include <asm/percpu.h>
24 #ifdef CONFIG_PARAVIRT
25 #include <asm/asm-offsets.h>
26 #include <asm/paravirt.h>
27 #define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
29 #define GET_CR2_INTO(reg) movq %cr2, reg
30 #define INTERRUPT_RETURN iretq
33 /* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
34 * because we need identity-mapped pages.
38 #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
40 L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
41 L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
42 L4_START_KERNEL = pgd_index(__START_KERNEL_map)
43 L3_START_KERNEL = pud_index(__START_KERNEL_map)
51 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
52 * and someone has loaded an identity mapped page table
53 * for us. These identity mapped page tables map all of the
54 * kernel pages and possibly all of memory.
56 * %rsi holds a physical pointer to real_mode_data.
58 * We come here either directly from a 64bit bootloader, or from
59 * arch/x86_64/boot/compressed/head.S.
61 * We only come here initially at boot nothing else comes here.
63 * Since we may be loaded at an address different from what we were
64 * compiled to run at we first fixup the physical addresses in our page
65 * tables and then reload them.
69 * Compute the delta between the address I am compiled to run at and the
70 * address I am actually running at.
72 leaq _text(%rip), %rbp
73 subq $_text - __START_KERNEL_map, %rbp
75 /* Is the address not 2M aligned? */
77 andl $~PMD_PAGE_MASK, %eax
82 * Is the address too large?
84 leaq _text(%rip), %rax
85 shrq $MAX_PHYSMEM_BITS, %rax
89 * Fixup the physical addresses in the page table
91 addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip)
93 addq %rbp, level3_kernel_pgt + (510*8)(%rip)
94 addq %rbp, level3_kernel_pgt + (511*8)(%rip)
96 addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
99 * Set up the identity mapping for the switchover. These
100 * entries should *NOT* have the global bit set! This also
101 * creates a bunch of nonsense entries but that is fine --
102 * it avoids problems around wraparound.
104 leaq _text(%rip), %rdi
105 leaq early_level4_pgt(%rip), %rbx
108 shrq $PGDIR_SHIFT, %rax
110 leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx
111 movq %rdx, 0(%rbx,%rax,8)
112 movq %rdx, 8(%rbx,%rax,8)
116 shrq $PUD_SHIFT, %rax
117 andl $(PTRS_PER_PUD-1), %eax
118 movq %rdx, (4096+0)(%rbx,%rax,8)
119 movq %rdx, (4096+8)(%rbx,%rax,8)
123 shrq $PMD_SHIFT, %rdi
124 addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax
125 leaq (_end - 1)(%rip), %rcx
126 shrq $PMD_SHIFT, %rcx
131 andq $(PTRS_PER_PMD - 1), %rdi
132 movq %rax, (%rbx,%rdi,8)
139 * Fixup the kernel text+data virtual addresses. Note that
140 * we might write invalid pmds, when the kernel is relocated
141 * cleanup_highmap() fixes this up along with the mappings
144 leaq level2_kernel_pgt(%rip), %rdi
146 /* See if it is a valid page table entry */
150 /* Go to the next page */
155 /* Fixup phys_base */
156 addq %rbp, phys_base(%rip)
158 movq $(early_level4_pgt - __START_KERNEL_map), %rax
160 ENTRY(secondary_startup_64)
162 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
163 * and someone has loaded a mapped page table.
165 * %rsi holds a physical pointer to real_mode_data.
167 * We come here either from startup_64 (using physical addresses)
168 * or from trampoline.S (using virtual addresses).
170 * Using virtual addresses from trampoline.S removes the need
171 * to have any identity mapped pages in the kernel page table
172 * after the boot processor executes this code.
175 movq $(init_level4_pgt - __START_KERNEL_map), %rax
178 /* Enable PAE mode and PGE */
179 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
182 /* Setup early boot stage 4 level pagetables. */
183 addq phys_base(%rip), %rax
186 /* Ensure I am executing from virtual addresses */
191 /* Check if nx is implemented */
192 movl $0x80000001, %eax
196 /* Setup EFER (Extended Feature Enable Register) */
199 btsl $_EFER_SCE, %eax /* Enable System Call */
200 btl $20,%edi /* No Execute supported? */
203 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
204 1: wrmsr /* Make changes effective */
207 #define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
208 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
210 movl $CR0_STATE, %eax
211 /* Make changes effective */
214 /* Setup a boot time stack */
215 movq stack_start(%rip), %rsp
217 /* zero EFLAGS after setting rsp */
222 * We must switch to a new descriptor in kernel space for the GDT
223 * because soon the kernel won't have access anymore to the userspace
224 * addresses where we're currently running on. We have to do that here
225 * because in 32bit we couldn't load a 64bit linear address.
227 lgdt early_gdt_descr(%rip)
229 /* set up data segments */
236 * We don't really need to load %fs or %gs, but load them anyway
237 * to kill any stale realmode selectors. This allows execution
245 * The base of %gs always points to the bottom of the irqstack
246 * union. If the stack protector canary is enabled, it is
247 * located at %gs:40. Note that, on SMP, the boot cpu uses
248 * init data section till per cpu areas are set up.
250 movl $MSR_GS_BASE,%ecx
251 movl initial_gs(%rip),%eax
252 movl initial_gs+4(%rip),%edx
255 /* rsi is pointer to real mode structure with interesting info.
259 /* Finally jump to run C code and to be on real kernel address
260 * Since we are running on identity-mapped space we have to jump
261 * to the full 64bit address, this is only possible as indirect
262 * jump. In addition we need to ensure %cs is set so we make this
265 * Note: do not change to far jump indirect with 64bit offset.
267 * AMD does not support far jump indirect with 64bit offset.
268 * AMD64 Architecture Programmer's Manual, Volume 3: states only
269 * JMP FAR mem16:16 FF /5 Far jump indirect,
270 * with the target specified by a far pointer in memory.
271 * JMP FAR mem16:32 FF /5 Far jump indirect,
272 * with the target specified by a far pointer in memory.
274 * Intel64 does support 64bit offset.
275 * Software Developer Manual Vol 2: states:
276 * FF /5 JMP m16:16 Jump far, absolute indirect,
277 * address given in m16:16
278 * FF /5 JMP m16:32 Jump far, absolute indirect,
279 * address given in m16:32.
280 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
281 * address given in m16:64.
283 movq initial_code(%rip),%rax
284 pushq $0 # fake return address to stop unwinder
285 pushq $__KERNEL_CS # set correct cs
286 pushq %rax # target address in negative space
289 #ifdef CONFIG_HOTPLUG_CPU
291 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
292 * up already except stack. We just set up stack here. Then call
296 movq stack_start(%rip),%rsp
297 movq initial_code(%rip),%rax
298 pushq $0 # fake return address to stop unwinder
299 pushq $__KERNEL_CS # set correct cs
300 pushq %rax # target address in negative space
305 /* SMP bootup changes these two */
309 .quad x86_64_start_kernel
311 .quad INIT_PER_CPU_VAR(irq_stack_union)
314 .quad init_thread_union+THREAD_SIZE-8
322 .globl early_idt_handlers
327 # 80(%rsp) error code
329 .rept NUM_EXCEPTION_VECTORS
330 .if (EXCEPTION_ERRCODE_MASK >> i) & 1
333 pushq $0 # Dummy error code, to make stack frame uniform
335 pushq $i # 72(%rsp) Vector number
336 jmp early_idt_handler
340 /* This is global to keep gas from relaxing the jumps */
341 ENTRY(early_idt_handler)
344 cmpl $2,early_recursion_flag(%rip)
346 incl early_recursion_flag(%rip)
348 pushq %rax # 64(%rsp)
349 pushq %rcx # 56(%rsp)
350 pushq %rdx # 48(%rsp)
351 pushq %rsi # 40(%rsp)
352 pushq %rdi # 32(%rsp)
358 cmpl $__KERNEL_CS,96(%rsp)
361 cmpl $14,72(%rsp) # Page fault?
363 GET_CR2_INTO(%rdi) # can clobber any volatile register if pv
364 call early_make_pgtable
369 leaq 88(%rsp),%rdi # Pointer to %rip
370 call early_fixup_exception
372 jnz 20f # Found an exception entry
375 #ifdef CONFIG_EARLY_PRINTK
376 GET_CR2_INTO(%r9) # can clobber any volatile register if pv
377 movl 80(%rsp),%r8d # error code
378 movl 72(%rsp),%esi # vector number
379 movl 96(%rsp),%edx # %cs
380 movq 88(%rsp),%rcx # %rip
382 leaq early_idt_msg(%rip),%rdi
384 cmpl $2,early_recursion_flag(%rip)
387 #ifdef CONFIG_KALLSYMS
388 leaq early_idt_ripmsg(%rip),%rdi
389 movq 40(%rsp),%rsi # %rip again
392 #endif /* EARLY_PRINTK */
396 20: # Exception table entry found or page table generated
406 addq $16,%rsp # drop vector number and error code
407 decl early_recursion_flag(%rip)
409 ENDPROC(early_idt_handler)
414 early_recursion_flag:
417 #ifdef CONFIG_EARLY_PRINTK
419 .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
422 #endif /* CONFIG_EARLY_PRINTK */
424 #define NEXT_PAGE(name) \
428 /* Automate the creation of 1 to 1 mapping pmd entries */
429 #define PMDS(START, PERM, COUNT) \
432 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
437 NEXT_PAGE(early_level4_pgt)
439 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
441 NEXT_PAGE(early_dynamic_pgts)
442 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
447 NEXT_PAGE(init_level4_pgt)
450 NEXT_PAGE(init_level4_pgt)
451 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
452 .org init_level4_pgt + L4_PAGE_OFFSET*8, 0
453 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
454 .org init_level4_pgt + L4_START_KERNEL*8, 0
455 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
456 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
458 NEXT_PAGE(level3_ident_pgt)
459 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
461 NEXT_PAGE(level2_ident_pgt)
462 /* Since I easily can, map the first 1G.
463 * Don't set NX because code runs from these pages.
465 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
468 NEXT_PAGE(level3_kernel_pgt)
469 .fill L3_START_KERNEL,8,0
470 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
471 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
472 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
474 NEXT_PAGE(level2_kernel_pgt)
476 * 512 MB kernel mapping. We spend a full page on this pagetable
479 * The kernel code+data+bss must not be bigger than that.
481 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
482 * If you want to increase this then increase MODULES_VADDR
485 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
486 KERNEL_IMAGE_SIZE/PMD_SIZE)
488 NEXT_PAGE(level2_fixmap_pgt)
490 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
491 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
494 NEXT_PAGE(level1_fixmap_pgt)
501 .globl early_gdt_descr
503 .word GDT_ENTRIES*8-1
504 early_gdt_descr_base:
505 .quad INIT_PER_CPU_VAR(gdt_page)
508 /* This must match the first entry in level2_kernel_pgt */
509 .quad 0x0000000000000000
511 #include "../../x86/xen/xen-head.S"
513 .section .bss, "aw", @nobits
514 .align L1_CACHE_BYTES
516 .skip IDT_ENTRIES * 16
518 .align L1_CACHE_BYTES
520 .skip IDT_ENTRIES * 16
523 NEXT_PAGE(empty_zero_page)