1 // SPDX-License-Identifier: GPL-2.0
3 * FPU register's regset abstraction, for ptrace, core dumps, etc.
5 #include <linux/sched/task_stack.h>
6 #include <linux/vmalloc.h>
8 #include <asm/fpu/internal.h>
9 #include <asm/fpu/signal.h>
10 #include <asm/fpu/regset.h>
11 #include <asm/fpu/xstate.h>
14 * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
15 * as the "regset->n" for the xstate regset will be updated based on the feature
16 * capabilities supported by the xsave.
18 int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
23 int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
25 if (boot_cpu_has(X86_FEATURE_FXSR))
32 * The regset get() functions are invoked from:
34 * - coredump to dump the current task's fpstate. If the current task
35 * owns the FPU then the memory state has to be synchronized and the
36 * FPU register state preserved. Otherwise fpstate is already in sync.
38 * - ptrace to dump fpstate of a stopped task, in which case the registers
39 * have already been saved to fpstate on context switch.
41 static void sync_fpstate(struct fpu *fpu)
43 if (fpu == ¤t->thread.fpu)
44 fpu_sync_fpstate(fpu);
48 * Invalidate cached FPU registers before modifying the stopped target
51 * This forces the target task on resume to restore the FPU registers from
52 * modified fpstate. Otherwise the task might skip the restore and operate
53 * with the cached FPU registers which discards the modifications.
55 static void fpu_force_restore(struct fpu *fpu)
58 * Only stopped child tasks can be used to modify the FPU
59 * state in the fpstate buffer:
61 WARN_ON_FPU(fpu == ¤t->thread.fpu);
63 __fpu_invalidate_fpregs_state(fpu);
66 int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
69 struct fpu *fpu = &target->thread.fpu;
71 if (!cpu_feature_enabled(X86_FEATURE_FXSR))
77 return membuf_write(&to, &fpu->state.fxsave,
78 sizeof(fpu->state.fxsave));
81 copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_FX);
85 int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
86 unsigned int pos, unsigned int count,
87 const void *kbuf, const void __user *ubuf)
89 struct fpu *fpu = &target->thread.fpu;
90 struct user32_fxsr_struct newstate;
93 BUILD_BUG_ON(sizeof(newstate) != sizeof(struct fxregs_state));
95 if (!cpu_feature_enabled(X86_FEATURE_FXSR))
98 /* No funny business with partial or oversized writes is permitted. */
99 if (pos != 0 || count != sizeof(newstate))
102 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);
106 /* Do not allow an invalid MXCSR value. */
107 if (newstate.mxcsr & ~mxcsr_feature_mask)
110 fpu_force_restore(fpu);
113 memcpy(&fpu->state.fxsave, &newstate, sizeof(newstate));
116 BUILD_BUG_ON(sizeof(fpu->state.fxsave.xmm_space) != 16 * 16);
117 memset(&fpu->state.fxsave.xmm_space[8], 0, 8 * 16);
119 /* Mark FP and SSE as in use when XSAVE is enabled */
121 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
126 int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
129 if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
132 sync_fpstate(&target->thread.fpu);
134 copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_XSAVE);
138 int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
139 unsigned int pos, unsigned int count,
140 const void *kbuf, const void __user *ubuf)
142 struct fpu *fpu = &target->thread.fpu;
143 struct xregs_state *tmpbuf = NULL;
146 if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
150 * A whole standard-format XSAVE buffer is needed:
152 if (pos != 0 || count != fpu_user_xstate_size)
156 tmpbuf = vmalloc(count);
160 if (copy_from_user(tmpbuf, ubuf, count)) {
166 fpu_force_restore(fpu);
167 ret = copy_uabi_from_kernel_to_xstate(&fpu->state.xsave, kbuf ?: tmpbuf);
174 #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
177 * FPU tag word conversions.
180 static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
182 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
184 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
186 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
187 /* and move the valid bits to the lower byte. */
188 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
189 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
190 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
195 #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
196 #define FP_EXP_TAG_VALID 0
197 #define FP_EXP_TAG_ZERO 1
198 #define FP_EXP_TAG_SPECIAL 2
199 #define FP_EXP_TAG_EMPTY 3
201 static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
204 u32 tos = (fxsave->swd >> 11) & 7;
205 u32 twd = (unsigned long) fxsave->twd;
207 u32 ret = 0xffff0000u;
210 for (i = 0; i < 8; i++, twd >>= 1) {
212 st = FPREG_ADDR(fxsave, (i - tos) & 7);
214 switch (st->exponent & 0x7fff) {
216 tag = FP_EXP_TAG_SPECIAL;
219 if (!st->significand[0] &&
220 !st->significand[1] &&
221 !st->significand[2] &&
223 tag = FP_EXP_TAG_ZERO;
225 tag = FP_EXP_TAG_SPECIAL;
228 if (st->significand[3] & 0x8000)
229 tag = FP_EXP_TAG_VALID;
231 tag = FP_EXP_TAG_SPECIAL;
235 tag = FP_EXP_TAG_EMPTY;
237 ret |= tag << (2 * i);
243 * FXSR floating point environment conversions.
246 static void __convert_from_fxsr(struct user_i387_ia32_struct *env,
247 struct task_struct *tsk,
248 struct fxregs_state *fxsave)
250 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
251 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
254 env->cwd = fxsave->cwd | 0xffff0000u;
255 env->swd = fxsave->swd | 0xffff0000u;
256 env->twd = twd_fxsr_to_i387(fxsave);
259 env->fip = fxsave->rip;
260 env->foo = fxsave->rdp;
262 * should be actually ds/cs at fpu exception time, but
263 * that information is not available in 64bit mode.
265 env->fcs = task_pt_regs(tsk)->cs;
266 if (tsk == current) {
267 savesegment(ds, env->fos);
269 env->fos = tsk->thread.ds;
271 env->fos |= 0xffff0000;
273 env->fip = fxsave->fip;
274 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
275 env->foo = fxsave->foo;
276 env->fos = fxsave->fos;
279 for (i = 0; i < 8; ++i)
280 memcpy(&to[i], &from[i], sizeof(to[0]));
284 convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
286 __convert_from_fxsr(env, tsk, &tsk->thread.fpu.state.fxsave);
289 void convert_to_fxsr(struct fxregs_state *fxsave,
290 const struct user_i387_ia32_struct *env)
293 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
294 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
297 fxsave->cwd = env->cwd;
298 fxsave->swd = env->swd;
299 fxsave->twd = twd_i387_to_fxsr(env->twd);
300 fxsave->fop = (u16) ((u32) env->fcs >> 16);
302 fxsave->rip = env->fip;
303 fxsave->rdp = env->foo;
304 /* cs and ds ignored */
306 fxsave->fip = env->fip;
307 fxsave->fcs = (env->fcs & 0xffff);
308 fxsave->foo = env->foo;
309 fxsave->fos = env->fos;
312 for (i = 0; i < 8; ++i)
313 memcpy(&to[i], &from[i], sizeof(from[0]));
316 int fpregs_get(struct task_struct *target, const struct user_regset *regset,
319 struct fpu *fpu = &target->thread.fpu;
320 struct user_i387_ia32_struct env;
321 struct fxregs_state fxsave, *fx;
325 if (!cpu_feature_enabled(X86_FEATURE_FPU))
326 return fpregs_soft_get(target, regset, to);
328 if (!cpu_feature_enabled(X86_FEATURE_FXSR)) {
329 return membuf_write(&to, &fpu->state.fsave,
330 sizeof(struct fregs_state));
334 struct membuf mb = { .p = &fxsave, .left = sizeof(fxsave) };
336 /* Handle init state optimized xstate correctly */
337 copy_xstate_to_uabi_buf(mb, target, XSTATE_COPY_FP);
340 fx = &fpu->state.fxsave;
343 __convert_from_fxsr(&env, target, fx);
344 return membuf_write(&to, &env, sizeof(env));
347 int fpregs_set(struct task_struct *target, const struct user_regset *regset,
348 unsigned int pos, unsigned int count,
349 const void *kbuf, const void __user *ubuf)
351 struct fpu *fpu = &target->thread.fpu;
352 struct user_i387_ia32_struct env;
355 /* No funny business with partial or oversized writes is permitted. */
356 if (pos != 0 || count != sizeof(struct user_i387_ia32_struct))
359 if (!cpu_feature_enabled(X86_FEATURE_FPU))
360 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
362 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
366 fpu_force_restore(fpu);
368 if (cpu_feature_enabled(X86_FEATURE_FXSR))
369 convert_to_fxsr(&fpu->state.fxsave, &env);
371 memcpy(&fpu->state.fsave, &env, sizeof(env));
374 * Update the header bit in the xsave header, indicating the
377 if (cpu_feature_enabled(X86_FEATURE_XSAVE))
378 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FP;
383 #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */