arch/x86/kernel/fpu/regset.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * FPU register's regset abstraction, for ptrace, core dumps, etc.
   4  */
   5 #include <linux/sched/task_stack.h>
   6 #include <linux/vmalloc.h>
   7
   8 #include <asm/fpu/internal.h>
   9 #include <asm/fpu/signal.h>
  10 #include <asm/fpu/regset.h>
  11 #include <asm/fpu/xstate.h>
  12
  13 /*
  14  * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
  15  * as the "regset->n" for the xstate regset will be updated based on the feature
  16  * capabilities supported by the xsave.
  17  */
  18 int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
  19 {
  20         return regset->n;
  21 }
  22
  23 int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
  24 {
  25         if (boot_cpu_has(X86_FEATURE_FXSR))
  26                 return regset->n;
  27         else
  28                 return 0;
  29 }
  30
  31 /*
  32  * The regset get() functions are invoked from:
  33  *
  34  *   - coredump to dump the current task's fpstate. If the current task
  35  *     owns the FPU then the memory state has to be synchronized and the
  36  *     FPU register state preserved. Otherwise fpstate is already in sync.
  37  *
  38  *   - ptrace to dump fpstate of a stopped task, in which case the registers
  39  *     have already been saved to fpstate on context switch.
  40  */
  41 static void sync_fpstate(struct fpu *fpu)
  42 {
  43         if (fpu == &current->thread.fpu)
  44                 fpu__save(fpu);
  45 }
  46
  47 int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
  48                 struct membuf to)
  49 {
  50         struct fpu *fpu = &target->thread.fpu;
  51
  52         if (!cpu_feature_enabled(X86_FEATURE_FXSR))
  53                 return -ENODEV;
  54
  55         sync_fpstate(fpu);
  56
  57         if (!use_xsave()) {
  58                 return membuf_write(&to, &fpu->state.fxsave,
  59                                     sizeof(fpu->state.fxsave));
  60         }
  61
  62         copy_xstate_to_uabi_buf(to, &fpu->state.xsave, XSTATE_COPY_FX);
  63         return 0;
  64 }
  65
  66 int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
  67                 unsigned int pos, unsigned int count,
  68                 const void *kbuf, const void __user *ubuf)
  69 {
  70         struct fpu *fpu = &target->thread.fpu;
  71         struct user32_fxsr_struct newstate;
  72         int ret;
  73
  74         BUILD_BUG_ON(sizeof(newstate) != sizeof(struct fxregs_state));
  75
  76         if (!cpu_feature_enabled(X86_FEATURE_FXSR))
  77                 return -ENODEV;
  78
  79         /* No funny business with partial or oversized writes is permitted. */
  80         if (pos != 0 || count != sizeof(newstate))
  81                 return -EINVAL;
  82
  83         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);
  84         if (ret)
  85                 return ret;
  86
  87         /* Do not allow an invalid MXCSR value. */
  88         if (newstate.mxcsr & ~mxcsr_feature_mask)
  89                 return -EINVAL;
  90
  91         fpu__prepare_write(fpu);
  92
  93         /* Copy the state  */
  94         memcpy(&fpu->state.fxsave, &newstate, sizeof(newstate));
  95
  96         /* Clear xmm8..15 */
  97         BUILD_BUG_ON(sizeof(fpu->state.fxsave.xmm_space) != 16 * 16);
  98         memset(&fpu->state.fxsave.xmm_space[8], 0, 8 * 16);
  99
 100         /* Mark FP and SSE as in use when XSAVE is enabled */
 101         if (use_xsave())
 102                 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
 103
 104         return 0;
 105 }
 106
 107 int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
 108                 struct membuf to)
 109 {
 110         struct fpu *fpu = &target->thread.fpu;
 111
 112         if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
 113                 return -ENODEV;
 114
 115         sync_fpstate(fpu);
 116
 117         copy_xstate_to_uabi_buf(to, &fpu->state.xsave, XSTATE_COPY_XSAVE);
 118         return 0;
 119 }
 120
 121 int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
 122                   unsigned int pos, unsigned int count,
 123                   const void *kbuf, const void __user *ubuf)
 124 {
 125         struct fpu *fpu = &target->thread.fpu;
 126         struct xregs_state *tmpbuf = NULL;
 127         int ret;
 128
 129         if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
 130                 return -ENODEV;
 131
 132         /*
 133          * A whole standard-format XSAVE buffer is needed:
 134          */
 135         if (pos != 0 || count != fpu_user_xstate_size)
 136                 return -EFAULT;
 137
 138         if (!kbuf) {
 139                 tmpbuf = vmalloc(count);
 140                 if (!tmpbuf)
 141                         return -ENOMEM;
 142
 143                 if (copy_from_user(tmpbuf, ubuf, count)) {
 144                         ret = -EFAULT;
 145                         goto out;
 146                 }
 147         }
 148
 149         fpu__prepare_write(fpu);
 150         ret = copy_kernel_to_xstate(&fpu->state.xsave, kbuf ?: tmpbuf);
 151
 152 out:
 153         vfree(tmpbuf);
 154         return ret;
 155 }
 156
 157 #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
 158
 159 /*
 160  * FPU tag word conversions.
 161  */
 162
 163 static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
 164 {
 165         unsigned int tmp; /* to avoid 16 bit prefixes in the code */
 166
 167         /* Transform each pair of bits into 01 (valid) or 00 (empty) */
 168         tmp = ~twd;
 169         tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
 170         /* and move the valid bits to the lower byte. */
 171         tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
 172         tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
 173         tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
 174
 175         return tmp;
 176 }
 177
 178 #define FPREG_ADDR(f, n)        ((void *)&(f)->st_space + (n) * 16)
 179 #define FP_EXP_TAG_VALID        0
 180 #define FP_EXP_TAG_ZERO         1
 181 #define FP_EXP_TAG_SPECIAL      2
 182 #define FP_EXP_TAG_EMPTY        3
 183
 184 static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
 185 {
 186         struct _fpxreg *st;
 187         u32 tos = (fxsave->swd >> 11) & 7;
 188         u32 twd = (unsigned long) fxsave->twd;
 189         u32 tag;
 190         u32 ret = 0xffff0000u;
 191         int i;
 192
 193         for (i = 0; i < 8; i++, twd >>= 1) {
 194                 if (twd & 0x1) {
 195                         st = FPREG_ADDR(fxsave, (i - tos) & 7);
 196
 197                         switch (st->exponent & 0x7fff) {
 198                         case 0x7fff:
 199                                 tag = FP_EXP_TAG_SPECIAL;
 200                                 break;
 201                         case 0x0000:
 202                                 if (!st->significand[0] &&
 203                                     !st->significand[1] &&
 204                                     !st->significand[2] &&
 205                                     !st->significand[3])
 206                                         tag = FP_EXP_TAG_ZERO;
 207                                 else
 208                                         tag = FP_EXP_TAG_SPECIAL;
 209                                 break;
 210                         default:
 211                                 if (st->significand[3] & 0x8000)
 212                                         tag = FP_EXP_TAG_VALID;
 213                                 else
 214                                         tag = FP_EXP_TAG_SPECIAL;
 215                                 break;
 216                         }
 217                 } else {
 218                         tag = FP_EXP_TAG_EMPTY;
 219                 }
 220                 ret |= tag << (2 * i);
 221         }
 222         return ret;
 223 }
 224
 225 /*
 226  * FXSR floating point environment conversions.
 227  */
 228
 229 static void __convert_from_fxsr(struct user_i387_ia32_struct *env,
 230                                 struct task_struct *tsk,
 231                                 struct fxregs_state *fxsave)
 232 {
 233         struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
 234         struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
 235         int i;
 236
 237         env->cwd = fxsave->cwd | 0xffff0000u;
 238         env->swd = fxsave->swd | 0xffff0000u;
 239         env->twd = twd_fxsr_to_i387(fxsave);
 240
 241 #ifdef CONFIG_X86_64
 242         env->fip = fxsave->rip;
 243         env->foo = fxsave->rdp;
 244         /*
 245          * should be actually ds/cs at fpu exception time, but
 246          * that information is not available in 64bit mode.
 247          */
 248         env->fcs = task_pt_regs(tsk)->cs;
 249         if (tsk == current) {
 250                 savesegment(ds, env->fos);
 251         } else {
 252                 env->fos = tsk->thread.ds;
 253         }
 254         env->fos |= 0xffff0000;
 255 #else
 256         env->fip = fxsave->fip;
 257         env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
 258         env->foo = fxsave->foo;
 259         env->fos = fxsave->fos;
 260 #endif
 261
 262         for (i = 0; i < 8; ++i)
 263                 memcpy(&to[i], &from[i], sizeof(to[0]));
 264 }
 265
 266 void
 267 convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
 268 {
 269         __convert_from_fxsr(env, tsk, &tsk->thread.fpu.state.fxsave);
 270 }
 271
 272 void convert_to_fxsr(struct fxregs_state *fxsave,
 273                      const struct user_i387_ia32_struct *env)
 274
 275 {
 276         struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
 277         struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
 278         int i;
 279
 280         fxsave->cwd = env->cwd;
 281         fxsave->swd = env->swd;
 282         fxsave->twd = twd_i387_to_fxsr(env->twd);
 283         fxsave->fop = (u16) ((u32) env->fcs >> 16);
 284 #ifdef CONFIG_X86_64
 285         fxsave->rip = env->fip;
 286         fxsave->rdp = env->foo;
 287         /* cs and ds ignored */
 288 #else
 289         fxsave->fip = env->fip;
 290         fxsave->fcs = (env->fcs & 0xffff);
 291         fxsave->foo = env->foo;
 292         fxsave->fos = env->fos;
 293 #endif
 294
 295         for (i = 0; i < 8; ++i)
 296                 memcpy(&to[i], &from[i], sizeof(from[0]));
 297 }
 298
 299 int fpregs_get(struct task_struct *target, const struct user_regset *regset,
 300                struct membuf to)
 301 {
 302         struct fpu *fpu = &target->thread.fpu;
 303         struct user_i387_ia32_struct env;
 304         struct fxregs_state fxsave, *fx;
 305
 306         sync_fpstate(fpu);
 307
 308         if (!cpu_feature_enabled(X86_FEATURE_FPU))
 309                 return fpregs_soft_get(target, regset, to);
 310
 311         if (!cpu_feature_enabled(X86_FEATURE_FXSR)) {
 312                 return membuf_write(&to, &fpu->state.fsave,
 313                                     sizeof(struct fregs_state));
 314         }
 315
 316         if (use_xsave()) {
 317                 struct membuf mb = { .p = &fxsave, .left = sizeof(fxsave) };
 318
 319                 /* Handle init state optimized xstate correctly */
 320                 copy_xstate_to_uabi_buf(mb, &fpu->state.xsave, XSTATE_COPY_FP);
 321                 fx = &fxsave;
 322         } else {
 323                 fx = &fpu->state.fxsave;
 324         }
 325
 326         __convert_from_fxsr(&env, target, fx);
 327         return membuf_write(&to, &env, sizeof(env));
 328 }
 329
 330 int fpregs_set(struct task_struct *target, const struct user_regset *regset,
 331                unsigned int pos, unsigned int count,
 332                const void *kbuf, const void __user *ubuf)
 333 {
 334         struct fpu *fpu = &target->thread.fpu;
 335         struct user_i387_ia32_struct env;
 336         int ret;
 337
 338         /* No funny business with partial or oversized writes is permitted. */
 339         if (pos != 0 || count != sizeof(struct user_i387_ia32_struct))
 340                 return -EINVAL;
 341
 342         if (!cpu_feature_enabled(X86_FEATURE_FPU))
 343                 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
 344
 345         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
 346         if (ret)
 347                 return ret;
 348
 349         fpu__prepare_write(fpu);
 350
 351         if (cpu_feature_enabled(X86_FEATURE_FXSR))
 352                 convert_to_fxsr(&fpu->state.fxsave, &env);
 353         else
 354                 memcpy(&fpu->state.fsave, &env, sizeof(env));
 355
 356         /*
 357          * Update the header bit in the xsave header, indicating the
 358          * presence of FP.
 359          */
 360         if (cpu_feature_enabled(X86_FEATURE_XSAVE))
 361                 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FP;
 362
 363         return 0;
 364 }
 365
 366 #endif  /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */