1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1994 Linus Torvalds
5 * Pentium III FXSR, SSE support
6 * General FPU state handling cleanups
7 * Gareth Hughes <gareth@valinux.com>, May 2000
9 #include <asm/fpu/internal.h>
10 #include <asm/fpu/regset.h>
11 #include <asm/fpu/signal.h>
12 #include <asm/fpu/types.h>
13 #include <asm/traps.h>
14 #include <asm/irq_regs.h>
16 #include <linux/hardirq.h>
17 #include <linux/pkeys.h>
19 #define CREATE_TRACE_POINTS
20 #include <asm/trace/fpu.h>
23 * Represents the initial FPU state. It's mostly (but not completely) zeroes,
24 * depending on the FPU hardware format:
26 union fpregs_state init_fpstate __read_mostly;
29 * Track whether the kernel is using the FPU state
34 * - by IRQ context code to potentially use the FPU
37 * - to debug kernel_fpu_begin()/end() correctness
39 static DEFINE_PER_CPU(bool, in_kernel_fpu);
42 * Track which context is using the FPU on the CPU:
44 DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
46 static bool kernel_fpu_disabled(void)
48 return this_cpu_read(in_kernel_fpu);
51 static bool interrupted_kernel_fpu_idle(void)
53 return !kernel_fpu_disabled();
57 * Were we in user mode (or vm86 mode) when we were
60 * Doing kernel_fpu_begin/end() is ok if we are running
61 * in an interrupt context from user mode - we'll just
62 * save the FPU state as required.
64 static bool interrupted_user_mode(void)
66 struct pt_regs *regs = get_irq_regs();
67 return regs && user_mode(regs);
71 * Can we use the FPU in kernel mode with the
72 * whole "kernel_fpu_begin/end()" sequence?
74 * It's always ok in process context (ie "not interrupt")
75 * but it is sometimes ok even from an irq.
77 bool irq_fpu_usable(void)
79 return !in_interrupt() ||
80 interrupted_user_mode() ||
81 interrupted_kernel_fpu_idle();
83 EXPORT_SYMBOL(irq_fpu_usable);
86 * Save the FPU register state in fpu->state. The register state is
89 * Must be called with fpregs_lock() held.
91 * The legacy FNSAVE instruction clears all FPU state unconditionally, so
92 * register state has to be reloaded. That might be a pointless exercise
93 * when the FPU is going to be used by another task right after that. But
94 * this only affects 20+ years old 32bit systems and avoids conditionals all
97 * FXSAVE and all XSAVE variants preserve the FPU register state.
99 void save_fpregs_to_fpstate(struct fpu *fpu)
101 if (likely(use_xsave())) {
102 os_xsave(&fpu->state.xsave);
105 * AVX512 state is tracked here because its use is
106 * known to slow the max clock speed of the core.
108 if (fpu->state.xsave.header.xfeatures & XFEATURE_MASK_AVX512)
109 fpu->avx512_timestamp = jiffies;
113 if (likely(use_fxsr())) {
114 fxsave(&fpu->state.fxsave);
119 * Legacy FPU register saving, FNSAVE always clears FPU registers,
120 * so we have to reload them from the memory state.
122 asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->state.fsave));
123 frstor(&fpu->state.fsave);
125 EXPORT_SYMBOL(save_fpregs_to_fpstate);
127 void kernel_fpu_begin_mask(unsigned int kfpu_mask)
131 WARN_ON_FPU(!irq_fpu_usable());
132 WARN_ON_FPU(this_cpu_read(in_kernel_fpu));
134 this_cpu_write(in_kernel_fpu, true);
136 if (!(current->flags & PF_KTHREAD) &&
137 !test_thread_flag(TIF_NEED_FPU_LOAD)) {
138 set_thread_flag(TIF_NEED_FPU_LOAD);
139 save_fpregs_to_fpstate(¤t->thread.fpu);
141 __cpu_invalidate_fpregs_state();
143 /* Put sane initial values into the control registers. */
144 if (likely(kfpu_mask & KFPU_MXCSR) && boot_cpu_has(X86_FEATURE_XMM))
145 ldmxcsr(MXCSR_DEFAULT);
147 if (unlikely(kfpu_mask & KFPU_387) && boot_cpu_has(X86_FEATURE_FPU))
148 asm volatile ("fninit");
150 EXPORT_SYMBOL_GPL(kernel_fpu_begin_mask);
152 void kernel_fpu_end(void)
154 WARN_ON_FPU(!this_cpu_read(in_kernel_fpu));
156 this_cpu_write(in_kernel_fpu, false);
159 EXPORT_SYMBOL_GPL(kernel_fpu_end);
162 * Sync the FPU register state to current's memory register state when the
163 * current task owns the FPU. The hardware register state is preserved.
165 void fpu_sync_fpstate(struct fpu *fpu)
167 WARN_ON_FPU(fpu != ¤t->thread.fpu);
170 trace_x86_fpu_before_save(fpu);
172 if (!test_thread_flag(TIF_NEED_FPU_LOAD))
173 save_fpregs_to_fpstate(fpu);
175 trace_x86_fpu_after_save(fpu);
179 static inline void fpstate_init_xstate(struct xregs_state *xsave)
182 * XRSTORS requires these bits set in xcomp_bv, or it will
185 xsave->header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT | xfeatures_mask_all;
188 static inline void fpstate_init_fxstate(struct fxregs_state *fx)
191 fx->mxcsr = MXCSR_DEFAULT;
195 * Legacy x87 fpstate state init:
197 static inline void fpstate_init_fstate(struct fregs_state *fp)
199 fp->cwd = 0xffff037fu;
200 fp->swd = 0xffff0000u;
201 fp->twd = 0xffffffffu;
202 fp->fos = 0xffff0000u;
205 void fpstate_init(union fpregs_state *state)
207 if (!static_cpu_has(X86_FEATURE_FPU)) {
208 fpstate_init_soft(&state->soft);
212 memset(state, 0, fpu_kernel_xstate_size);
214 if (static_cpu_has(X86_FEATURE_XSAVES))
215 fpstate_init_xstate(&state->xsave);
216 if (static_cpu_has(X86_FEATURE_FXSR))
217 fpstate_init_fxstate(&state->fxsave);
219 fpstate_init_fstate(&state->fsave);
221 EXPORT_SYMBOL_GPL(fpstate_init);
223 /* Clone current's FPU state on fork */
224 int fpu_clone(struct task_struct *dst)
226 struct fpu *src_fpu = ¤t->thread.fpu;
227 struct fpu *dst_fpu = &dst->thread.fpu;
229 /* The new task's FPU state cannot be valid in the hardware. */
230 dst_fpu->last_cpu = -1;
232 if (!cpu_feature_enabled(X86_FEATURE_FPU))
236 * Don't let 'init optimized' areas of the XSAVE area
237 * leak into the child task:
239 memset(&dst_fpu->state.xsave, 0, fpu_kernel_xstate_size);
242 * If the FPU registers are not owned by current just memcpy() the
243 * state. Otherwise save the FPU registers directly into the
244 * child's FPU context, without any memory-to-memory copying.
247 if (test_thread_flag(TIF_NEED_FPU_LOAD))
248 memcpy(&dst_fpu->state, &src_fpu->state, fpu_kernel_xstate_size);
251 save_fpregs_to_fpstate(dst_fpu);
254 set_tsk_thread_flag(dst, TIF_NEED_FPU_LOAD);
256 trace_x86_fpu_copy_src(src_fpu);
257 trace_x86_fpu_copy_dst(dst_fpu);
263 * Drops current FPU state: deactivates the fpregs and
264 * the fpstate. NOTE: it still leaves previous contents
265 * in the fpregs in the eager-FPU case.
267 * This function can be used in cases where we know that
268 * a state-restore is coming: either an explicit one,
271 void fpu__drop(struct fpu *fpu)
275 if (fpu == ¤t->thread.fpu) {
276 /* Ignore delayed exceptions from user space */
277 asm volatile("1: fwait\n"
279 _ASM_EXTABLE(1b, 2b));
280 fpregs_deactivate(fpu);
283 trace_x86_fpu_dropped(fpu);
289 * Clear FPU registers by setting them up from the init fpstate.
290 * Caller must do fpregs_[un]lock() around it.
292 static inline void restore_fpregs_from_init_fpstate(u64 features_mask)
295 os_xrstor(&init_fpstate.xsave, features_mask);
297 fxrstor(&init_fpstate.fxsave);
299 frstor(&init_fpstate.fsave);
301 pkru_write_default();
304 static inline unsigned int init_fpstate_copy_size(void)
307 return fpu_kernel_xstate_size;
309 /* XSAVE(S) just needs the legacy and the xstate header part */
310 return sizeof(init_fpstate.xsave);
313 /* Temporary workaround. Will be removed once PKRU and XSTATE are untangled. */
314 static inline void pkru_set_default_in_xstate(struct xregs_state *xsave)
316 struct pkru_state *pk;
318 if (!cpu_feature_enabled(X86_FEATURE_OSPKE))
321 * Force XFEATURE_PKRU to be set in the header otherwise
322 * get_xsave_addr() does not work and it also needs to be set to
323 * make XRSTOR(S) load it.
325 xsave->header.xfeatures |= XFEATURE_MASK_PKRU;
326 pk = get_xsave_addr(xsave, XFEATURE_PKRU);
327 pk->pkru = pkru_get_init_value();
331 * Reset current->fpu memory state to the init values.
333 static void fpu_reset_fpstate(void)
335 struct fpu *fpu = ¤t->thread.fpu;
340 * This does not change the actual hardware registers. It just
341 * resets the memory image and sets TIF_NEED_FPU_LOAD so a
342 * subsequent return to usermode will reload the registers from the
343 * task's memory image.
345 * Do not use fpstate_init() here. Just copy init_fpstate which has
346 * the correct content already except for PKRU.
348 memcpy(&fpu->state, &init_fpstate, init_fpstate_copy_size());
349 pkru_set_default_in_xstate(&fpu->state.xsave);
350 set_thread_flag(TIF_NEED_FPU_LOAD);
355 * Reset current's user FPU states to the init states. current's
356 * supervisor states, if any, are not modified by this function. The
357 * caller guarantees that the XSTATE header in memory is intact.
359 void fpu__clear_user_states(struct fpu *fpu)
361 WARN_ON_FPU(fpu != ¤t->thread.fpu);
364 if (!cpu_feature_enabled(X86_FEATURE_FPU)) {
371 * Ensure that current's supervisor states are loaded into their
372 * corresponding registers.
374 if (xfeatures_mask_supervisor() &&
375 !fpregs_state_valid(fpu, smp_processor_id())) {
376 os_xrstor(&fpu->state.xsave, xfeatures_mask_supervisor());
379 /* Reset user states in registers. */
380 restore_fpregs_from_init_fpstate(xfeatures_mask_user());
383 * Now all FPU registers have their desired values. Inform the FPU
384 * state machine that current's FPU registers are in the hardware
385 * registers. The memory image does not need to be updated because
386 * any operation relying on it has to save the registers first when
387 * current's FPU is marked active.
389 fpregs_mark_activate();
393 void fpu_flush_thread(void)
398 * Load FPU context before returning to userspace.
400 void switch_fpu_return(void)
402 if (!static_cpu_has(X86_FEATURE_FPU))
405 __fpregs_load_activate();
407 EXPORT_SYMBOL_GPL(switch_fpu_return);
409 #ifdef CONFIG_X86_DEBUG_FPU
411 * If current FPU state according to its tracking (loaded FPU context on this
412 * CPU) is not valid then we must have TIF_NEED_FPU_LOAD set so the context is
413 * loaded on return to userland.
415 void fpregs_assert_state_consistent(void)
417 struct fpu *fpu = ¤t->thread.fpu;
419 if (test_thread_flag(TIF_NEED_FPU_LOAD))
422 WARN_ON_FPU(!fpregs_state_valid(fpu, smp_processor_id()));
424 EXPORT_SYMBOL_GPL(fpregs_assert_state_consistent);
427 void fpregs_mark_activate(void)
429 struct fpu *fpu = ¤t->thread.fpu;
431 fpregs_activate(fpu);
432 fpu->last_cpu = smp_processor_id();
433 clear_thread_flag(TIF_NEED_FPU_LOAD);
435 EXPORT_SYMBOL_GPL(fpregs_mark_activate);
438 * x87 math exception handling:
441 int fpu__exception_code(struct fpu *fpu, int trap_nr)
445 if (trap_nr == X86_TRAP_MF) {
446 unsigned short cwd, swd;
448 * (~cwd & swd) will mask out exceptions that are not set to unmasked
449 * status. 0x3f is the exception bits in these regs, 0x200 is the
450 * C1 reg you need in case of a stack fault, 0x040 is the stack
451 * fault bit. We should only be taking one exception at a time,
452 * so if this combination doesn't produce any single exception,
453 * then we have a bad program that isn't synchronizing its FPU usage
454 * and it will suffer the consequences since we won't be able to
455 * fully reproduce the context of the exception.
457 if (boot_cpu_has(X86_FEATURE_FXSR)) {
458 cwd = fpu->state.fxsave.cwd;
459 swd = fpu->state.fxsave.swd;
461 cwd = (unsigned short)fpu->state.fsave.cwd;
462 swd = (unsigned short)fpu->state.fsave.swd;
468 * The SIMD FPU exceptions are handled a little differently, as there
469 * is only a single status/control register. Thus, to determine which
470 * unmasked exception was caught we must mask the exception mask bits
471 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
473 unsigned short mxcsr = MXCSR_DEFAULT;
475 if (boot_cpu_has(X86_FEATURE_XMM))
476 mxcsr = fpu->state.fxsave.mxcsr;
478 err = ~(mxcsr >> 7) & mxcsr;
481 if (err & 0x001) { /* Invalid op */
483 * swd & 0x240 == 0x040: Stack Underflow
484 * swd & 0x240 == 0x240: Stack Overflow
485 * User must clear the SF bit (0x40) if set
488 } else if (err & 0x004) { /* Divide by Zero */
490 } else if (err & 0x008) { /* Overflow */
492 } else if (err & 0x012) { /* Denormal, Underflow */
494 } else if (err & 0x020) { /* Precision */
499 * If we're using IRQ 13, or supposedly even some trap
500 * X86_TRAP_MF implementations, it's possible
501 * we get a spurious trap, which is not an error.