1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Transactional Synchronization Extensions (TSX) control.
5 * Copyright (C) 2019-2021 Intel Corporation
8 * Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
11 #include <linux/cpufeature.h>
13 #include <asm/cmdline.h>
18 #define pr_fmt(fmt) "tsx: " fmt
20 enum tsx_ctrl_states tsx_ctrl_state __ro_after_init = TSX_CTRL_NOT_SUPPORTED;
22 void tsx_disable(void)
26 rdmsrl(MSR_IA32_TSX_CTRL, tsx);
28 /* Force all transactions to immediately abort */
29 tsx |= TSX_CTRL_RTM_DISABLE;
32 * Ensure TSX support is not enumerated in CPUID.
33 * This is visible to userspace and will ensure they
34 * do not waste resources trying TSX transactions that
37 tsx |= TSX_CTRL_CPUID_CLEAR;
39 wrmsrl(MSR_IA32_TSX_CTRL, tsx);
46 rdmsrl(MSR_IA32_TSX_CTRL, tsx);
48 /* Enable the RTM feature in the cpu */
49 tsx &= ~TSX_CTRL_RTM_DISABLE;
52 * Ensure TSX support is enumerated in CPUID.
53 * This is visible to userspace and will ensure they
54 * can enumerate and use the TSX feature.
56 tsx &= ~TSX_CTRL_CPUID_CLEAR;
58 wrmsrl(MSR_IA32_TSX_CTRL, tsx);
61 static bool __init tsx_ctrl_is_supported(void)
63 u64 ia32_cap = x86_read_arch_cap_msr();
66 * TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
67 * MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
69 * TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
70 * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
71 * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
72 * MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
73 * tsx= cmdline requests will do nothing on CPUs without
74 * MSR_IA32_TSX_CTRL support.
76 return !!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR);
79 static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)
81 if (boot_cpu_has_bug(X86_BUG_TAA))
82 return TSX_CTRL_DISABLE;
84 return TSX_CTRL_ENABLE;
87 void tsx_clear_cpuid(void)
92 * MSR_TFA_TSX_CPUID_CLEAR bit is only present when both CPUID
93 * bits RTM_ALWAYS_ABORT and TSX_FORCE_ABORT are present.
95 if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT) &&
96 boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
97 rdmsrl(MSR_TSX_FORCE_ABORT, msr);
98 msr |= MSR_TFA_TSX_CPUID_CLEAR;
99 wrmsrl(MSR_TSX_FORCE_ABORT, msr);
103 void __init tsx_init(void)
109 * Hardware will always abort a TSX transaction if both CPUID bits
110 * RTM_ALWAYS_ABORT and TSX_FORCE_ABORT are set. In this case, it is
111 * better not to enumerate CPUID.RTM and CPUID.HLE bits. Clear them
114 if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT) &&
115 boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
116 tsx_ctrl_state = TSX_CTRL_RTM_ALWAYS_ABORT;
118 setup_clear_cpu_cap(X86_FEATURE_RTM);
119 setup_clear_cpu_cap(X86_FEATURE_HLE);
123 if (!tsx_ctrl_is_supported()) {
124 tsx_ctrl_state = TSX_CTRL_NOT_SUPPORTED;
128 ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));
130 if (!strcmp(arg, "on")) {
131 tsx_ctrl_state = TSX_CTRL_ENABLE;
132 } else if (!strcmp(arg, "off")) {
133 tsx_ctrl_state = TSX_CTRL_DISABLE;
134 } else if (!strcmp(arg, "auto")) {
135 tsx_ctrl_state = x86_get_tsx_auto_mode();
137 tsx_ctrl_state = TSX_CTRL_DISABLE;
138 pr_err("invalid option, defaulting to off\n");
141 /* tsx= not provided */
142 if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_AUTO))
143 tsx_ctrl_state = x86_get_tsx_auto_mode();
144 else if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_OFF))
145 tsx_ctrl_state = TSX_CTRL_DISABLE;
147 tsx_ctrl_state = TSX_CTRL_ENABLE;
150 if (tsx_ctrl_state == TSX_CTRL_DISABLE) {
154 * tsx_disable() will change the state of the RTM and HLE CPUID
155 * bits. Clear them here since they are now expected to be not
158 setup_clear_cpu_cap(X86_FEATURE_RTM);
159 setup_clear_cpu_cap(X86_FEATURE_HLE);
160 } else if (tsx_ctrl_state == TSX_CTRL_ENABLE) {
163 * HW defaults TSX to be enabled at bootup.
164 * We may still need the TSX enable support
165 * during init for special cases like
166 * kexec after TSX is disabled.
171 * tsx_enable() will change the state of the RTM and HLE CPUID
172 * bits. Force them here since they are now expected to be set.
174 setup_force_cpu_cap(X86_FEATURE_RTM);
175 setup_force_cpu_cap(X86_FEATURE_HLE);