arch/x86/kernel/cpu/resctrl/core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Resource Director Technology(RDT)
   4  * - Cache Allocation code.
   5  *
   6  * Copyright (C) 2016 Intel Corporation
   7  *
   8  * Authors:
   9  *    Fenghua Yu <fenghua.yu@intel.com>
  10  *    Tony Luck <tony.luck@intel.com>
  11  *    Vikas Shivappa <vikas.shivappa@intel.com>
  12  *
  13  * More information about RDT be found in the Intel (R) x86 Architecture
  14  * Software Developer Manual June 2016, volume 3, section 17.17.
  15  */
  16
  17 #define pr_fmt(fmt)     "resctrl: " fmt
  18
  19 #include <linux/slab.h>
  20 #include <linux/err.h>
  21 #include <linux/cacheinfo.h>
  22 #include <linux/cpuhotplug.h>
  23
  24 #include <asm/intel-family.h>
  25 #include <asm/resctrl.h>
  26 #include "internal.h"
  27
  28 /* Mutex to protect rdtgroup access. */
  29 DEFINE_MUTEX(rdtgroup_mutex);
  30
  31 /*
  32  * The cached resctrl_pqr_state is strictly per CPU and can never be
  33  * updated from a remote CPU. Functions which modify the state
  34  * are called with interrupts disabled and no preemption, which
  35  * is sufficient for the protection.
  36  */
  37 DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state);
  38
  39 /*
  40  * Used to store the max resource name width and max resource data width
  41  * to display the schemata in a tabular format
  42  */
  43 int max_name_width, max_data_width;
  44
  45 /*
  46  * Global boolean for rdt_alloc which is true if any
  47  * resource allocation is enabled.
  48  */
  49 bool rdt_alloc_capable;
  50
  51 static void
  52 mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m,
  53                 struct rdt_resource *r);
  54 static void
  55 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r);
  56 static void
  57 mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m,
  58               struct rdt_resource *r);
  59
  60 #define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.domains)
  61
  62 struct rdt_hw_resource rdt_resources_all[] = {
  63         [RDT_RESOURCE_L3] =
  64         {
  65                 .conf_type                      = CDP_NONE,
  66                 .r_resctrl = {
  67                         .rid                    = RDT_RESOURCE_L3,
  68                         .name                   = "L3",
  69                         .cache_level            = 3,
  70                         .cache = {
  71                                 .min_cbm_bits   = 1,
  72                                 .cbm_idx_mult   = 1,
  73                                 .cbm_idx_offset = 0,
  74                         },
  75                         .domains                = domain_init(RDT_RESOURCE_L3),
  76                         .parse_ctrlval          = parse_cbm,
  77                         .format_str             = "%d=%0*x",
  78                         .fflags                 = RFTYPE_RES_CACHE,
  79                 },
  80                 .msr_base               = MSR_IA32_L3_CBM_BASE,
  81                 .msr_update             = cat_wrmsr,
  82         },
  83         [RDT_RESOURCE_L3DATA] =
  84         {
  85                 .conf_type                      = CDP_DATA,
  86                 .r_resctrl = {
  87                         .rid                    = RDT_RESOURCE_L3DATA,
  88                         .name                   = "L3DATA",
  89                         .cache_level            = 3,
  90                         .cache = {
  91                                 .min_cbm_bits   = 1,
  92                                 .cbm_idx_mult   = 2,
  93                                 .cbm_idx_offset = 0,
  94                         },
  95                         .domains                = domain_init(RDT_RESOURCE_L3DATA),
  96                         .parse_ctrlval          = parse_cbm,
  97                         .format_str             = "%d=%0*x",
  98                         .fflags                 = RFTYPE_RES_CACHE,
  99                 },
 100                 .msr_base               = MSR_IA32_L3_CBM_BASE,
 101                 .msr_update             = cat_wrmsr,
 102         },
 103         [RDT_RESOURCE_L3CODE] =
 104         {
 105                 .conf_type                      = CDP_CODE,
 106                 .r_resctrl = {
 107                         .rid                    = RDT_RESOURCE_L3CODE,
 108                         .name                   = "L3CODE",
 109                         .cache_level            = 3,
 110                         .cache = {
 111                                 .min_cbm_bits   = 1,
 112                                 .cbm_idx_mult   = 2,
 113                                 .cbm_idx_offset = 1,
 114                         },
 115                         .domains                = domain_init(RDT_RESOURCE_L3CODE),
 116                         .parse_ctrlval          = parse_cbm,
 117                         .format_str             = "%d=%0*x",
 118                         .fflags                 = RFTYPE_RES_CACHE,
 119                 },
 120                 .msr_base               = MSR_IA32_L3_CBM_BASE,
 121                 .msr_update             = cat_wrmsr,
 122         },
 123         [RDT_RESOURCE_L2] =
 124         {
 125                 .conf_type                      = CDP_NONE,
 126                 .r_resctrl = {
 127                         .rid                    = RDT_RESOURCE_L2,
 128                         .name                   = "L2",
 129                         .cache_level            = 2,
 130                         .cache = {
 131                                 .min_cbm_bits   = 1,
 132                                 .cbm_idx_mult   = 1,
 133                                 .cbm_idx_offset = 0,
 134                         },
 135                         .domains                = domain_init(RDT_RESOURCE_L2),
 136                         .parse_ctrlval          = parse_cbm,
 137                         .format_str             = "%d=%0*x",
 138                         .fflags                 = RFTYPE_RES_CACHE,
 139                 },
 140                 .msr_base               = MSR_IA32_L2_CBM_BASE,
 141                 .msr_update             = cat_wrmsr,
 142         },
 143         [RDT_RESOURCE_L2DATA] =
 144         {
 145                 .conf_type                      = CDP_DATA,
 146                 .r_resctrl = {
 147                         .rid                    = RDT_RESOURCE_L2DATA,
 148                         .name                   = "L2DATA",
 149                         .cache_level            = 2,
 150                         .cache = {
 151                                 .min_cbm_bits   = 1,
 152                                 .cbm_idx_mult   = 2,
 153                                 .cbm_idx_offset = 0,
 154                         },
 155                         .domains                = domain_init(RDT_RESOURCE_L2DATA),
 156                         .parse_ctrlval          = parse_cbm,
 157                         .format_str             = "%d=%0*x",
 158                         .fflags                 = RFTYPE_RES_CACHE,
 159                 },
 160                 .msr_base               = MSR_IA32_L2_CBM_BASE,
 161                 .msr_update             = cat_wrmsr,
 162         },
 163         [RDT_RESOURCE_L2CODE] =
 164         {
 165                 .conf_type                      = CDP_CODE,
 166                 .r_resctrl = {
 167                         .rid                    = RDT_RESOURCE_L2CODE,
 168                         .name                   = "L2CODE",
 169                         .cache_level            = 2,
 170                         .cache = {
 171                                 .min_cbm_bits   = 1,
 172                                 .cbm_idx_mult   = 2,
 173                                 .cbm_idx_offset = 1,
 174                         },
 175                         .domains                = domain_init(RDT_RESOURCE_L2CODE),
 176                         .parse_ctrlval          = parse_cbm,
 177                         .format_str             = "%d=%0*x",
 178                         .fflags                 = RFTYPE_RES_CACHE,
 179                 },
 180                 .msr_base               = MSR_IA32_L2_CBM_BASE,
 181                 .msr_update             = cat_wrmsr,
 182         },
 183         [RDT_RESOURCE_MBA] =
 184         {
 185                 .conf_type                      = CDP_NONE,
 186                 .r_resctrl = {
 187                         .rid                    = RDT_RESOURCE_MBA,
 188                         .name                   = "MB",
 189                         .cache_level            = 3,
 190                         .domains                = domain_init(RDT_RESOURCE_MBA),
 191                         .parse_ctrlval          = parse_bw,
 192                         .format_str             = "%d=%*u",
 193                         .fflags                 = RFTYPE_RES_MB,
 194                 },
 195         },
 196 };
 197
 198 static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid)
 199 {
 200         return closid * r->cache.cbm_idx_mult + r->cache.cbm_idx_offset;
 201 }
 202
 203 /*
 204  * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
 205  * as they do not have CPUID enumeration support for Cache allocation.
 206  * The check for Vendor/Family/Model is not enough to guarantee that
 207  * the MSRs won't #GP fault because only the following SKUs support
 208  * CAT:
 209  *      Intel(R) Xeon(R)  CPU E5-2658  v3  @  2.20GHz
 210  *      Intel(R) Xeon(R)  CPU E5-2648L v3  @  1.80GHz
 211  *      Intel(R) Xeon(R)  CPU E5-2628L v3  @  2.00GHz
 212  *      Intel(R) Xeon(R)  CPU E5-2618L v3  @  2.30GHz
 213  *      Intel(R) Xeon(R)  CPU E5-2608L v3  @  2.00GHz
 214  *      Intel(R) Xeon(R)  CPU E5-2658A v3  @  2.20GHz
 215  *
 216  * Probe by trying to write the first of the L3 cache mask registers
 217  * and checking that the bits stick. Max CLOSids is always 4 and max cbm length
 218  * is always 20 on hsw server parts. The minimum cache bitmask length
 219  * allowed for HSW server is always 2 bits. Hardcode all of them.
 220  */
 221 static inline void cache_alloc_hsw_probe(void)
 222 {
 223         struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3];
 224         struct rdt_resource *r  = &hw_res->r_resctrl;
 225         u32 l, h, max_cbm = BIT_MASK(20) - 1;
 226
 227         if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))
 228                 return;
 229
 230         rdmsr(MSR_IA32_L3_CBM_BASE, l, h);
 231
 232         /* If all the bits were set in MSR, return success */
 233         if (l != max_cbm)
 234                 return;
 235
 236         hw_res->num_closid = 4;
 237         r->default_ctrl = max_cbm;
 238         r->cache.cbm_len = 20;
 239         r->cache.shareable_bits = 0xc0000;
 240         r->cache.min_cbm_bits = 2;
 241         r->alloc_capable = true;
 242         r->alloc_enabled = true;
 243
 244         rdt_alloc_capable = true;
 245 }
 246
 247 bool is_mba_sc(struct rdt_resource *r)
 248 {
 249         if (!r)
 250                 return rdt_resources_all[RDT_RESOURCE_MBA].r_resctrl.membw.mba_sc;
 251
 252         return r->membw.mba_sc;
 253 }
 254
 255 /*
 256  * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values
 257  * exposed to user interface and the h/w understandable delay values.
 258  *
 259  * The non-linear delay values have the granularity of power of two
 260  * and also the h/w does not guarantee a curve for configured delay
 261  * values vs. actual b/w enforced.
 262  * Hence we need a mapping that is pre calibrated so the user can
 263  * express the memory b/w as a percentage value.
 264  */
 265 static inline bool rdt_get_mb_table(struct rdt_resource *r)
 266 {
 267         /*
 268          * There are no Intel SKUs as of now to support non-linear delay.
 269          */
 270         pr_info("MBA b/w map not implemented for cpu:%d, model:%d",
 271                 boot_cpu_data.x86, boot_cpu_data.x86_model);
 272
 273         return false;
 274 }
 275
 276 static bool __get_mem_config_intel(struct rdt_resource *r)
 277 {
 278         struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
 279         union cpuid_0x10_3_eax eax;
 280         union cpuid_0x10_x_edx edx;
 281         u32 ebx, ecx, max_delay;
 282
 283         cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full);
 284         hw_res->num_closid = edx.split.cos_max + 1;
 285         max_delay = eax.split.max_delay + 1;
 286         r->default_ctrl = MAX_MBA_BW;
 287         r->membw.arch_needs_linear = true;
 288         if (ecx & MBA_IS_LINEAR) {
 289                 r->membw.delay_linear = true;
 290                 r->membw.min_bw = MAX_MBA_BW - max_delay;
 291                 r->membw.bw_gran = MAX_MBA_BW - max_delay;
 292         } else {
 293                 if (!rdt_get_mb_table(r))
 294                         return false;
 295                 r->membw.arch_needs_linear = false;
 296         }
 297         r->data_width = 3;
 298
 299         if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA))
 300                 r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD;
 301         else
 302                 r->membw.throttle_mode = THREAD_THROTTLE_MAX;
 303         thread_throttle_mode_init();
 304
 305         r->alloc_capable = true;
 306         r->alloc_enabled = true;
 307
 308         return true;
 309 }
 310
 311 static bool __rdt_get_mem_config_amd(struct rdt_resource *r)
 312 {
 313         struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
 314         union cpuid_0x10_3_eax eax;
 315         union cpuid_0x10_x_edx edx;
 316         u32 ebx, ecx;
 317
 318         cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full);
 319         hw_res->num_closid = edx.split.cos_max + 1;
 320         r->default_ctrl = MAX_MBA_BW_AMD;
 321
 322         /* AMD does not use delay */
 323         r->membw.delay_linear = false;
 324         r->membw.arch_needs_linear = false;
 325
 326         /*
 327          * AMD does not use memory delay throttle model to control
 328          * the allocation like Intel does.
 329          */
 330         r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED;
 331         r->membw.min_bw = 0;
 332         r->membw.bw_gran = 1;
 333         /* Max value is 2048, Data width should be 4 in decimal */
 334         r->data_width = 4;
 335
 336         r->alloc_capable = true;
 337         r->alloc_enabled = true;
 338
 339         return true;
 340 }
 341
 342 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r)
 343 {
 344         struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
 345         union cpuid_0x10_1_eax eax;
 346         union cpuid_0x10_x_edx edx;
 347         u32 ebx, ecx;
 348
 349         cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);
 350         hw_res->num_closid = edx.split.cos_max + 1;
 351         r->cache.cbm_len = eax.split.cbm_len + 1;
 352         r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;
 353         r->cache.shareable_bits = ebx & r->default_ctrl;
 354         r->data_width = (r->cache.cbm_len + 3) / 4;
 355         r->alloc_capable = true;
 356         r->alloc_enabled = true;
 357 }
 358
 359 static void rdt_get_cdp_config(int level, int type)
 360 {
 361         struct rdt_resource *r_l = &rdt_resources_all[level].r_resctrl;
 362         struct rdt_hw_resource *hw_res_l = resctrl_to_arch_res(r_l);
 363         struct rdt_resource *r = &rdt_resources_all[type].r_resctrl;
 364         struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
 365
 366         hw_res->num_closid = hw_res_l->num_closid / 2;
 367         r->cache.cbm_len = r_l->cache.cbm_len;
 368         r->default_ctrl = r_l->default_ctrl;
 369         r->cache.shareable_bits = r_l->cache.shareable_bits;
 370         r->data_width = (r->cache.cbm_len + 3) / 4;
 371         r->alloc_capable = true;
 372         /*
 373          * By default, CDP is disabled. CDP can be enabled by mount parameter
 374          * "cdp" during resctrl file system mount time.
 375          */
 376         r->alloc_enabled = false;
 377         rdt_resources_all[level].cdp_enabled = false;
 378         rdt_resources_all[type].cdp_enabled = false;
 379         r_l->cdp_capable = true;
 380         r->cdp_capable = true;
 381 }
 382
 383 static void rdt_get_cdp_l3_config(void)
 384 {
 385         rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3DATA);
 386         rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3CODE);
 387 }
 388
 389 static void rdt_get_cdp_l2_config(void)
 390 {
 391         rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2DATA);
 392         rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2CODE);
 393 }
 394
 395 static void
 396 mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
 397 {
 398         unsigned int i;
 399         struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d);
 400         struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
 401
 402         for (i = m->low; i < m->high; i++)
 403                 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]);
 404 }
 405
 406 /*
 407  * Map the memory b/w percentage value to delay values
 408  * that can be written to QOS_MSRs.
 409  * There are currently no SKUs which support non linear delay values.
 410  */
 411 u32 delay_bw_map(unsigned long bw, struct rdt_resource *r)
 412 {
 413         if (r->membw.delay_linear)
 414                 return MAX_MBA_BW - bw;
 415
 416         pr_warn_once("Non Linear delay-bw map not supported but queried\n");
 417         return r->default_ctrl;
 418 }
 419
 420 static void
 421 mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m,
 422                 struct rdt_resource *r)
 423 {
 424         unsigned int i;
 425         struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d);
 426         struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
 427
 428         /*  Write the delay values for mba. */
 429         for (i = m->low; i < m->high; i++)
 430                 wrmsrl(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], r));
 431 }
 432
 433 static void
 434 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
 435 {
 436         unsigned int i;
 437         struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d);
 438         struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
 439
 440         for (i = m->low; i < m->high; i++)
 441                 wrmsrl(hw_res->msr_base + cbm_idx(r, i), hw_dom->ctrl_val[i]);
 442 }
 443
 444 struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r)
 445 {
 446         struct rdt_domain *d;
 447
 448         list_for_each_entry(d, &r->domains, list) {
 449                 /* Find the domain that contains this CPU */
 450                 if (cpumask_test_cpu(cpu, &d->cpu_mask))
 451                         return d;
 452         }
 453
 454         return NULL;
 455 }
 456
 457 u32 resctrl_arch_get_num_closid(struct rdt_resource *r)
 458 {
 459         return resctrl_to_arch_res(r)->num_closid;
 460 }
 461
 462 void rdt_ctrl_update(void *arg)
 463 {
 464         struct msr_param *m = arg;
 465         struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res);
 466         struct rdt_resource *r = m->res;
 467         int cpu = smp_processor_id();
 468         struct rdt_domain *d;
 469
 470         d = get_domain_from_cpu(cpu, r);
 471         if (d) {
 472                 hw_res->msr_update(d, m, r);
 473                 return;
 474         }
 475         pr_warn_once("cpu %d not found in any domain for resource %s\n",
 476                      cpu, r->name);
 477 }
 478
 479 /*
 480  * rdt_find_domain - Find a domain in a resource that matches input resource id
 481  *
 482  * Search resource r's domain list to find the resource id. If the resource
 483  * id is found in a domain, return the domain. Otherwise, if requested by
 484  * caller, return the first domain whose id is bigger than the input id.
 485  * The domain list is sorted by id in ascending order.
 486  */
 487 struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id,
 488                                    struct list_head **pos)
 489 {
 490         struct rdt_domain *d;
 491         struct list_head *l;
 492
 493         if (id < 0)
 494                 return ERR_PTR(-ENODEV);
 495
 496         list_for_each(l, &r->domains) {
 497                 d = list_entry(l, struct rdt_domain, list);
 498                 /* When id is found, return its domain. */
 499                 if (id == d->id)
 500                         return d;
 501                 /* Stop searching when finding id's position in sorted list. */
 502                 if (id < d->id)
 503                         break;
 504         }
 505
 506         if (pos)
 507                 *pos = l;
 508
 509         return NULL;
 510 }
 511
 512 void setup_default_ctrlval(struct rdt_resource *r, u32 *dc, u32 *dm)
 513 {
 514         struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
 515         int i;
 516
 517         /*
 518          * Initialize the Control MSRs to having no control.
 519          * For Cache Allocation: Set all bits in cbm
 520          * For Memory Allocation: Set b/w requested to 100%
 521          * and the bandwidth in MBps to U32_MAX
 522          */
 523         for (i = 0; i < hw_res->num_closid; i++, dc++, dm++) {
 524                 *dc = r->default_ctrl;
 525                 *dm = MBA_MAX_MBPS;
 526         }
 527 }
 528
 529 static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d)
 530 {
 531         struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
 532         struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d);
 533         struct msr_param m;
 534         u32 *dc, *dm;
 535
 536         dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val), GFP_KERNEL);
 537         if (!dc)
 538                 return -ENOMEM;
 539
 540         dm = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->mbps_val), GFP_KERNEL);
 541         if (!dm) {
 542                 kfree(dc);
 543                 return -ENOMEM;
 544         }
 545
 546         hw_dom->ctrl_val = dc;
 547         hw_dom->mbps_val = dm;
 548         setup_default_ctrlval(r, dc, dm);
 549
 550         m.low = 0;
 551         m.high = hw_res->num_closid;
 552         hw_res->msr_update(d, &m, r);
 553         return 0;
 554 }
 555
 556 static int domain_setup_mon_state(struct rdt_resource *r, struct rdt_domain *d)
 557 {
 558         size_t tsize;
 559
 560         if (is_llc_occupancy_enabled()) {
 561                 d->rmid_busy_llc = bitmap_zalloc(r->num_rmid, GFP_KERNEL);
 562                 if (!d->rmid_busy_llc)
 563                         return -ENOMEM;
 564                 INIT_DELAYED_WORK(&d->cqm_limbo, cqm_handle_limbo);
 565         }
 566         if (is_mbm_total_enabled()) {
 567                 tsize = sizeof(*d->mbm_total);
 568                 d->mbm_total = kcalloc(r->num_rmid, tsize, GFP_KERNEL);
 569                 if (!d->mbm_total) {
 570                         bitmap_free(d->rmid_busy_llc);
 571                         return -ENOMEM;
 572                 }
 573         }
 574         if (is_mbm_local_enabled()) {
 575                 tsize = sizeof(*d->mbm_local);
 576                 d->mbm_local = kcalloc(r->num_rmid, tsize, GFP_KERNEL);
 577                 if (!d->mbm_local) {
 578                         bitmap_free(d->rmid_busy_llc);
 579                         kfree(d->mbm_total);
 580                         return -ENOMEM;
 581                 }
 582         }
 583
 584         if (is_mbm_enabled()) {
 585                 INIT_DELAYED_WORK(&d->mbm_over, mbm_handle_overflow);
 586                 mbm_setup_overflow_handler(d, MBM_OVERFLOW_INTERVAL);
 587         }
 588
 589         return 0;
 590 }
 591
 592 /*
 593  * domain_add_cpu - Add a cpu to a resource's domain list.
 594  *
 595  * If an existing domain in the resource r's domain list matches the cpu's
 596  * resource id, add the cpu in the domain.
 597  *
 598  * Otherwise, a new domain is allocated and inserted into the right position
 599  * in the domain list sorted by id in ascending order.
 600  *
 601  * The order in the domain list is visible to users when we print entries
 602  * in the schemata file and schemata input is validated to have the same order
 603  * as this list.
 604  */
 605 static void domain_add_cpu(int cpu, struct rdt_resource *r)
 606 {
 607         int id = get_cpu_cacheinfo_id(cpu, r->cache_level);
 608         struct list_head *add_pos = NULL;
 609         struct rdt_hw_domain *hw_dom;
 610         struct rdt_domain *d;
 611
 612         d = rdt_find_domain(r, id, &add_pos);
 613         if (IS_ERR(d)) {
 614                 pr_warn("Couldn't find cache id for CPU %d\n", cpu);
 615                 return;
 616         }
 617
 618         if (d) {
 619                 cpumask_set_cpu(cpu, &d->cpu_mask);
 620                 if (r->cache.arch_has_per_cpu_cfg)
 621                         rdt_domain_reconfigure_cdp(r);
 622                 return;
 623         }
 624
 625         hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu));
 626         if (!hw_dom)
 627                 return;
 628
 629         d = &hw_dom->d_resctrl;
 630         d->id = id;
 631         cpumask_set_cpu(cpu, &d->cpu_mask);
 632
 633         rdt_domain_reconfigure_cdp(r);
 634
 635         if (r->alloc_capable && domain_setup_ctrlval(r, d)) {
 636                 kfree(d);
 637                 return;
 638         }
 639
 640         if (r->mon_capable && domain_setup_mon_state(r, d)) {
 641                 kfree(d);
 642                 return;
 643         }
 644
 645         list_add_tail(&d->list, add_pos);
 646
 647         /*
 648          * If resctrl is mounted, add
 649          * per domain monitor data directories.
 650          */
 651         if (static_branch_unlikely(&rdt_mon_enable_key))
 652                 mkdir_mondata_subdir_allrdtgrp(r, d);
 653 }
 654
 655 static void domain_remove_cpu(int cpu, struct rdt_resource *r)
 656 {
 657         int id = get_cpu_cacheinfo_id(cpu, r->cache_level);
 658         struct rdt_hw_domain *hw_dom;
 659         struct rdt_domain *d;
 660
 661         d = rdt_find_domain(r, id, NULL);
 662         if (IS_ERR_OR_NULL(d)) {
 663                 pr_warn("Couldn't find cache id for CPU %d\n", cpu);
 664                 return;
 665         }
 666         hw_dom = resctrl_to_arch_dom(d);
 667
 668         cpumask_clear_cpu(cpu, &d->cpu_mask);
 669         if (cpumask_empty(&d->cpu_mask)) {
 670                 /*
 671                  * If resctrl is mounted, remove all the
 672                  * per domain monitor data directories.
 673                  */
 674                 if (static_branch_unlikely(&rdt_mon_enable_key))
 675                         rmdir_mondata_subdir_allrdtgrp(r, d->id);
 676                 list_del(&d->list);
 677                 if (r->mon_capable && is_mbm_enabled())
 678                         cancel_delayed_work(&d->mbm_over);
 679                 if (is_llc_occupancy_enabled() &&  has_busy_rmid(r, d)) {
 680                         /*
 681                          * When a package is going down, forcefully
 682                          * decrement rmid->ebusy. There is no way to know
 683                          * that the L3 was flushed and hence may lead to
 684                          * incorrect counts in rare scenarios, but leaving
 685                          * the RMID as busy creates RMID leaks if the
 686                          * package never comes back.
 687                          */
 688                         __check_limbo(d, true);
 689                         cancel_delayed_work(&d->cqm_limbo);
 690                 }
 691
 692                 /*
 693                  * rdt_domain "d" is going to be freed below, so clear
 694                  * its pointer from pseudo_lock_region struct.
 695                  */
 696                 if (d->plr)
 697                         d->plr->d = NULL;
 698
 699                 kfree(hw_dom->ctrl_val);
 700                 kfree(hw_dom->mbps_val);
 701                 bitmap_free(d->rmid_busy_llc);
 702                 kfree(d->mbm_total);
 703                 kfree(d->mbm_local);
 704                 kfree(hw_dom);
 705                 return;
 706         }
 707
 708         if (r == &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl) {
 709                 if (is_mbm_enabled() && cpu == d->mbm_work_cpu) {
 710                         cancel_delayed_work(&d->mbm_over);
 711                         mbm_setup_overflow_handler(d, 0);
 712                 }
 713                 if (is_llc_occupancy_enabled() && cpu == d->cqm_work_cpu &&
 714                     has_busy_rmid(r, d)) {
 715                         cancel_delayed_work(&d->cqm_limbo);
 716                         cqm_setup_limbo_handler(d, 0);
 717                 }
 718         }
 719 }
 720
 721 static void clear_closid_rmid(int cpu)
 722 {
 723         struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state);
 724
 725         state->default_closid = 0;
 726         state->default_rmid = 0;
 727         state->cur_closid = 0;
 728         state->cur_rmid = 0;
 729         wrmsr(IA32_PQR_ASSOC, 0, 0);
 730 }
 731
 732 static int resctrl_online_cpu(unsigned int cpu)
 733 {
 734         struct rdt_resource *r;
 735
 736         mutex_lock(&rdtgroup_mutex);
 737         for_each_capable_rdt_resource(r)
 738                 domain_add_cpu(cpu, r);
 739         /* The cpu is set in default rdtgroup after online. */
 740         cpumask_set_cpu(cpu, &rdtgroup_default.cpu_mask);
 741         clear_closid_rmid(cpu);
 742         mutex_unlock(&rdtgroup_mutex);
 743
 744         return 0;
 745 }
 746
 747 static void clear_childcpus(struct rdtgroup *r, unsigned int cpu)
 748 {
 749         struct rdtgroup *cr;
 750
 751         list_for_each_entry(cr, &r->mon.crdtgrp_list, mon.crdtgrp_list) {
 752                 if (cpumask_test_and_clear_cpu(cpu, &cr->cpu_mask)) {
 753                         break;
 754                 }
 755         }
 756 }
 757
 758 static int resctrl_offline_cpu(unsigned int cpu)
 759 {
 760         struct rdtgroup *rdtgrp;
 761         struct rdt_resource *r;
 762
 763         mutex_lock(&rdtgroup_mutex);
 764         for_each_capable_rdt_resource(r)
 765                 domain_remove_cpu(cpu, r);
 766         list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) {
 767                 if (cpumask_test_and_clear_cpu(cpu, &rdtgrp->cpu_mask)) {
 768                         clear_childcpus(rdtgrp, cpu);
 769                         break;
 770                 }
 771         }
 772         clear_closid_rmid(cpu);
 773         mutex_unlock(&rdtgroup_mutex);
 774
 775         return 0;
 776 }
 777
 778 /*
 779  * Choose a width for the resource name and resource data based on the
 780  * resource that has widest name and cbm.
 781  */
 782 static __init void rdt_init_padding(void)
 783 {
 784         struct rdt_resource *r;
 785         int cl;
 786
 787         for_each_alloc_capable_rdt_resource(r) {
 788                 cl = strlen(r->name);
 789                 if (cl > max_name_width)
 790                         max_name_width = cl;
 791
 792                 if (r->data_width > max_data_width)
 793                         max_data_width = r->data_width;
 794         }
 795 }
 796
 797 enum {
 798         RDT_FLAG_CMT,
 799         RDT_FLAG_MBM_TOTAL,
 800         RDT_FLAG_MBM_LOCAL,
 801         RDT_FLAG_L3_CAT,
 802         RDT_FLAG_L3_CDP,
 803         RDT_FLAG_L2_CAT,
 804         RDT_FLAG_L2_CDP,
 805         RDT_FLAG_MBA,
 806 };
 807
 808 #define RDT_OPT(idx, n, f)      \
 809 [idx] = {                       \
 810         .name = n,              \
 811         .flag = f               \
 812 }
 813
 814 struct rdt_options {
 815         char    *name;
 816         int     flag;
 817         bool    force_off, force_on;
 818 };
 819
 820 static struct rdt_options rdt_options[]  __initdata = {
 821         RDT_OPT(RDT_FLAG_CMT,       "cmt",      X86_FEATURE_CQM_OCCUP_LLC),
 822         RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL),
 823         RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL),
 824         RDT_OPT(RDT_FLAG_L3_CAT,    "l3cat",    X86_FEATURE_CAT_L3),
 825         RDT_OPT(RDT_FLAG_L3_CDP,    "l3cdp",    X86_FEATURE_CDP_L3),
 826         RDT_OPT(RDT_FLAG_L2_CAT,    "l2cat",    X86_FEATURE_CAT_L2),
 827         RDT_OPT(RDT_FLAG_L2_CDP,    "l2cdp",    X86_FEATURE_CDP_L2),
 828         RDT_OPT(RDT_FLAG_MBA,       "mba",      X86_FEATURE_MBA),
 829 };
 830 #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options)
 831
 832 static int __init set_rdt_options(char *str)
 833 {
 834         struct rdt_options *o;
 835         bool force_off;
 836         char *tok;
 837
 838         if (*str == '=')
 839                 str++;
 840         while ((tok = strsep(&str, ",")) != NULL) {
 841                 force_off = *tok == '!';
 842                 if (force_off)
 843                         tok++;
 844                 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
 845                         if (strcmp(tok, o->name) == 0) {
 846                                 if (force_off)
 847                                         o->force_off = true;
 848                                 else
 849                                         o->force_on = true;
 850                                 break;
 851                         }
 852                 }
 853         }
 854         return 1;
 855 }
 856 __setup("rdt", set_rdt_options);
 857
 858 static bool __init rdt_cpu_has(int flag)
 859 {
 860         bool ret = boot_cpu_has(flag);
 861         struct rdt_options *o;
 862
 863         if (!ret)
 864                 return ret;
 865
 866         for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
 867                 if (flag == o->flag) {
 868                         if (o->force_off)
 869                                 ret = false;
 870                         if (o->force_on)
 871                                 ret = true;
 872                         break;
 873                 }
 874         }
 875         return ret;
 876 }
 877
 878 static __init bool get_mem_config(void)
 879 {
 880         struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_MBA];
 881
 882         if (!rdt_cpu_has(X86_FEATURE_MBA))
 883                 return false;
 884
 885         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
 886                 return __get_mem_config_intel(&hw_res->r_resctrl);
 887         else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
 888                 return __rdt_get_mem_config_amd(&hw_res->r_resctrl);
 889
 890         return false;
 891 }
 892
 893 static __init bool get_rdt_alloc_resources(void)
 894 {
 895         struct rdt_resource *r;
 896         bool ret = false;
 897
 898         if (rdt_alloc_capable)
 899                 return true;
 900
 901         if (!boot_cpu_has(X86_FEATURE_RDT_A))
 902                 return false;
 903
 904         if (rdt_cpu_has(X86_FEATURE_CAT_L3)) {
 905                 r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
 906                 rdt_get_cache_alloc_cfg(1, r);
 907                 if (rdt_cpu_has(X86_FEATURE_CDP_L3))
 908                         rdt_get_cdp_l3_config();
 909                 ret = true;
 910         }
 911         if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {
 912                 /* CPUID 0x10.2 fields are same format at 0x10.1 */
 913                 r = &rdt_resources_all[RDT_RESOURCE_L2].r_resctrl;
 914                 rdt_get_cache_alloc_cfg(2, r);
 915                 if (rdt_cpu_has(X86_FEATURE_CDP_L2))
 916                         rdt_get_cdp_l2_config();
 917                 ret = true;
 918         }
 919
 920         if (get_mem_config())
 921                 ret = true;
 922
 923         return ret;
 924 }
 925
 926 static __init bool get_rdt_mon_resources(void)
 927 {
 928         struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
 929
 930         if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC))
 931                 rdt_mon_features |= (1 << QOS_L3_OCCUP_EVENT_ID);
 932         if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL))
 933                 rdt_mon_features |= (1 << QOS_L3_MBM_TOTAL_EVENT_ID);
 934         if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL))
 935                 rdt_mon_features |= (1 << QOS_L3_MBM_LOCAL_EVENT_ID);
 936
 937         if (!rdt_mon_features)
 938                 return false;
 939
 940         return !rdt_get_mon_l3_config(r);
 941 }
 942
 943 static __init void __check_quirks_intel(void)
 944 {
 945         switch (boot_cpu_data.x86_model) {
 946         case INTEL_FAM6_HASWELL_X:
 947                 if (!rdt_options[RDT_FLAG_L3_CAT].force_off)
 948                         cache_alloc_hsw_probe();
 949                 break;
 950         case INTEL_FAM6_SKYLAKE_X:
 951                 if (boot_cpu_data.x86_stepping <= 4)
 952                         set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");
 953                 else
 954                         set_rdt_options("!l3cat");
 955                 fallthrough;
 956         case INTEL_FAM6_BROADWELL_X:
 957                 intel_rdt_mbm_apply_quirk();
 958                 break;
 959         }
 960 }
 961
 962 static __init void check_quirks(void)
 963 {
 964         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
 965                 __check_quirks_intel();
 966 }
 967
 968 static __init bool get_rdt_resources(void)
 969 {
 970         rdt_alloc_capable = get_rdt_alloc_resources();
 971         rdt_mon_capable = get_rdt_mon_resources();
 972
 973         return (rdt_mon_capable || rdt_alloc_capable);
 974 }
 975
 976 static __init void rdt_init_res_defs_intel(void)
 977 {
 978         struct rdt_hw_resource *hw_res;
 979         struct rdt_resource *r;
 980
 981         for_each_rdt_resource(r) {
 982                 hw_res = resctrl_to_arch_res(r);
 983
 984                 if (r->rid == RDT_RESOURCE_L3 ||
 985                     r->rid == RDT_RESOURCE_L3DATA ||
 986                     r->rid == RDT_RESOURCE_L3CODE ||
 987                     r->rid == RDT_RESOURCE_L2 ||
 988                     r->rid == RDT_RESOURCE_L2DATA ||
 989                     r->rid == RDT_RESOURCE_L2CODE) {
 990                         r->cache.arch_has_sparse_bitmaps = false;
 991                         r->cache.arch_has_empty_bitmaps = false;
 992                         r->cache.arch_has_per_cpu_cfg = false;
 993                 } else if (r->rid == RDT_RESOURCE_MBA) {
 994                         hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE;
 995                         hw_res->msr_update = mba_wrmsr_intel;
 996                 }
 997         }
 998 }
 999
1000 static __init void rdt_init_res_defs_amd(void)
1001 {
1002         struct rdt_hw_resource *hw_res;
1003         struct rdt_resource *r;
1004
1005         for_each_rdt_resource(r) {
1006                 hw_res = resctrl_to_arch_res(r);
1007
1008                 if (r->rid == RDT_RESOURCE_L3 ||
1009                     r->rid == RDT_RESOURCE_L3DATA ||
1010                     r->rid == RDT_RESOURCE_L3CODE ||
1011                     r->rid == RDT_RESOURCE_L2 ||
1012                     r->rid == RDT_RESOURCE_L2DATA ||
1013                     r->rid == RDT_RESOURCE_L2CODE) {
1014                         r->cache.arch_has_sparse_bitmaps = true;
1015                         r->cache.arch_has_empty_bitmaps = true;
1016                         r->cache.arch_has_per_cpu_cfg = true;
1017                 } else if (r->rid == RDT_RESOURCE_MBA) {
1018                         hw_res->msr_base = MSR_IA32_MBA_BW_BASE;
1019                         hw_res->msr_update = mba_wrmsr_amd;
1020                 }
1021         }
1022 }
1023
1024 static __init void rdt_init_res_defs(void)
1025 {
1026         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1027                 rdt_init_res_defs_intel();
1028         else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1029                 rdt_init_res_defs_amd();
1030 }
1031
1032 static enum cpuhp_state rdt_online;
1033
1034 /* Runs once on the BSP during boot. */
1035 void resctrl_cpu_detect(struct cpuinfo_x86 *c)
1036 {
1037         if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
1038                 c->x86_cache_max_rmid  = -1;
1039                 c->x86_cache_occ_scale = -1;
1040                 c->x86_cache_mbm_width_offset = -1;
1041                 return;
1042         }
1043
1044         /* will be overridden if occupancy monitoring exists */
1045         c->x86_cache_max_rmid = cpuid_ebx(0xf);
1046
1047         if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) ||
1048             cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) ||
1049             cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) {
1050                 u32 eax, ebx, ecx, edx;
1051
1052                 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
1053                 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx);
1054
1055                 c->x86_cache_max_rmid  = ecx;
1056                 c->x86_cache_occ_scale = ebx;
1057                 c->x86_cache_mbm_width_offset = eax & 0xff;
1058
1059                 if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset)
1060                         c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD;
1061         }
1062 }
1063
1064 static int __init resctrl_late_init(void)
1065 {
1066         struct rdt_resource *r;
1067         int state, ret;
1068
1069         /*
1070          * Initialize functions(or definitions) that are different
1071          * between vendors here.
1072          */
1073         rdt_init_res_defs();
1074
1075         check_quirks();
1076
1077         if (!get_rdt_resources())
1078                 return -ENODEV;
1079
1080         rdt_init_padding();
1081
1082         state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
1083                                   "x86/resctrl/cat:online:",
1084                                   resctrl_online_cpu, resctrl_offline_cpu);
1085         if (state < 0)
1086                 return state;
1087
1088         ret = rdtgroup_init();
1089         if (ret) {
1090                 cpuhp_remove_state(state);
1091                 return ret;
1092         }
1093         rdt_online = state;
1094
1095         for_each_alloc_capable_rdt_resource(r)
1096                 pr_info("%s allocation detected\n", r->name);
1097
1098         for_each_mon_capable_rdt_resource(r)
1099                 pr_info("%s monitoring detected\n", r->name);
1100
1101         return 0;
1102 }
1103
1104 late_initcall(resctrl_late_init);
1105
1106 static void __exit resctrl_exit(void)
1107 {
1108         cpuhp_remove_state(rdt_online);
1109         rdtgroup_exit();
1110 }
1111
1112 __exitcall(resctrl_exit);