2 * Intel specific MCE features.
3 * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
4 * Copyright (C) 2008, 2009 Intel Corporation
9 #include <linux/interrupt.h>
10 #include <linux/percpu.h>
11 #include <linux/sched.h>
13 #include <asm/processor.h>
17 #include "mce-internal.h"
20 * Support for Intel Correct Machine Check Interrupts. This allows
21 * the CPU to raise an interrupt when a corrected machine check happened.
22 * Normally we pick those up using a regular polling timer.
23 * Also supports reliable discovery of shared banks.
27 * CMCI can be delivered to multiple cpus that share a machine check bank
28 * so we need to designate a single cpu to process errors logged in each bank
29 * in the interrupt handler (otherwise we would have many races and potential
30 * double reporting of the same error).
31 * Note that this can change when a cpu is offlined or brought online since
32 * some MCA banks are shared across cpus. When a cpu is offlined, cmci_clear()
33 * disables CMCI on all banks owned by the cpu and clears this bitfield. At
34 * this point, cmci_rediscover() kicks in and a different cpu may end up
35 * taking ownership of some of the shared MCA banks that were previously
36 * owned by the offlined cpu.
38 static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
41 * cmci_discover_lock protects against parallel discovery attempts
42 * which could race against each other.
44 static DEFINE_RAW_SPINLOCK(cmci_discover_lock);
46 #define CMCI_THRESHOLD 1
47 #define CMCI_POLL_INTERVAL (30 * HZ)
48 #define CMCI_STORM_INTERVAL (1 * HZ)
49 #define CMCI_STORM_THRESHOLD 15
51 static DEFINE_PER_CPU(unsigned long, cmci_time_stamp);
52 static DEFINE_PER_CPU(unsigned int, cmci_storm_cnt);
53 static DEFINE_PER_CPU(unsigned int, cmci_storm_state);
61 static atomic_t cmci_storm_on_cpus;
63 static int cmci_supported(int *banks)
67 if (mca_cfg.cmci_disabled || mca_cfg.ignore_ce)
71 * Vendor check is not strictly needed, but the initial
72 * initialization is vendor keyed and this
73 * makes sure none of the backdoors are entered otherwise.
75 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
77 if (!cpu_has_apic || lapic_get_maxlvt() < 6)
79 rdmsrl(MSR_IA32_MCG_CAP, cap);
80 *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
81 return !!(cap & MCG_CMCI_P);
84 void mce_intel_cmci_poll(void)
86 if (__this_cpu_read(cmci_storm_state) == CMCI_STORM_NONE)
88 machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
91 void mce_intel_hcpu_update(unsigned long cpu)
93 if (per_cpu(cmci_storm_state, cpu) == CMCI_STORM_ACTIVE)
94 atomic_dec(&cmci_storm_on_cpus);
96 per_cpu(cmci_storm_state, cpu) = CMCI_STORM_NONE;
99 unsigned long mce_intel_adjust_timer(unsigned long interval)
103 if (interval < CMCI_POLL_INTERVAL)
106 switch (__this_cpu_read(cmci_storm_state)) {
107 case CMCI_STORM_ACTIVE:
109 * We switch back to interrupt mode once the poll timer has
110 * silenced itself. That means no events recorded and the
111 * timer interval is back to our poll interval.
113 __this_cpu_write(cmci_storm_state, CMCI_STORM_SUBSIDED);
114 r = atomic_sub_return(1, &cmci_storm_on_cpus);
116 pr_notice("CMCI storm subsided: switching to interrupt mode\n");
119 case CMCI_STORM_SUBSIDED:
121 * We wait for all cpus to go back to SUBSIDED
122 * state. When that happens we switch back to
125 if (!atomic_read(&cmci_storm_on_cpus)) {
126 __this_cpu_write(cmci_storm_state, CMCI_STORM_NONE);
130 return CMCI_POLL_INTERVAL;
133 * We have shiny weather. Let the poll do whatever it
140 static bool cmci_storm_detect(void)
142 unsigned int cnt = __this_cpu_read(cmci_storm_cnt);
143 unsigned long ts = __this_cpu_read(cmci_time_stamp);
144 unsigned long now = jiffies;
147 if (__this_cpu_read(cmci_storm_state) != CMCI_STORM_NONE)
150 if (time_before_eq(now, ts + CMCI_STORM_INTERVAL)) {
154 __this_cpu_write(cmci_time_stamp, now);
156 __this_cpu_write(cmci_storm_cnt, cnt);
158 if (cnt <= CMCI_STORM_THRESHOLD)
162 __this_cpu_write(cmci_storm_state, CMCI_STORM_ACTIVE);
163 r = atomic_add_return(1, &cmci_storm_on_cpus);
164 mce_timer_kick(CMCI_POLL_INTERVAL);
167 pr_notice("CMCI storm detected: switching to poll mode\n");
172 * The interrupt handler. This is called on every event.
173 * Just call the poller directly to log any events.
174 * This could in theory increase the threshold under high load,
175 * but doesn't for now.
177 static void intel_threshold_interrupt(void)
179 if (cmci_storm_detect())
181 machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
186 * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
187 * on this CPU. Use the algorithm recommended in the SDM to discover shared
190 static void cmci_discover(int banks)
192 unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned);
195 int bios_wrong_thresh = 0;
197 raw_spin_lock_irqsave(&cmci_discover_lock, flags);
198 for (i = 0; i < banks; i++) {
200 int bios_zero_thresh = 0;
202 if (test_bit(i, owned))
205 /* Skip banks in firmware first mode */
206 if (test_bit(i, mce_banks_ce_disabled))
209 rdmsrl(MSR_IA32_MCx_CTL2(i), val);
211 /* Already owned by someone else? */
212 if (val & MCI_CTL2_CMCI_EN) {
214 __clear_bit(i, __get_cpu_var(mce_poll_banks));
218 if (!mca_cfg.bios_cmci_threshold) {
219 val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
220 val |= CMCI_THRESHOLD;
221 } else if (!(val & MCI_CTL2_CMCI_THRESHOLD_MASK)) {
223 * If bios_cmci_threshold boot option was specified
224 * but the threshold is zero, we'll try to initialize
227 bios_zero_thresh = 1;
228 val |= CMCI_THRESHOLD;
231 val |= MCI_CTL2_CMCI_EN;
232 wrmsrl(MSR_IA32_MCx_CTL2(i), val);
233 rdmsrl(MSR_IA32_MCx_CTL2(i), val);
235 /* Did the enable bit stick? -- the bank supports CMCI */
236 if (val & MCI_CTL2_CMCI_EN) {
238 __clear_bit(i, __get_cpu_var(mce_poll_banks));
240 * We are able to set thresholds for some banks that
241 * had a threshold of 0. This means the BIOS has not
242 * set the thresholds properly or does not work with
243 * this boot option. Note down now and report later.
245 if (mca_cfg.bios_cmci_threshold && bios_zero_thresh &&
246 (val & MCI_CTL2_CMCI_THRESHOLD_MASK))
247 bios_wrong_thresh = 1;
249 WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
252 raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
253 if (mca_cfg.bios_cmci_threshold && bios_wrong_thresh) {
255 "bios_cmci_threshold: Some banks do not have valid thresholds set\n");
257 "bios_cmci_threshold: Make sure your BIOS supports this boot option\n");
262 * Just in case we missed an event during initialization check
263 * all the CMCI owned banks.
265 void cmci_recheck(void)
270 if (!mce_available(__this_cpu_ptr(&cpu_info)) || !cmci_supported(&banks))
272 local_irq_save(flags);
273 machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
274 local_irq_restore(flags);
277 /* Caller must hold the lock on cmci_discover_lock */
278 static void __cmci_disable_bank(int bank)
282 if (!test_bit(bank, __get_cpu_var(mce_banks_owned)))
284 rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
285 val &= ~MCI_CTL2_CMCI_EN;
286 wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
287 __clear_bit(bank, __get_cpu_var(mce_banks_owned));
291 * Disable CMCI on this CPU for all banks it owns when it goes down.
292 * This allows other CPUs to claim the banks on rediscovery.
294 void cmci_clear(void)
300 if (!cmci_supported(&banks))
302 raw_spin_lock_irqsave(&cmci_discover_lock, flags);
303 for (i = 0; i < banks; i++)
304 __cmci_disable_bank(i);
305 raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
308 static void cmci_rediscover_work_func(void *arg)
312 /* Recheck banks in case CPUs don't all have the same */
313 if (cmci_supported(&banks))
314 cmci_discover(banks);
317 /* After a CPU went down cycle through all the others and rediscover */
318 void cmci_rediscover(void)
322 if (!cmci_supported(&banks))
325 on_each_cpu(cmci_rediscover_work_func, NULL, 1);
329 * Reenable CMCI on this CPU in case a CPU down failed.
331 void cmci_reenable(void)
334 if (cmci_supported(&banks))
335 cmci_discover(banks);
338 void cmci_disable_bank(int bank)
343 if (!cmci_supported(&banks))
346 raw_spin_lock_irqsave(&cmci_discover_lock, flags);
347 __cmci_disable_bank(bank);
348 raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
351 static void intel_init_cmci(void)
355 if (!cmci_supported(&banks))
358 mce_threshold_vector = intel_threshold_interrupt;
359 cmci_discover(banks);
361 * For CPU #0 this runs with still disabled APIC, but that's
362 * ok because only the vector is set up. We still do another
363 * check for the banks later for CPU #0 just to make sure
364 * to not miss any events.
366 apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
370 void mce_intel_feature_init(struct cpuinfo_x86 *c)
372 intel_init_thermal(c);