2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/rcupdate.h>
18 #include <linux/kobject.h>
19 #include <linux/uaccess.h>
20 #include <linux/kdebug.h>
21 #include <linux/kernel.h>
22 #include <linux/percpu.h>
23 #include <linux/string.h>
24 #include <linux/device.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/delay.h>
27 #include <linux/ctype.h>
28 #include <linux/sched.h>
29 #include <linux/sysfs.h>
30 #include <linux/types.h>
31 #include <linux/slab.h>
32 #include <linux/init.h>
33 #include <linux/kmod.h>
34 #include <linux/poll.h>
35 #include <linux/nmi.h>
36 #include <linux/cpu.h>
37 #include <linux/ras.h>
38 #include <linux/smp.h>
41 #include <linux/debugfs.h>
42 #include <linux/irq_work.h>
43 #include <linux/export.h>
44 #include <linux/jump_label.h>
45 #include <linux/set_memory.h>
47 #include <asm/intel-family.h>
48 #include <asm/processor.h>
49 #include <asm/traps.h>
50 #include <asm/tlbflush.h>
53 #include <asm/reboot.h>
55 #include "mce-internal.h"
57 static DEFINE_MUTEX(mce_log_mutex);
59 /* sysfs synchronization */
60 static DEFINE_MUTEX(mce_sysfs_mutex);
62 #define CREATE_TRACE_POINTS
63 #include <trace/events/mce.h>
65 #define SPINUNIT 100 /* 100ns */
67 DEFINE_PER_CPU(unsigned, mce_exception_count);
69 struct mce_bank *mce_banks __read_mostly;
70 struct mce_vendor_flags mce_flags __read_mostly;
72 struct mca_config mca_cfg __read_mostly = {
76 * 0: always panic on uncorrected errors, log corrected errors
77 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
78 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
79 * 3: never panic or SIGBUS, log all errors (for testing only)
85 static DEFINE_PER_CPU(struct mce, mces_seen);
86 static unsigned long mce_need_notify;
87 static int cpu_missing;
90 * MCA banks polled by the period polling timer for corrected events.
91 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
93 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
94 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
98 * MCA banks controlled through firmware first for corrected errors.
99 * This is a global list of banks for which we won't enable CMCI and we
100 * won't poll. Firmware controls these banks and is responsible for
101 * reporting corrected errors through GHES. Uncorrected/recoverable
102 * errors are still notified through a machine check.
104 mce_banks_t mce_banks_ce_disabled;
106 static struct work_struct mce_work;
107 static struct irq_work mce_irq_work;
109 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
112 * CPU/chipset specific EDAC code can register a notifier call here to print
113 * MCE errors in a human-readable form.
115 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
117 /* Do initial initialization of a struct mce */
118 void mce_setup(struct mce *m)
120 memset(m, 0, sizeof(struct mce));
121 m->cpu = m->extcpu = smp_processor_id();
122 /* need the internal __ version to avoid deadlocks */
123 m->time = __ktime_get_real_seconds();
124 m->cpuvendor = boot_cpu_data.x86_vendor;
125 m->cpuid = cpuid_eax(1);
126 m->socketid = cpu_data(m->extcpu).phys_proc_id;
127 m->apicid = cpu_data(m->extcpu).initial_apicid;
128 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
130 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
131 rdmsrl(MSR_PPIN, m->ppin);
133 m->microcode = boot_cpu_data.microcode;
136 DEFINE_PER_CPU(struct mce, injectm);
137 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
139 void mce_log(struct mce *m)
141 if (!mce_gen_pool_add(m))
142 irq_work_queue(&mce_irq_work);
145 void mce_inject_log(struct mce *m)
147 mutex_lock(&mce_log_mutex);
149 mutex_unlock(&mce_log_mutex);
151 EXPORT_SYMBOL_GPL(mce_inject_log);
153 static struct notifier_block mce_srao_nb;
156 * We run the default notifier if we have only the SRAO, the first and the
157 * default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS
158 * notifiers registered on the chain.
160 #define NUM_DEFAULT_NOTIFIERS 3
161 static atomic_t num_notifiers;
163 void mce_register_decode_chain(struct notifier_block *nb)
165 if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC))
168 atomic_inc(&num_notifiers);
170 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
172 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
174 void mce_unregister_decode_chain(struct notifier_block *nb)
176 atomic_dec(&num_notifiers);
178 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
180 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
182 static inline u32 ctl_reg(int bank)
184 return MSR_IA32_MCx_CTL(bank);
187 static inline u32 status_reg(int bank)
189 return MSR_IA32_MCx_STATUS(bank);
192 static inline u32 addr_reg(int bank)
194 return MSR_IA32_MCx_ADDR(bank);
197 static inline u32 misc_reg(int bank)
199 return MSR_IA32_MCx_MISC(bank);
202 static inline u32 smca_ctl_reg(int bank)
204 return MSR_AMD64_SMCA_MCx_CTL(bank);
207 static inline u32 smca_status_reg(int bank)
209 return MSR_AMD64_SMCA_MCx_STATUS(bank);
212 static inline u32 smca_addr_reg(int bank)
214 return MSR_AMD64_SMCA_MCx_ADDR(bank);
217 static inline u32 smca_misc_reg(int bank)
219 return MSR_AMD64_SMCA_MCx_MISC(bank);
222 struct mca_msr_regs msr_ops = {
224 .status = status_reg,
229 static void __print_mce(struct mce *m)
231 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
233 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
234 m->mcgstatus, m->bank, m->status);
237 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
238 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
241 if (m->cs == __KERNEL_CS)
242 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
246 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
248 pr_cont("ADDR %llx ", m->addr);
250 pr_cont("MISC %llx ", m->misc);
252 if (mce_flags.smca) {
254 pr_cont("SYND %llx ", m->synd);
256 pr_cont("IPID %llx ", m->ipid);
261 * Note this output is parsed by external tools and old fields
262 * should not be changed.
264 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
265 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
269 static void print_mce(struct mce *m)
273 if (m->cpuvendor != X86_VENDOR_AMD)
274 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
277 #define PANIC_TIMEOUT 5 /* 5 seconds */
279 static atomic_t mce_panicked;
281 static int fake_panic;
282 static atomic_t mce_fake_panicked;
284 /* Panic in progress. Enable interrupts and wait for final IPI */
285 static void wait_for_panic(void)
287 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
291 while (timeout-- > 0)
293 if (panic_timeout == 0)
294 panic_timeout = mca_cfg.panic_timeout;
295 panic("Panicing machine check CPU died");
298 static void mce_panic(const char *msg, struct mce *final, char *exp)
301 struct llist_node *pending;
302 struct mce_evt_llist *l;
306 * Make sure only one CPU runs in machine check panic
308 if (atomic_inc_return(&mce_panicked) > 1)
315 /* Don't log too much for fake panic */
316 if (atomic_inc_return(&mce_fake_panicked) > 1)
319 pending = mce_gen_pool_prepare_records();
320 /* First print corrected ones that are still unlogged */
321 llist_for_each_entry(l, pending, llnode) {
322 struct mce *m = &l->mce;
323 if (!(m->status & MCI_STATUS_UC)) {
326 apei_err = apei_write_mce(m);
329 /* Now print uncorrected but with the final one last */
330 llist_for_each_entry(l, pending, llnode) {
331 struct mce *m = &l->mce;
332 if (!(m->status & MCI_STATUS_UC))
334 if (!final || mce_cmp(m, final)) {
337 apei_err = apei_write_mce(m);
343 apei_err = apei_write_mce(final);
346 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
348 pr_emerg(HW_ERR "Machine check: %s\n", exp);
350 if (panic_timeout == 0)
351 panic_timeout = mca_cfg.panic_timeout;
354 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
357 /* Support code for software error injection */
359 static int msr_to_offset(u32 msr)
361 unsigned bank = __this_cpu_read(injectm.bank);
363 if (msr == mca_cfg.rip_msr)
364 return offsetof(struct mce, ip);
365 if (msr == msr_ops.status(bank))
366 return offsetof(struct mce, status);
367 if (msr == msr_ops.addr(bank))
368 return offsetof(struct mce, addr);
369 if (msr == msr_ops.misc(bank))
370 return offsetof(struct mce, misc);
371 if (msr == MSR_IA32_MCG_STATUS)
372 return offsetof(struct mce, mcgstatus);
376 /* MSR access wrappers used for error injection */
377 static u64 mce_rdmsrl(u32 msr)
381 if (__this_cpu_read(injectm.finished)) {
382 int offset = msr_to_offset(msr);
386 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
389 if (rdmsrl_safe(msr, &v)) {
390 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
392 * Return zero in case the access faulted. This should
393 * not happen normally but can happen if the CPU does
394 * something weird, or if the code is buggy.
402 static void mce_wrmsrl(u32 msr, u64 v)
404 if (__this_cpu_read(injectm.finished)) {
405 int offset = msr_to_offset(msr);
408 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
415 * Collect all global (w.r.t. this processor) status about this machine
416 * check into our "mce" struct so that we can use it later to assess
417 * the severity of the problem as we read per-bank specific details.
419 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
423 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
426 * Get the address of the instruction at the time of
427 * the machine check error.
429 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
434 * When in VM86 mode make the cs look like ring 3
435 * always. This is a lie, but it's better than passing
436 * the additional vm86 bit around everywhere.
438 if (v8086_mode(regs))
441 /* Use accurate RIP reporting if available. */
443 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
447 int mce_available(struct cpuinfo_x86 *c)
449 if (mca_cfg.disabled)
451 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
454 static void mce_schedule_work(void)
456 if (!mce_gen_pool_empty())
457 schedule_work(&mce_work);
460 static void mce_irq_work_cb(struct irq_work *entry)
465 static void mce_report_event(struct pt_regs *regs)
467 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
470 * Triggering the work queue here is just an insurance
471 * policy in case the syscall exit notify handler
472 * doesn't run soon enough or ends up running on the
473 * wrong CPU (can happen when audit sleeps)
479 irq_work_queue(&mce_irq_work);
483 * Check if the address reported by the CPU is in a format we can parse.
484 * It would be possible to add code for most other cases, but all would
485 * be somewhat complicated (e.g. segment offset would require an instruction
486 * parser). So only support physical addresses up to page granuality for now.
488 static int mce_usable_address(struct mce *m)
490 if (!(m->status & MCI_STATUS_ADDRV))
493 /* Checks after this one are Intel-specific: */
494 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
497 if (!(m->status & MCI_STATUS_MISCV))
500 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
503 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
509 bool mce_is_memory_error(struct mce *m)
511 if (m->cpuvendor == X86_VENDOR_AMD) {
512 return amd_mce_is_memory_error(m);
514 } else if (m->cpuvendor == X86_VENDOR_INTEL) {
516 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
518 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
519 * indicating a memory error. Bit 8 is used for indicating a
520 * cache hierarchy error. The combination of bit 2 and bit 3
521 * is used for indicating a `generic' cache hierarchy error
522 * But we can't just blindly check the above bits, because if
523 * bit 11 is set, then it is a bus/interconnect error - and
524 * either way the above bits just gives more detail on what
525 * bus/interconnect error happened. Note that bit 12 can be
526 * ignored, as it's the "filter" bit.
528 return (m->status & 0xef80) == BIT(7) ||
529 (m->status & 0xef00) == BIT(8) ||
530 (m->status & 0xeffc) == 0xc;
535 EXPORT_SYMBOL_GPL(mce_is_memory_error);
537 static bool mce_is_correctable(struct mce *m)
539 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
542 if (m->status & MCI_STATUS_UC)
548 static bool cec_add_mce(struct mce *m)
553 /* We eat only correctable DRAM errors with usable addresses. */
554 if (mce_is_memory_error(m) &&
555 mce_is_correctable(m) &&
556 mce_usable_address(m))
557 if (!cec_add_elem(m->addr >> PAGE_SHIFT))
563 static int mce_first_notifier(struct notifier_block *nb, unsigned long val,
566 struct mce *m = (struct mce *)data;
574 /* Emit the trace record: */
577 set_bit(0, &mce_need_notify);
584 static struct notifier_block first_nb = {
585 .notifier_call = mce_first_notifier,
586 .priority = MCE_PRIO_FIRST,
589 static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
592 struct mce *mce = (struct mce *)data;
598 if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) {
599 pfn = mce->addr >> PAGE_SHIFT;
600 if (!memory_failure(pfn, 0))
606 static struct notifier_block mce_srao_nb = {
607 .notifier_call = srao_decode_notifier,
608 .priority = MCE_PRIO_SRAO,
611 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
614 struct mce *m = (struct mce *)data;
619 if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS)
627 static struct notifier_block mce_default_nb = {
628 .notifier_call = mce_default_notifier,
629 /* lowest prio, we want it to run last. */
630 .priority = MCE_PRIO_LOWEST,
634 * Read ADDR and MISC registers.
636 static void mce_read_aux(struct mce *m, int i)
638 if (m->status & MCI_STATUS_MISCV)
639 m->misc = mce_rdmsrl(msr_ops.misc(i));
641 if (m->status & MCI_STATUS_ADDRV) {
642 m->addr = mce_rdmsrl(msr_ops.addr(i));
645 * Mask the reported address by the reported granularity.
647 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
648 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
654 * Extract [55:<lsb>] where lsb is the least significant
655 * *valid* bit of the address bits.
657 if (mce_flags.smca) {
658 u8 lsb = (m->addr >> 56) & 0x3f;
660 m->addr &= GENMASK_ULL(55, lsb);
664 if (mce_flags.smca) {
665 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
667 if (m->status & MCI_STATUS_SYNDV)
668 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
672 DEFINE_PER_CPU(unsigned, mce_poll_count);
675 * Poll for corrected events or events that happened before reset.
676 * Those are just logged through /dev/mcelog.
678 * This is executed in standard interrupt context.
680 * Note: spec recommends to panic for fatal unsignalled
681 * errors here. However this would be quite problematic --
682 * we would need to reimplement the Monarch handling and
683 * it would mess up the exclusion between exception handler
684 * and poll hander -- * so we skip this for now.
685 * These cases should not happen anyways, or only when the CPU
686 * is already totally * confused. In this case it's likely it will
687 * not fully execute the machine check handler either.
689 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
691 bool error_seen = false;
695 this_cpu_inc(mce_poll_count);
697 mce_gather_info(&m, NULL);
699 if (flags & MCP_TIMESTAMP)
702 for (i = 0; i < mca_cfg.banks; i++) {
703 if (!mce_banks[i].ctl || !test_bit(i, *b))
711 m.status = mce_rdmsrl(msr_ops.status(i));
712 if (!(m.status & MCI_STATUS_VAL))
716 * Uncorrected or signalled events are handled by the exception
717 * handler when it is enabled, so don't process those here.
719 * TBD do the same check for MCI_STATUS_EN here?
721 if (!(flags & MCP_UC) &&
722 (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
729 m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
732 * Don't get the IP here because it's unlikely to
733 * have anything to do with the actual error location.
735 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
737 else if (mce_usable_address(&m)) {
739 * Although we skipped logging this, we still want
740 * to take action. Add to the pool so the registered
741 * notifiers will see it.
743 if (!mce_gen_pool_add(&m))
748 * Clear state for this bank.
750 mce_wrmsrl(msr_ops.status(i), 0);
754 * Don't clear MCG_STATUS here because it's only defined for
762 EXPORT_SYMBOL_GPL(machine_check_poll);
765 * Do a quick check if any of the events requires a panic.
766 * This decides if we keep the events around or clear them.
768 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
769 struct pt_regs *regs)
774 for (i = 0; i < mca_cfg.banks; i++) {
775 m->status = mce_rdmsrl(msr_ops.status(i));
776 if (!(m->status & MCI_STATUS_VAL))
779 __set_bit(i, validp);
780 if (quirk_no_way_out)
781 quirk_no_way_out(i, m, regs);
783 if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
793 * Variable to establish order between CPUs while scanning.
794 * Each CPU spins initially until executing is equal its number.
796 static atomic_t mce_executing;
799 * Defines order of CPUs on entry. First CPU becomes Monarch.
801 static atomic_t mce_callin;
804 * Check if a timeout waiting for other CPUs happened.
806 static int mce_timed_out(u64 *t, const char *msg)
809 * The others already did panic for some reason.
810 * Bail out like in a timeout.
811 * rmb() to tell the compiler that system_state
812 * might have been modified by someone else.
815 if (atomic_read(&mce_panicked))
817 if (!mca_cfg.monarch_timeout)
819 if ((s64)*t < SPINUNIT) {
820 if (mca_cfg.tolerant <= 1)
821 mce_panic(msg, NULL, NULL);
827 touch_nmi_watchdog();
832 * The Monarch's reign. The Monarch is the CPU who entered
833 * the machine check handler first. It waits for the others to
834 * raise the exception too and then grades them. When any
835 * error is fatal panic. Only then let the others continue.
837 * The other CPUs entering the MCE handler will be controlled by the
838 * Monarch. They are called Subjects.
840 * This way we prevent any potential data corruption in a unrecoverable case
841 * and also makes sure always all CPU's errors are examined.
843 * Also this detects the case of a machine check event coming from outer
844 * space (not detected by any CPUs) In this case some external agent wants
845 * us to shut down, so panic too.
847 * The other CPUs might still decide to panic if the handler happens
848 * in a unrecoverable place, but in this case the system is in a semi-stable
849 * state and won't corrupt anything by itself. It's ok to let the others
850 * continue for a bit first.
852 * All the spin loops have timeouts; when a timeout happens a CPU
853 * typically elects itself to be Monarch.
855 static void mce_reign(void)
858 struct mce *m = NULL;
859 int global_worst = 0;
864 * This CPU is the Monarch and the other CPUs have run
865 * through their handlers.
866 * Grade the severity of the errors of all the CPUs.
868 for_each_possible_cpu(cpu) {
869 int severity = mce_severity(&per_cpu(mces_seen, cpu),
872 if (severity > global_worst) {
874 global_worst = severity;
875 m = &per_cpu(mces_seen, cpu);
880 * Cannot recover? Panic here then.
881 * This dumps all the mces in the log buffer and stops the
884 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
885 mce_panic("Fatal machine check", m, msg);
888 * For UC somewhere we let the CPU who detects it handle it.
889 * Also must let continue the others, otherwise the handling
890 * CPU could deadlock on a lock.
894 * No machine check event found. Must be some external
895 * source or one CPU is hung. Panic.
897 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
898 mce_panic("Fatal machine check from unknown source", NULL, NULL);
901 * Now clear all the mces_seen so that they don't reappear on
904 for_each_possible_cpu(cpu)
905 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
908 static atomic_t global_nwo;
911 * Start of Monarch synchronization. This waits until all CPUs have
912 * entered the exception handler and then determines if any of them
913 * saw a fatal event that requires panic. Then it executes them
914 * in the entry order.
915 * TBD double check parallel CPU hotunplug
917 static int mce_start(int *no_way_out)
920 int cpus = num_online_cpus();
921 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
926 atomic_add(*no_way_out, &global_nwo);
928 * Rely on the implied barrier below, such that global_nwo
929 * is updated before mce_callin.
931 order = atomic_inc_return(&mce_callin);
936 while (atomic_read(&mce_callin) != cpus) {
937 if (mce_timed_out(&timeout,
938 "Timeout: Not all CPUs entered broadcast exception handler")) {
939 atomic_set(&global_nwo, 0);
946 * mce_callin should be read before global_nwo
952 * Monarch: Starts executing now, the others wait.
954 atomic_set(&mce_executing, 1);
957 * Subject: Now start the scanning loop one by one in
958 * the original callin order.
959 * This way when there are any shared banks it will be
960 * only seen by one CPU before cleared, avoiding duplicates.
962 while (atomic_read(&mce_executing) < order) {
963 if (mce_timed_out(&timeout,
964 "Timeout: Subject CPUs unable to finish machine check processing")) {
965 atomic_set(&global_nwo, 0);
973 * Cache the global no_way_out state.
975 *no_way_out = atomic_read(&global_nwo);
981 * Synchronize between CPUs after main scanning loop.
982 * This invokes the bulk of the Monarch processing.
984 static int mce_end(int order)
987 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
995 * Allow others to run.
997 atomic_inc(&mce_executing);
1000 /* CHECKME: Can this race with a parallel hotplug? */
1001 int cpus = num_online_cpus();
1004 * Monarch: Wait for everyone to go through their scanning
1007 while (atomic_read(&mce_executing) <= cpus) {
1008 if (mce_timed_out(&timeout,
1009 "Timeout: Monarch CPU unable to finish machine check processing"))
1019 * Subject: Wait for Monarch to finish.
1021 while (atomic_read(&mce_executing) != 0) {
1022 if (mce_timed_out(&timeout,
1023 "Timeout: Monarch CPU did not finish machine check processing"))
1029 * Don't reset anything. That's done by the Monarch.
1035 * Reset all global state.
1038 atomic_set(&global_nwo, 0);
1039 atomic_set(&mce_callin, 0);
1043 * Let others run again.
1045 atomic_set(&mce_executing, 0);
1049 static void mce_clear_state(unsigned long *toclear)
1053 for (i = 0; i < mca_cfg.banks; i++) {
1054 if (test_bit(i, toclear))
1055 mce_wrmsrl(msr_ops.status(i), 0);
1059 static int do_memory_failure(struct mce *m)
1061 int flags = MF_ACTION_REQUIRED;
1064 pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr);
1065 if (!(m->mcgstatus & MCG_STATUS_RIPV))
1066 flags |= MF_MUST_KILL;
1067 ret = memory_failure(m->addr >> PAGE_SHIFT, flags);
1069 pr_err("Memory error not recovered");
1071 set_mce_nospec(m->addr >> PAGE_SHIFT);
1077 * Cases where we avoid rendezvous handler timeout:
1078 * 1) If this CPU is offline.
1080 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1081 * skip those CPUs which remain looping in the 1st kernel - see
1082 * crash_nmi_callback().
1084 * Note: there still is a small window between kexec-ing and the new,
1085 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1086 * might not get handled properly.
1088 static bool __mc_check_crashing_cpu(int cpu)
1090 if (cpu_is_offline(cpu) ||
1091 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1094 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
1095 if (mcgstatus & MCG_STATUS_RIPV) {
1096 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1103 static void __mc_scan_banks(struct mce *m, struct mce *final,
1104 unsigned long *toclear, unsigned long *valid_banks,
1105 int no_way_out, int *worst)
1107 struct mca_config *cfg = &mca_cfg;
1110 for (i = 0; i < cfg->banks; i++) {
1111 __clear_bit(i, toclear);
1112 if (!test_bit(i, valid_banks))
1115 if (!mce_banks[i].ctl)
1122 m->status = mce_rdmsrl(msr_ops.status(i));
1123 if (!(m->status & MCI_STATUS_VAL))
1127 * Corrected or non-signaled errors are handled by
1128 * machine_check_poll(). Leave them alone, unless this panics.
1130 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1134 /* Set taint even when machine check was not enabled. */
1135 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1137 severity = mce_severity(m, cfg->tolerant, NULL, true);
1140 * When machine check was for corrected/deferred handler don't
1141 * touch, unless we're panicking.
1143 if ((severity == MCE_KEEP_SEVERITY ||
1144 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1147 __set_bit(i, toclear);
1149 /* Machine check event was not enabled. Clear, but ignore. */
1150 if (severity == MCE_NO_SEVERITY)
1155 /* assuming valid severity level != 0 */
1156 m->severity = severity;
1160 if (severity > *worst) {
1166 /* mce_clear_state will clear *final, save locally for use later */
1171 * The actual machine check handler. This only handles real
1172 * exceptions when something got corrupted coming in through int 18.
1174 * This is executed in NMI context not subject to normal locking rules. This
1175 * implies that most kernel services cannot be safely used. Don't even
1176 * think about putting a printk in there!
1178 * On Intel systems this is entered on all CPUs in parallel through
1179 * MCE broadcast. However some CPUs might be broken beyond repair,
1180 * so be always careful when synchronizing with others.
1182 void do_machine_check(struct pt_regs *regs, long error_code)
1184 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1185 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1186 struct mca_config *cfg = &mca_cfg;
1187 int cpu = smp_processor_id();
1188 char *msg = "Unknown";
1189 struct mce m, *final;
1193 * Establish sequential order between the CPUs entering the machine
1199 * If no_way_out gets set, there is no safe way to recover from this
1200 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1205 * If kill_it gets set, there might be a way to recover from this
1211 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1216 if (__mc_check_crashing_cpu(cpu))
1221 this_cpu_inc(mce_exception_count);
1223 mce_gather_info(&m, regs);
1226 final = this_cpu_ptr(&mces_seen);
1229 memset(valid_banks, 0, sizeof(valid_banks));
1230 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1235 * When no restart IP might need to kill or panic.
1236 * Assume the worst for now, but if we find the
1237 * severity is MCE_AR_SEVERITY we have other options.
1239 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1243 * Check if this MCE is signaled to only this logical processor,
1246 if (m.cpuvendor == X86_VENDOR_INTEL)
1247 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1250 * Local machine check may already know that we have to panic.
1251 * Broadcast machine check begins rendezvous in mce_start()
1252 * Go through all banks in exclusion of the other CPUs. This way we
1253 * don't report duplicated events on shared banks because the first one
1254 * to see it will clear it.
1258 mce_panic("Fatal local machine check", &m, msg);
1260 order = mce_start(&no_way_out);
1263 __mc_scan_banks(&m, final, toclear, valid_banks, no_way_out, &worst);
1266 mce_clear_state(toclear);
1269 * Do most of the synchronization with other CPUs.
1270 * When there's any problem use only local no_way_out state.
1273 if (mce_end(order) < 0)
1274 no_way_out = worst >= MCE_PANIC_SEVERITY;
1277 * If there was a fatal machine check we should have
1278 * already called mce_panic earlier in this function.
1279 * Since we re-read the banks, we might have found
1280 * something new. Check again to see if we found a
1281 * fatal error. We call "mce_severity()" again to
1282 * make sure we have the right "msg".
1284 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
1285 mce_severity(&m, cfg->tolerant, &msg, true);
1286 mce_panic("Local fatal machine check!", &m, msg);
1291 * If tolerant is at an insane level we drop requests to kill
1292 * processes and continue even when there is no way out.
1294 if (cfg->tolerant == 3)
1296 else if (no_way_out)
1297 mce_panic("Fatal machine check on current CPU", &m, msg);
1300 mce_report_event(regs);
1301 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1305 if (worst != MCE_AR_SEVERITY && !kill_it)
1308 /* Fault was in user mode and we need to take some action */
1309 if ((m.cs & 3) == 3) {
1310 ist_begin_non_atomic(regs);
1313 if (kill_it || do_memory_failure(&m))
1314 force_sig(SIGBUS, current);
1315 local_irq_disable();
1316 ist_end_non_atomic();
1318 if (!fixup_exception(regs, X86_TRAP_MC))
1319 mce_panic("Failed kernel mode recovery", &m, NULL);
1325 EXPORT_SYMBOL_GPL(do_machine_check);
1327 #ifndef CONFIG_MEMORY_FAILURE
1328 int memory_failure(unsigned long pfn, int flags)
1330 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1331 BUG_ON(flags & MF_ACTION_REQUIRED);
1332 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1333 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1341 * Periodic polling timer for "silent" machine check errors. If the
1342 * poller finds an MCE, poll 2x faster. When the poller finds no more
1343 * errors, poll 2x slower (up to check_interval seconds).
1345 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1347 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1348 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1350 static unsigned long mce_adjust_timer_default(unsigned long interval)
1355 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1357 static void __start_timer(struct timer_list *t, unsigned long interval)
1359 unsigned long when = jiffies + interval;
1360 unsigned long flags;
1362 local_irq_save(flags);
1364 if (!timer_pending(t) || time_before(when, t->expires))
1365 mod_timer(t, round_jiffies(when));
1367 local_irq_restore(flags);
1370 static void mce_timer_fn(struct timer_list *t)
1372 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1375 WARN_ON(cpu_t != t);
1377 iv = __this_cpu_read(mce_next_interval);
1379 if (mce_available(this_cpu_ptr(&cpu_info))) {
1380 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1382 if (mce_intel_cmci_poll()) {
1383 iv = mce_adjust_timer(iv);
1389 * Alert userspace if needed. If we logged an MCE, reduce the polling
1390 * interval, otherwise increase the polling interval.
1392 if (mce_notify_irq())
1393 iv = max(iv / 2, (unsigned long) HZ/100);
1395 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1398 __this_cpu_write(mce_next_interval, iv);
1399 __start_timer(t, iv);
1403 * Ensure that the timer is firing in @interval from now.
1405 void mce_timer_kick(unsigned long interval)
1407 struct timer_list *t = this_cpu_ptr(&mce_timer);
1408 unsigned long iv = __this_cpu_read(mce_next_interval);
1410 __start_timer(t, interval);
1413 __this_cpu_write(mce_next_interval, interval);
1416 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1417 static void mce_timer_delete_all(void)
1421 for_each_online_cpu(cpu)
1422 del_timer_sync(&per_cpu(mce_timer, cpu));
1426 * Notify the user(s) about new machine check events.
1427 * Can be called from interrupt context, but not from machine check/NMI
1430 int mce_notify_irq(void)
1432 /* Not more than two messages every minute */
1433 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1435 if (test_and_clear_bit(0, &mce_need_notify)) {
1438 if (__ratelimit(&ratelimit))
1439 pr_info(HW_ERR "Machine check events logged\n");
1445 EXPORT_SYMBOL_GPL(mce_notify_irq);
1447 static int __mcheck_cpu_mce_banks_init(void)
1450 u8 num_banks = mca_cfg.banks;
1452 mce_banks = kcalloc(num_banks, sizeof(struct mce_bank), GFP_KERNEL);
1456 for (i = 0; i < num_banks; i++) {
1457 struct mce_bank *b = &mce_banks[i];
1466 * Initialize Machine Checks for a CPU.
1468 static int __mcheck_cpu_cap_init(void)
1473 rdmsrl(MSR_IA32_MCG_CAP, cap);
1475 b = cap & MCG_BANKCNT_MASK;
1477 pr_info("CPU supports %d MCE banks\n", b);
1479 if (b > MAX_NR_BANKS) {
1480 pr_warn("Using only %u machine check banks out of %u\n",
1485 /* Don't support asymmetric configurations today */
1486 WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks);
1490 int err = __mcheck_cpu_mce_banks_init();
1496 /* Use accurate RIP reporting if available. */
1497 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1498 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1500 if (cap & MCG_SER_P)
1506 static void __mcheck_cpu_init_generic(void)
1508 enum mcp_flags m_fl = 0;
1509 mce_banks_t all_banks;
1512 if (!mca_cfg.bootlog)
1516 * Log the machine checks left over from the previous reset.
1518 bitmap_fill(all_banks, MAX_NR_BANKS);
1519 machine_check_poll(MCP_UC | m_fl, &all_banks);
1521 cr4_set_bits(X86_CR4_MCE);
1523 rdmsrl(MSR_IA32_MCG_CAP, cap);
1524 if (cap & MCG_CTL_P)
1525 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1528 static void __mcheck_cpu_init_clear_banks(void)
1532 for (i = 0; i < mca_cfg.banks; i++) {
1533 struct mce_bank *b = &mce_banks[i];
1537 wrmsrl(msr_ops.ctl(i), b->ctl);
1538 wrmsrl(msr_ops.status(i), 0);
1543 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1544 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1545 * Vol 3B Table 15-20). But this confuses both the code that determines
1546 * whether the machine check occurred in kernel or user mode, and also
1547 * the severity assessment code. Pretend that EIPV was set, and take the
1548 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1550 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1554 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1556 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1557 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1558 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1560 (MCI_STATUS_UC|MCI_STATUS_EN|
1561 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1562 MCI_STATUS_AR|MCACOD_INSTR))
1565 m->mcgstatus |= MCG_STATUS_EIPV;
1570 /* Add per CPU specific workarounds here */
1571 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1573 struct mca_config *cfg = &mca_cfg;
1575 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1576 pr_info("unknown CPU type - not enabling MCE support\n");
1580 /* This should be disabled by the BIOS, but isn't always */
1581 if (c->x86_vendor == X86_VENDOR_AMD) {
1582 if (c->x86 == 15 && cfg->banks > 4) {
1584 * disable GART TBL walk error reporting, which
1585 * trips off incorrectly with the IOMMU & 3ware
1588 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1590 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1592 * Lots of broken BIOS around that don't clear them
1593 * by default and leave crap in there. Don't log:
1598 * Various K7s with broken bank 0 around. Always disable
1601 if (c->x86 == 6 && cfg->banks > 0)
1602 mce_banks[0].ctl = 0;
1605 * overflow_recov is supported for F15h Models 00h-0fh
1606 * even though we don't have a CPUID bit for it.
1608 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1609 mce_flags.overflow_recov = 1;
1612 * Turn off MC4_MISC thresholding banks on those models since
1613 * they're not supported there.
1615 if (c->x86 == 0x15 &&
1616 (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
1621 0x00000413, /* MC4_MISC0 */
1622 0xc0000408, /* MC4_MISC1 */
1625 rdmsrl(MSR_K7_HWCR, hwcr);
1627 /* McStatusWrEn has to be set */
1628 need_toggle = !(hwcr & BIT(18));
1631 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
1633 /* Clear CntP bit safely */
1634 for (i = 0; i < ARRAY_SIZE(msrs); i++)
1635 msr_clear_bit(msrs[i], 62);
1637 /* restore old settings */
1639 wrmsrl(MSR_K7_HWCR, hwcr);
1643 if (c->x86_vendor == X86_VENDOR_INTEL) {
1645 * SDM documents that on family 6 bank 0 should not be written
1646 * because it aliases to another special BIOS controlled
1648 * But it's not aliased anymore on model 0x1a+
1649 * Don't ignore bank 0 completely because there could be a
1650 * valid event later, merely don't write CTL0.
1653 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1654 mce_banks[0].init = 0;
1657 * All newer Intel systems support MCE broadcasting. Enable
1658 * synchronization with a one second timeout.
1660 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1661 cfg->monarch_timeout < 0)
1662 cfg->monarch_timeout = USEC_PER_SEC;
1665 * There are also broken BIOSes on some Pentium M and
1668 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1671 if (c->x86 == 6 && c->x86_model == 45)
1672 quirk_no_way_out = quirk_sandybridge_ifu;
1674 if (cfg->monarch_timeout < 0)
1675 cfg->monarch_timeout = 0;
1676 if (cfg->bootlog != 0)
1677 cfg->panic_timeout = 30;
1682 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1687 switch (c->x86_vendor) {
1688 case X86_VENDOR_INTEL:
1689 intel_p5_mcheck_init(c);
1692 case X86_VENDOR_CENTAUR:
1693 winchip_mcheck_init(c);
1704 * Init basic CPU features needed for early decoding of MCEs.
1706 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1708 if (c->x86_vendor == X86_VENDOR_AMD) {
1709 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1710 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1711 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1713 if (mce_flags.smca) {
1714 msr_ops.ctl = smca_ctl_reg;
1715 msr_ops.status = smca_status_reg;
1716 msr_ops.addr = smca_addr_reg;
1717 msr_ops.misc = smca_misc_reg;
1722 static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1724 struct mca_config *cfg = &mca_cfg;
1727 * All newer Centaur CPUs support MCE broadcasting. Enable
1728 * synchronization with a one second timeout.
1730 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1732 if (cfg->monarch_timeout < 0)
1733 cfg->monarch_timeout = USEC_PER_SEC;
1737 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1739 switch (c->x86_vendor) {
1740 case X86_VENDOR_INTEL:
1741 mce_intel_feature_init(c);
1742 mce_adjust_timer = cmci_intel_adjust_timer;
1745 case X86_VENDOR_AMD: {
1746 mce_amd_feature_init(c);
1749 case X86_VENDOR_CENTAUR:
1750 mce_centaur_feature_init(c);
1758 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1760 switch (c->x86_vendor) {
1761 case X86_VENDOR_INTEL:
1762 mce_intel_feature_clear(c);
1769 static void mce_start_timer(struct timer_list *t)
1771 unsigned long iv = check_interval * HZ;
1773 if (mca_cfg.ignore_ce || !iv)
1776 this_cpu_write(mce_next_interval, iv);
1777 __start_timer(t, iv);
1780 static void __mcheck_cpu_setup_timer(void)
1782 struct timer_list *t = this_cpu_ptr(&mce_timer);
1784 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1787 static void __mcheck_cpu_init_timer(void)
1789 struct timer_list *t = this_cpu_ptr(&mce_timer);
1791 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1795 /* Handle unconfigured int18 (should never happen) */
1796 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1798 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1799 smp_processor_id());
1802 /* Call the installed machine check handler for this CPU setup. */
1803 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1804 unexpected_machine_check;
1806 dotraplinkage void do_mce(struct pt_regs *regs, long error_code)
1808 machine_check_vector(regs, error_code);
1812 * Called for each booted CPU to set up machine checks.
1813 * Must be called with preempt off:
1815 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1817 if (mca_cfg.disabled)
1820 if (__mcheck_cpu_ancient_init(c))
1823 if (!mce_available(c))
1826 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1827 mca_cfg.disabled = 1;
1831 if (mce_gen_pool_init()) {
1832 mca_cfg.disabled = 1;
1833 pr_emerg("Couldn't allocate MCE records pool!\n");
1837 machine_check_vector = do_machine_check;
1839 __mcheck_cpu_init_early(c);
1840 __mcheck_cpu_init_generic();
1841 __mcheck_cpu_init_vendor(c);
1842 __mcheck_cpu_init_clear_banks();
1843 __mcheck_cpu_setup_timer();
1847 * Called for each booted CPU to clear some machine checks opt-ins
1849 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
1851 if (mca_cfg.disabled)
1854 if (!mce_available(c))
1858 * Possibly to clear general settings generic to x86
1859 * __mcheck_cpu_clear_generic(c);
1861 __mcheck_cpu_clear_vendor(c);
1865 static void __mce_disable_bank(void *arg)
1867 int bank = *((int *)arg);
1868 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
1869 cmci_disable_bank(bank);
1872 void mce_disable_bank(int bank)
1874 if (bank >= mca_cfg.banks) {
1876 "Ignoring request to disable invalid MCA bank %d.\n",
1880 set_bit(bank, mce_banks_ce_disabled);
1881 on_each_cpu(__mce_disable_bank, &bank, 1);
1885 * mce=off Disables machine check
1886 * mce=no_cmci Disables CMCI
1887 * mce=no_lmce Disables LMCE
1888 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1889 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1890 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1891 * monarchtimeout is how long to wait for other CPUs on machine
1892 * check, or 0 to not wait
1893 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
1895 * mce=nobootlog Don't log MCEs from before booting.
1896 * mce=bios_cmci_threshold Don't program the CMCI threshold
1897 * mce=recovery force enable memcpy_mcsafe()
1899 static int __init mcheck_enable(char *str)
1901 struct mca_config *cfg = &mca_cfg;
1909 if (!strcmp(str, "off"))
1911 else if (!strcmp(str, "no_cmci"))
1912 cfg->cmci_disabled = true;
1913 else if (!strcmp(str, "no_lmce"))
1914 cfg->lmce_disabled = 1;
1915 else if (!strcmp(str, "dont_log_ce"))
1916 cfg->dont_log_ce = true;
1917 else if (!strcmp(str, "ignore_ce"))
1918 cfg->ignore_ce = true;
1919 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1920 cfg->bootlog = (str[0] == 'b');
1921 else if (!strcmp(str, "bios_cmci_threshold"))
1922 cfg->bios_cmci_threshold = 1;
1923 else if (!strcmp(str, "recovery"))
1925 else if (isdigit(str[0])) {
1926 if (get_option(&str, &cfg->tolerant) == 2)
1927 get_option(&str, &(cfg->monarch_timeout));
1929 pr_info("mce argument %s ignored. Please use /sys\n", str);
1934 __setup("mce", mcheck_enable);
1936 int __init mcheck_init(void)
1938 mcheck_intel_therm_init();
1939 mce_register_decode_chain(&first_nb);
1940 mce_register_decode_chain(&mce_srao_nb);
1941 mce_register_decode_chain(&mce_default_nb);
1942 mcheck_vendor_init_severity();
1944 INIT_WORK(&mce_work, mce_gen_pool_process);
1945 init_irq_work(&mce_irq_work, mce_irq_work_cb);
1951 * mce_syscore: PM support
1955 * Disable machine checks on suspend and shutdown. We can't really handle
1958 static void mce_disable_error_reporting(void)
1962 for (i = 0; i < mca_cfg.banks; i++) {
1963 struct mce_bank *b = &mce_banks[i];
1966 wrmsrl(msr_ops.ctl(i), 0);
1971 static void vendor_disable_error_reporting(void)
1974 * Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
1975 * Disabling them for just a single offlined CPU is bad, since it will
1976 * inhibit reporting for all shared resources on the socket like the
1977 * last level cache (LLC), the integrated memory controller (iMC), etc.
1979 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
1980 boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1983 mce_disable_error_reporting();
1986 static int mce_syscore_suspend(void)
1988 vendor_disable_error_reporting();
1992 static void mce_syscore_shutdown(void)
1994 vendor_disable_error_reporting();
1998 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1999 * Only one CPU is active at this time, the others get re-added later using
2002 static void mce_syscore_resume(void)
2004 __mcheck_cpu_init_generic();
2005 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2006 __mcheck_cpu_init_clear_banks();
2009 static struct syscore_ops mce_syscore_ops = {
2010 .suspend = mce_syscore_suspend,
2011 .shutdown = mce_syscore_shutdown,
2012 .resume = mce_syscore_resume,
2016 * mce_device: Sysfs support
2019 static void mce_cpu_restart(void *data)
2021 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2023 __mcheck_cpu_init_generic();
2024 __mcheck_cpu_init_clear_banks();
2025 __mcheck_cpu_init_timer();
2028 /* Reinit MCEs after user configuration changes */
2029 static void mce_restart(void)
2031 mce_timer_delete_all();
2032 on_each_cpu(mce_cpu_restart, NULL, 1);
2035 /* Toggle features for corrected errors */
2036 static void mce_disable_cmci(void *data)
2038 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2043 static void mce_enable_ce(void *all)
2045 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2050 __mcheck_cpu_init_timer();
2053 static struct bus_type mce_subsys = {
2054 .name = "machinecheck",
2055 .dev_name = "machinecheck",
2058 DEFINE_PER_CPU(struct device *, mce_device);
2060 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2062 return container_of(attr, struct mce_bank, attr);
2065 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2068 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2071 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2072 const char *buf, size_t size)
2076 if (kstrtou64(buf, 0, &new) < 0)
2079 attr_to_bank(attr)->ctl = new;
2085 static ssize_t set_ignore_ce(struct device *s,
2086 struct device_attribute *attr,
2087 const char *buf, size_t size)
2091 if (kstrtou64(buf, 0, &new) < 0)
2094 mutex_lock(&mce_sysfs_mutex);
2095 if (mca_cfg.ignore_ce ^ !!new) {
2097 /* disable ce features */
2098 mce_timer_delete_all();
2099 on_each_cpu(mce_disable_cmci, NULL, 1);
2100 mca_cfg.ignore_ce = true;
2102 /* enable ce features */
2103 mca_cfg.ignore_ce = false;
2104 on_each_cpu(mce_enable_ce, (void *)1, 1);
2107 mutex_unlock(&mce_sysfs_mutex);
2112 static ssize_t set_cmci_disabled(struct device *s,
2113 struct device_attribute *attr,
2114 const char *buf, size_t size)
2118 if (kstrtou64(buf, 0, &new) < 0)
2121 mutex_lock(&mce_sysfs_mutex);
2122 if (mca_cfg.cmci_disabled ^ !!new) {
2125 on_each_cpu(mce_disable_cmci, NULL, 1);
2126 mca_cfg.cmci_disabled = true;
2129 mca_cfg.cmci_disabled = false;
2130 on_each_cpu(mce_enable_ce, NULL, 1);
2133 mutex_unlock(&mce_sysfs_mutex);
2138 static ssize_t store_int_with_restart(struct device *s,
2139 struct device_attribute *attr,
2140 const char *buf, size_t size)
2142 unsigned long old_check_interval = check_interval;
2143 ssize_t ret = device_store_ulong(s, attr, buf, size);
2145 if (check_interval == old_check_interval)
2148 mutex_lock(&mce_sysfs_mutex);
2150 mutex_unlock(&mce_sysfs_mutex);
2155 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2156 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2157 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2159 static struct dev_ext_attribute dev_attr_check_interval = {
2160 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2164 static struct dev_ext_attribute dev_attr_ignore_ce = {
2165 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2169 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2170 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2171 &mca_cfg.cmci_disabled
2174 static struct device_attribute *mce_device_attrs[] = {
2175 &dev_attr_tolerant.attr,
2176 &dev_attr_check_interval.attr,
2177 #ifdef CONFIG_X86_MCELOG_LEGACY
2180 &dev_attr_monarch_timeout.attr,
2181 &dev_attr_dont_log_ce.attr,
2182 &dev_attr_ignore_ce.attr,
2183 &dev_attr_cmci_disabled.attr,
2187 static cpumask_var_t mce_device_initialized;
2189 static void mce_device_release(struct device *dev)
2194 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2195 static int mce_device_create(unsigned int cpu)
2201 if (!mce_available(&boot_cpu_data))
2204 dev = per_cpu(mce_device, cpu);
2208 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2212 dev->bus = &mce_subsys;
2213 dev->release = &mce_device_release;
2215 err = device_register(dev);
2221 for (i = 0; mce_device_attrs[i]; i++) {
2222 err = device_create_file(dev, mce_device_attrs[i]);
2226 for (j = 0; j < mca_cfg.banks; j++) {
2227 err = device_create_file(dev, &mce_banks[j].attr);
2231 cpumask_set_cpu(cpu, mce_device_initialized);
2232 per_cpu(mce_device, cpu) = dev;
2237 device_remove_file(dev, &mce_banks[j].attr);
2240 device_remove_file(dev, mce_device_attrs[i]);
2242 device_unregister(dev);
2247 static void mce_device_remove(unsigned int cpu)
2249 struct device *dev = per_cpu(mce_device, cpu);
2252 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2255 for (i = 0; mce_device_attrs[i]; i++)
2256 device_remove_file(dev, mce_device_attrs[i]);
2258 for (i = 0; i < mca_cfg.banks; i++)
2259 device_remove_file(dev, &mce_banks[i].attr);
2261 device_unregister(dev);
2262 cpumask_clear_cpu(cpu, mce_device_initialized);
2263 per_cpu(mce_device, cpu) = NULL;
2266 /* Make sure there are no machine checks on offlined CPUs. */
2267 static void mce_disable_cpu(void)
2269 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2272 if (!cpuhp_tasks_frozen)
2275 vendor_disable_error_reporting();
2278 static void mce_reenable_cpu(void)
2282 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2285 if (!cpuhp_tasks_frozen)
2287 for (i = 0; i < mca_cfg.banks; i++) {
2288 struct mce_bank *b = &mce_banks[i];
2291 wrmsrl(msr_ops.ctl(i), b->ctl);
2295 static int mce_cpu_dead(unsigned int cpu)
2297 mce_intel_hcpu_update(cpu);
2299 /* intentionally ignoring frozen here */
2300 if (!cpuhp_tasks_frozen)
2305 static int mce_cpu_online(unsigned int cpu)
2307 struct timer_list *t = this_cpu_ptr(&mce_timer);
2310 mce_device_create(cpu);
2312 ret = mce_threshold_create_device(cpu);
2314 mce_device_remove(cpu);
2322 static int mce_cpu_pre_down(unsigned int cpu)
2324 struct timer_list *t = this_cpu_ptr(&mce_timer);
2328 mce_threshold_remove_device(cpu);
2329 mce_device_remove(cpu);
2333 static __init void mce_init_banks(void)
2337 for (i = 0; i < mca_cfg.banks; i++) {
2338 struct mce_bank *b = &mce_banks[i];
2339 struct device_attribute *a = &b->attr;
2341 sysfs_attr_init(&a->attr);
2342 a->attr.name = b->attrname;
2343 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2345 a->attr.mode = 0644;
2346 a->show = show_bank;
2347 a->store = set_bank;
2351 static __init int mcheck_init_device(void)
2356 * Check if we have a spare virtual bit. This will only become
2357 * a problem if/when we move beyond 5-level page tables.
2359 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2361 if (!mce_available(&boot_cpu_data)) {
2366 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2373 err = subsys_system_register(&mce_subsys, NULL);
2377 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2382 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2383 mce_cpu_online, mce_cpu_pre_down);
2385 goto err_out_online;
2387 register_syscore_ops(&mce_syscore_ops);
2392 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2395 free_cpumask_var(mce_device_initialized);
2398 pr_err("Unable to init MCE device (rc: %d)\n", err);
2402 device_initcall_sync(mcheck_init_device);
2405 * Old style boot options parsing. Only for compatibility.
2407 static int __init mcheck_disable(char *str)
2409 mca_cfg.disabled = 1;
2412 __setup("nomce", mcheck_disable);
2414 #ifdef CONFIG_DEBUG_FS
2415 struct dentry *mce_get_debugfs_dir(void)
2417 static struct dentry *dmce;
2420 dmce = debugfs_create_dir("mce", NULL);
2425 static void mce_reset(void)
2428 atomic_set(&mce_fake_panicked, 0);
2429 atomic_set(&mce_executing, 0);
2430 atomic_set(&mce_callin, 0);
2431 atomic_set(&global_nwo, 0);
2434 static int fake_panic_get(void *data, u64 *val)
2440 static int fake_panic_set(void *data, u64 val)
2447 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2448 fake_panic_set, "%llu\n");
2450 static int __init mcheck_debugfs_init(void)
2452 struct dentry *dmce, *ffake_panic;
2454 dmce = mce_get_debugfs_dir();
2457 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2465 static int __init mcheck_debugfs_init(void) { return -EINVAL; }
2468 DEFINE_STATIC_KEY_FALSE(mcsafe_key);
2469 EXPORT_SYMBOL_GPL(mcsafe_key);
2471 static int __init mcheck_late_init(void)
2473 if (mca_cfg.recovery)
2474 static_branch_inc(&mcsafe_key);
2476 mcheck_debugfs_init();
2480 * Flush out everything that has been logged during early boot, now that
2481 * everything has been initialized (workqueues, decoders, ...).
2483 mce_schedule_work();
2487 late_initcall(mcheck_late_init);