3 * Copyright 2008, 2009 Intel Corporation.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; version 2
12 #include <linux/kernel.h>
13 #include <linux/seq_file.h>
14 #include <linux/init.h>
15 #include <linux/debugfs.h>
17 #include <linux/uaccess.h>
22 * Grade an mce by severity. In general the most severe ones are processed
23 * first. Since there are quite a lot of combinations test the bits in a
24 * table-driven way. The rules are simply processed in order, first
27 * Note this is only used for machine check exceptions, the corrected
28 * errors use much simpler rules. The exceptions still check for the corrected
29 * errors, but only to leave them alone for the CMCI handler (except for
33 enum context { IN_KERNEL = 1, IN_USER = 2, IN_KERNEL_RECOV = 3 };
34 enum ser { SER_REQUIRED = 1, NO_SER = 2 };
35 enum exception { EXCP_CONTEXT = 1, NO_EXCP = 2 };
37 static struct severity {
41 unsigned char mcgmask;
44 unsigned char context;
46 unsigned char covered;
49 #define MCESEV(s, m, c...) { .sev = MCE_ ## s ## _SEVERITY, .msg = m, ## c }
50 #define KERNEL .context = IN_KERNEL
51 #define USER .context = IN_USER
52 #define KERNEL_RECOV .context = IN_KERNEL_RECOV
53 #define SER .ser = SER_REQUIRED
54 #define NOSER .ser = NO_SER
55 #define EXCP .excp = EXCP_CONTEXT
56 #define NOEXCP .excp = NO_EXCP
57 #define BITCLR(x) .mask = x, .result = 0
58 #define BITSET(x) .mask = x, .result = x
59 #define MCGMASK(x, y) .mcgmask = x, .mcgres = y
60 #define MASK(x, y) .mask = x, .result = y
61 #define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S)
62 #define MCI_UC_AR (MCI_STATUS_UC|MCI_STATUS_AR)
63 #define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR)
64 #define MCI_ADDR (MCI_STATUS_ADDRV|MCI_STATUS_MISCV)
68 BITCLR(MCI_STATUS_VAL)
72 EXCP, BITCLR(MCI_STATUS_EN)
75 PANIC, "Processor context corrupt",
76 BITSET(MCI_STATUS_PCC)
78 /* When MCIP is not set something is very confused */
80 PANIC, "MCIP not set in MCA handler",
81 EXCP, MCGMASK(MCG_STATUS_MCIP, 0)
83 /* Neither return not error IP -- no chance to recover -> PANIC */
85 PANIC, "Neither restart nor error IP",
86 EXCP, MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0)
89 PANIC, "In kernel and no restart IP",
90 EXCP, KERNEL, MCGMASK(MCG_STATUS_RIPV, 0)
93 PANIC, "In kernel and no restart IP",
94 EXCP, KERNEL_RECOV, MCGMASK(MCG_STATUS_RIPV, 0)
97 DEFERRED, "Deferred error",
98 NOSER, MASK(MCI_STATUS_UC|MCI_STATUS_DEFERRED|MCI_STATUS_POISON, MCI_STATUS_DEFERRED)
101 KEEP, "Corrected error",
102 NOSER, BITCLR(MCI_STATUS_UC)
106 * known AO MCACODs reported via MCE or CMC:
108 * SRAO could be signaled either via a machine check exception or
109 * CMCI with the corresponding bit S 1 or 0. So we don't need to
110 * check bit S for SRAO.
113 AO, "Action optional: memory scrubbing error",
114 SER, MASK(MCI_STATUS_OVER|MCI_UC_AR|MCACOD_SCRUBMSK, MCI_STATUS_UC|MCACOD_SCRUB)
117 AO, "Action optional: last level cache writeback error",
118 SER, MASK(MCI_STATUS_OVER|MCI_UC_AR|MCACOD, MCI_STATUS_UC|MCACOD_L3WB)
121 /* ignore OVER for UCNA */
123 UCNA, "Uncorrected no action required",
124 SER, MASK(MCI_UC_SAR, MCI_STATUS_UC)
127 PANIC, "Illegal combination (UCNA with AR=1)",
129 MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR)
132 KEEP, "Non signalled machine check",
133 SER, BITCLR(MCI_STATUS_S)
137 PANIC, "Action required with lost events",
138 SER, BITSET(MCI_STATUS_OVER|MCI_UC_SAR)
141 /* known AR MCACODs: */
142 #ifdef CONFIG_MEMORY_FAILURE
144 KEEP, "Action required but unaffected thread is continuable",
145 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR, MCI_UC_SAR|MCI_ADDR),
146 MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, MCG_STATUS_RIPV)
149 AR, "Action required: data load in error recoverable area of kernel",
150 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
154 AR, "Action required: data load error in a user process",
155 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
159 AR, "Action required: instruction fetch error in a user process",
160 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
164 PANIC, "Data load in unrecoverable area of kernel",
165 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
169 PANIC, "Instruction fetch error in kernel",
170 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
175 PANIC, "Action required: unknown MCACOD",
176 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_SAR)
180 SOME, "Action optional: unknown MCACOD",
181 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S)
184 SOME, "Action optional with lost events",
185 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_OVER|MCI_UC_S)
189 PANIC, "Overflowed uncorrected",
190 BITSET(MCI_STATUS_OVER|MCI_STATUS_UC)
194 BITSET(MCI_STATUS_UC)
199 ) /* always matches. keep at end */
202 #define mc_recoverable(mcg) (((mcg) & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) == \
203 (MCG_STATUS_RIPV|MCG_STATUS_EIPV))
206 * If mcgstatus indicated that ip/cs on the stack were
207 * no good, then "m->cs" will be zero and we will have
208 * to assume the worst case (IN_KERNEL) as we actually
209 * have no idea what we were executing when the machine
211 * If we do have a good "m->cs" (or a faked one in the
212 * case we were executing in VM86 mode) we can use it to
213 * distinguish an exception taken in user from from one
214 * taken in the kernel.
216 static int error_context(struct mce *m)
218 if ((m->cs & 3) == 3)
220 if (mc_recoverable(m->mcgstatus) && ex_has_fault_handler(m->ip))
221 return IN_KERNEL_RECOV;
225 static int mce_severity_amd_smca(struct mce *m, enum context err_ctx)
227 u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
231 * We need to look at the following bits:
232 * - "succor" bit (data poisoning support), and
233 * - TCC bit (Task Context Corrupt)
234 * in MCi_STATUS to determine error severity.
236 if (!mce_flags.succor)
237 return MCE_PANIC_SEVERITY;
239 if (rdmsr_safe(addr, &low, &high))
240 return MCE_PANIC_SEVERITY;
242 /* TCC (Task context corrupt). If set and if IN_KERNEL, panic. */
243 if ((low & MCI_CONFIG_MCAX) &&
244 (m->status & MCI_STATUS_TCC) &&
245 (err_ctx == IN_KERNEL))
246 return MCE_PANIC_SEVERITY;
248 /* ...otherwise invoke hwpoison handler. */
249 return MCE_AR_SEVERITY;
253 * See AMD Error Scope Hierarchy table in a newer BKDG. For example
254 * 49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features"
256 static int mce_severity_amd(struct mce *m, int tolerant, char **msg, bool is_excp)
258 enum context ctx = error_context(m);
260 /* Processor Context Corrupt, no need to fumble too much, die! */
261 if (m->status & MCI_STATUS_PCC)
262 return MCE_PANIC_SEVERITY;
264 if (m->status & MCI_STATUS_UC) {
266 if (ctx == IN_KERNEL)
267 return MCE_PANIC_SEVERITY;
270 * On older systems where overflow_recov flag is not present, we
271 * should simply panic if an error overflow occurs. If
272 * overflow_recov flag is present and set, then software can try
273 * to at least kill process to prolong system operation.
275 if (mce_flags.overflow_recov) {
277 return mce_severity_amd_smca(m, ctx);
279 /* kill current process */
280 return MCE_AR_SEVERITY;
282 /* at least one error was not logged */
283 if (m->status & MCI_STATUS_OVER)
284 return MCE_PANIC_SEVERITY;
288 * For any other case, return MCE_UC_SEVERITY so that we log the
289 * error and exit #MC handler.
291 return MCE_UC_SEVERITY;
295 * deferred error: poll handler catches these and adds to mce_ring so
296 * memory-failure can take recovery actions.
298 if (m->status & MCI_STATUS_DEFERRED)
299 return MCE_DEFERRED_SEVERITY;
302 * corrected error: poll handler catches these and passes responsibility
303 * of decoding the error to EDAC
305 return MCE_KEEP_SEVERITY;
308 static int mce_severity_intel(struct mce *m, int tolerant, char **msg, bool is_excp)
310 enum exception excp = (is_excp ? EXCP_CONTEXT : NO_EXCP);
311 enum context ctx = error_context(m);
314 for (s = severities;; s++) {
315 if ((m->status & s->mask) != s->result)
317 if ((m->mcgstatus & s->mcgmask) != s->mcgres)
319 if (s->ser == SER_REQUIRED && !mca_cfg.ser)
321 if (s->ser == NO_SER && mca_cfg.ser)
323 if (s->context && ctx != s->context)
325 if (s->excp && excp != s->excp)
330 if (s->sev >= MCE_UC_SEVERITY && ctx == IN_KERNEL) {
332 return MCE_PANIC_SEVERITY;
338 /* Default to mce_severity_intel */
339 int (*mce_severity)(struct mce *m, int tolerant, char **msg, bool is_excp) =
342 void __init mcheck_vendor_init_severity(void)
344 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
345 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
346 mce_severity = mce_severity_amd;
349 #ifdef CONFIG_DEBUG_FS
350 static void *s_start(struct seq_file *f, loff_t *pos)
352 if (*pos >= ARRAY_SIZE(severities))
354 return &severities[*pos];
357 static void *s_next(struct seq_file *f, void *data, loff_t *pos)
359 if (++(*pos) >= ARRAY_SIZE(severities))
361 return &severities[*pos];
364 static void s_stop(struct seq_file *f, void *data)
368 static int s_show(struct seq_file *f, void *data)
370 struct severity *ser = data;
371 seq_printf(f, "%d\t%s\n", ser->covered, ser->msg);
375 static const struct seq_operations severities_seq_ops = {
382 static int severities_coverage_open(struct inode *inode, struct file *file)
384 return seq_open(file, &severities_seq_ops);
387 static ssize_t severities_coverage_write(struct file *file,
388 const char __user *ubuf,
389 size_t count, loff_t *ppos)
392 for (i = 0; i < ARRAY_SIZE(severities); i++)
393 severities[i].covered = 0;
397 static const struct file_operations severities_coverage_fops = {
398 .open = severities_coverage_open,
399 .release = seq_release,
401 .write = severities_coverage_write,
405 static int __init severities_debugfs_init(void)
407 struct dentry *dmce, *fsev;
409 dmce = mce_get_debugfs_dir();
413 fsev = debugfs_create_file("severities-coverage", 0444, dmce, NULL,
414 &severities_coverage_fops);
423 late_initcall(severities_debugfs_init);
424 #endif /* CONFIG_DEBUG_FS */