1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2008, 2009 Intel Corporation.
8 #include <linux/kernel.h>
9 #include <linux/seq_file.h>
10 #include <linux/init.h>
11 #include <linux/debugfs.h>
12 #include <linux/uaccess.h>
15 #include <asm/intel-family.h>
16 #include <asm/traps.h>
18 #include <asm/insn-eval.h>
23 * Grade an mce by severity. In general the most severe ones are processed
24 * first. Since there are quite a lot of combinations test the bits in a
25 * table-driven way. The rules are simply processed in order, first
28 * Note this is only used for machine check exceptions, the corrected
29 * errors use much simpler rules. The exceptions still check for the corrected
30 * errors, but only to leave them alone for the CMCI handler (except for
34 enum context { IN_KERNEL = 1, IN_USER = 2, IN_KERNEL_RECOV = 3 };
35 enum ser { SER_REQUIRED = 1, NO_SER = 2 };
36 enum exception { EXCP_CONTEXT = 1, NO_EXCP = 2 };
38 static struct severity {
42 unsigned char mcgmask;
45 unsigned char context;
47 unsigned char covered;
48 unsigned char cpu_model;
49 unsigned char cpu_minstepping;
50 unsigned char bank_lo, bank_hi;
53 #define MCESEV(s, m, c...) { .sev = MCE_ ## s ## _SEVERITY, .msg = m, ## c }
54 #define BANK_RANGE(l, h) .bank_lo = l, .bank_hi = h
55 #define MODEL_STEPPING(m, s) .cpu_model = m, .cpu_minstepping = s
56 #define KERNEL .context = IN_KERNEL
57 #define USER .context = IN_USER
58 #define KERNEL_RECOV .context = IN_KERNEL_RECOV
59 #define SER .ser = SER_REQUIRED
60 #define NOSER .ser = NO_SER
61 #define EXCP .excp = EXCP_CONTEXT
62 #define NOEXCP .excp = NO_EXCP
63 #define BITCLR(x) .mask = x, .result = 0
64 #define BITSET(x) .mask = x, .result = x
65 #define MCGMASK(x, y) .mcgmask = x, .mcgres = y
66 #define MASK(x, y) .mask = x, .result = y
67 #define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S)
68 #define MCI_UC_AR (MCI_STATUS_UC|MCI_STATUS_AR)
69 #define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR)
70 #define MCI_ADDR (MCI_STATUS_ADDRV|MCI_STATUS_MISCV)
74 BITCLR(MCI_STATUS_VAL)
78 EXCP, BITCLR(MCI_STATUS_EN)
81 PANIC, "Processor context corrupt",
82 BITSET(MCI_STATUS_PCC)
84 /* When MCIP is not set something is very confused */
86 PANIC, "MCIP not set in MCA handler",
87 EXCP, MCGMASK(MCG_STATUS_MCIP, 0)
89 /* Neither return not error IP -- no chance to recover -> PANIC */
91 PANIC, "Neither restart nor error IP",
92 EXCP, MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0)
95 PANIC, "In kernel and no restart IP",
96 EXCP, KERNEL, MCGMASK(MCG_STATUS_RIPV, 0)
99 PANIC, "In kernel and no restart IP",
100 EXCP, KERNEL_RECOV, MCGMASK(MCG_STATUS_RIPV, 0)
103 KEEP, "Corrected error",
104 NOSER, BITCLR(MCI_STATUS_UC)
107 * known AO MCACODs reported via MCE or CMC:
109 * SRAO could be signaled either via a machine check exception or
110 * CMCI with the corresponding bit S 1 or 0. So we don't need to
111 * check bit S for SRAO.
114 AO, "Action optional: memory scrubbing error",
115 SER, MASK(MCI_UC_AR|MCACOD_SCRUBMSK, MCI_STATUS_UC|MCACOD_SCRUB)
118 AO, "Action optional: last level cache writeback error",
119 SER, MASK(MCI_UC_AR|MCACOD, MCI_STATUS_UC|MCACOD_L3WB)
122 * Quirk for Skylake/Cascade Lake. Patrol scrubber may be configured
123 * to report uncorrected errors using CMCI with a special signature.
124 * UC=0, MSCOD=0x0010, MCACOD=binary(000X 0000 1100 XXXX) reported
125 * in one of the memory controller banks.
126 * Set severity to "AO" for same action as normal patrol scrub error.
129 AO, "Uncorrected Patrol Scrub Error",
130 SER, MASK(MCI_STATUS_UC|MCI_ADDR|0xffffeff0, MCI_ADDR|0x001000c0),
131 MODEL_STEPPING(INTEL_FAM6_SKYLAKE_X, 4), BANK_RANGE(13, 18)
134 /* ignore OVER for UCNA */
136 UCNA, "Uncorrected no action required",
137 SER, MASK(MCI_UC_SAR, MCI_STATUS_UC)
140 PANIC, "Illegal combination (UCNA with AR=1)",
142 MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR)
145 KEEP, "Non signaled machine check",
146 SER, BITCLR(MCI_STATUS_S)
150 PANIC, "Action required with lost events",
151 SER, BITSET(MCI_STATUS_OVER|MCI_UC_SAR)
154 /* known AR MCACODs: */
155 #ifdef CONFIG_MEMORY_FAILURE
157 KEEP, "Action required but unaffected thread is continuable",
158 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR, MCI_UC_SAR|MCI_ADDR),
159 MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, MCG_STATUS_RIPV)
162 AR, "Action required: data load in error recoverable area of kernel",
163 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
167 AR, "Action required: data load error in a user process",
168 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
172 AR, "Action required: instruction fetch error in a user process",
173 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
177 PANIC, "Data load in unrecoverable area of kernel",
178 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
182 PANIC, "Instruction fetch error in kernel",
183 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
188 PANIC, "Action required: unknown MCACOD",
189 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_SAR)
193 SOME, "Action optional: unknown MCACOD",
194 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S)
197 SOME, "Action optional with lost events",
198 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_OVER|MCI_UC_S)
202 PANIC, "Overflowed uncorrected",
203 BITSET(MCI_STATUS_OVER|MCI_STATUS_UC)
207 BITSET(MCI_STATUS_UC)
212 ) /* always matches. keep at end */
215 #define mc_recoverable(mcg) (((mcg) & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) == \
216 (MCG_STATUS_RIPV|MCG_STATUS_EIPV))
218 static bool is_copy_from_user(struct pt_regs *regs)
220 u8 insn_buf[MAX_INSN_SIZE];
228 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip, MAX_INSN_SIZE))
231 ret = insn_decode_kernel(&insn, insn_buf);
235 switch (insn.opcode.value) {
237 case 0x8A: case 0x8B:
239 case 0xB60F: case 0xB70F:
240 addr = (unsigned long)insn_get_addr_ref(&insn, regs);
243 case 0xA4: case 0xA5:
250 if (fault_in_kernel_space(addr))
253 current->mce_vaddr = (void __user *)addr;
259 * If mcgstatus indicated that ip/cs on the stack were
260 * no good, then "m->cs" will be zero and we will have
261 * to assume the worst case (IN_KERNEL) as we actually
262 * have no idea what we were executing when the machine
264 * If we do have a good "m->cs" (or a faked one in the
265 * case we were executing in VM86 mode) we can use it to
266 * distinguish an exception taken in user from from one
267 * taken in the kernel.
269 static noinstr int error_context(struct mce *m, struct pt_regs *regs)
274 if ((m->cs & 3) == 3)
277 if (!mc_recoverable(m->mcgstatus))
280 /* Allow instrumentation around external facilities usage. */
281 instrumentation_begin();
282 fixup_type = ex_get_fixup_type(m->ip);
283 copy_user = is_copy_from_user(regs);
284 instrumentation_end();
286 switch (fixup_type) {
287 case EX_TYPE_UACCESS:
291 m->kflags |= MCE_IN_KERNEL_COPYIN;
294 case EX_TYPE_FAULT_MCE_SAFE:
295 case EX_TYPE_DEFAULT_MCE_SAFE:
296 m->kflags |= MCE_IN_KERNEL_RECOV;
297 return IN_KERNEL_RECOV;
304 /* See AMD PPR(s) section Machine Check Error Handling. */
305 static noinstr int mce_severity_amd(struct mce *m, struct pt_regs *regs, char **msg, bool is_excp)
307 char *panic_msg = NULL;
311 * Default return value: Action required, the error must be handled
314 ret = MCE_AR_SEVERITY;
316 /* Processor Context Corrupt, no need to fumble too much, die! */
317 if (m->status & MCI_STATUS_PCC) {
318 panic_msg = "Processor Context Corrupt";
319 ret = MCE_PANIC_SEVERITY;
323 if (m->status & MCI_STATUS_DEFERRED) {
324 ret = MCE_DEFERRED_SEVERITY;
329 * If the UC bit is not set, the system either corrected or deferred
330 * the error. No action will be required after logging the error.
332 if (!(m->status & MCI_STATUS_UC)) {
333 ret = MCE_KEEP_SEVERITY;
338 * On MCA overflow, without the MCA overflow recovery feature the
339 * system will not be able to recover, panic.
341 if ((m->status & MCI_STATUS_OVER) && !mce_flags.overflow_recov) {
342 panic_msg = "Overflowed uncorrected error without MCA Overflow Recovery";
343 ret = MCE_PANIC_SEVERITY;
347 if (!mce_flags.succor) {
348 panic_msg = "Uncorrected error without MCA Recovery";
349 ret = MCE_PANIC_SEVERITY;
353 if (error_context(m, regs) == IN_KERNEL) {
354 panic_msg = "Uncorrected unrecoverable error in kernel context";
355 ret = MCE_PANIC_SEVERITY;
359 if (msg && panic_msg)
365 static noinstr int mce_severity_intel(struct mce *m, struct pt_regs *regs, char **msg, bool is_excp)
367 enum exception excp = (is_excp ? EXCP_CONTEXT : NO_EXCP);
368 enum context ctx = error_context(m, regs);
371 for (s = severities;; s++) {
372 if ((m->status & s->mask) != s->result)
374 if ((m->mcgstatus & s->mcgmask) != s->mcgres)
376 if (s->ser == SER_REQUIRED && !mca_cfg.ser)
378 if (s->ser == NO_SER && mca_cfg.ser)
380 if (s->context && ctx != s->context)
382 if (s->excp && excp != s->excp)
384 if (s->cpu_model && boot_cpu_data.x86_model != s->cpu_model)
386 if (s->cpu_minstepping && boot_cpu_data.x86_stepping < s->cpu_minstepping)
388 if (s->bank_lo && (m->bank < s->bank_lo || m->bank > s->bank_hi))
394 if (s->sev >= MCE_UC_SEVERITY && ctx == IN_KERNEL)
395 return MCE_PANIC_SEVERITY;
401 int noinstr mce_severity(struct mce *m, struct pt_regs *regs, char **msg, bool is_excp)
403 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
404 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
405 return mce_severity_amd(m, regs, msg, is_excp);
407 return mce_severity_intel(m, regs, msg, is_excp);
410 #ifdef CONFIG_DEBUG_FS
411 static void *s_start(struct seq_file *f, loff_t *pos)
413 if (*pos >= ARRAY_SIZE(severities))
415 return &severities[*pos];
418 static void *s_next(struct seq_file *f, void *data, loff_t *pos)
420 if (++(*pos) >= ARRAY_SIZE(severities))
422 return &severities[*pos];
425 static void s_stop(struct seq_file *f, void *data)
429 static int s_show(struct seq_file *f, void *data)
431 struct severity *ser = data;
432 seq_printf(f, "%d\t%s\n", ser->covered, ser->msg);
436 static const struct seq_operations severities_seq_ops = {
443 static int severities_coverage_open(struct inode *inode, struct file *file)
445 return seq_open(file, &severities_seq_ops);
448 static ssize_t severities_coverage_write(struct file *file,
449 const char __user *ubuf,
450 size_t count, loff_t *ppos)
453 for (i = 0; i < ARRAY_SIZE(severities); i++)
454 severities[i].covered = 0;
458 static const struct file_operations severities_coverage_fops = {
459 .open = severities_coverage_open,
460 .release = seq_release,
462 .write = severities_coverage_write,
466 static int __init severities_debugfs_init(void)
470 dmce = mce_get_debugfs_dir();
472 debugfs_create_file("severities-coverage", 0444, dmce, NULL,
473 &severities_coverage_fops);
476 late_initcall(severities_debugfs_init);
477 #endif /* CONFIG_DEBUG_FS */