1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __X86_MCE_INTERNAL_H__
3 #define __X86_MCE_INTERNAL_H__
6 #define pr_fmt(fmt) "mce: " fmt
8 #include <linux/device.h>
11 /* Pointer to the installed machine check handler for this CPU setup. */
12 extern void (*machine_check_vector)(struct pt_regs *);
16 MCE_DEFERRED_SEVERITY,
17 MCE_UCNA_SEVERITY = MCE_DEFERRED_SEVERITY,
26 extern struct blocking_notifier_head x86_mce_decoder_chain;
28 #define INITIAL_CHECK_INTERVAL 5 * 60 /* 5 minutes */
30 struct mce_evt_llist {
31 struct llist_node llnode;
35 void mce_gen_pool_process(struct work_struct *__unused);
36 bool mce_gen_pool_empty(void);
37 int mce_gen_pool_add(struct mce *mce);
38 int mce_gen_pool_init(void);
39 struct llist_node *mce_gen_pool_prepare_records(void);
41 extern int (*mce_severity)(struct mce *a, struct pt_regs *regs,
42 int tolerant, char **msg, bool is_excp);
43 struct dentry *mce_get_debugfs_dir(void);
45 extern mce_banks_t mce_banks_ce_disabled;
47 #ifdef CONFIG_X86_MCE_INTEL
48 unsigned long cmci_intel_adjust_timer(unsigned long interval);
49 bool mce_intel_cmci_poll(void);
50 void mce_intel_hcpu_update(unsigned long cpu);
51 void cmci_disable_bank(int bank);
52 void intel_init_cmci(void);
53 void intel_init_lmce(void);
54 void intel_clear_lmce(void);
55 bool intel_filter_mce(struct mce *m);
57 # define cmci_intel_adjust_timer mce_adjust_timer_default
58 static inline bool mce_intel_cmci_poll(void) { return false; }
59 static inline void mce_intel_hcpu_update(unsigned long cpu) { }
60 static inline void cmci_disable_bank(int bank) { }
61 static inline void intel_init_cmci(void) { }
62 static inline void intel_init_lmce(void) { }
63 static inline void intel_clear_lmce(void) { }
64 static inline bool intel_filter_mce(struct mce *m) { return false; };
67 void mce_timer_kick(unsigned long interval);
69 #ifdef CONFIG_ACPI_APEI
70 int apei_write_mce(struct mce *m);
71 ssize_t apei_read_mce(struct mce *m, u64 *record_id);
72 int apei_check_mce(void);
73 int apei_clear_mce(u64 record_id);
75 static inline int apei_write_mce(struct mce *m)
79 static inline ssize_t apei_read_mce(struct mce *m, u64 *record_id)
83 static inline int apei_check_mce(void)
87 static inline int apei_clear_mce(u64 record_id)
94 * We consider records to be equivalent if bank+status+addr+misc all match.
95 * This is only used when the system is going down because of a fatal error
96 * to avoid cluttering the console log with essentially repeated information.
97 * In normal processing all errors seen are logged.
99 static inline bool mce_cmp(struct mce *m1, struct mce *m2)
101 return m1->bank != m2->bank ||
102 m1->status != m2->status ||
103 m1->addr != m2->addr ||
104 m1->misc != m2->misc;
107 extern struct device_attribute dev_attr_trigger;
109 #ifdef CONFIG_X86_MCELOG_LEGACY
110 void mce_work_trigger(void);
111 void mce_register_injector_chain(struct notifier_block *nb);
112 void mce_unregister_injector_chain(struct notifier_block *nb);
114 static inline void mce_work_trigger(void) { }
115 static inline void mce_register_injector_chain(struct notifier_block *nb) { }
116 static inline void mce_unregister_injector_chain(struct notifier_block *nb) { }
125 __u64 lmce_disabled : 1,
129 bios_cmci_threshold : 1,
139 extern struct mca_config mca_cfg;
140 DECLARE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
142 struct mce_vendor_flags {
144 * Indicates that overflow conditions are not fatal, when set.
146 __u64 overflow_recov : 1,
149 * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
150 * Recovery. It indicates support for data poisoning in HW and deferred
156 * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
157 * the register space for each MCA bank and also increases number of
158 * banks. Also, to accommodate the new banks and registers, the MCA
159 * register space is moved to a new MSR range.
163 /* AMD-style error thresholding banks present. */
169 extern struct mce_vendor_flags mce_flags;
171 struct mca_msr_regs {
172 u32 (*ctl) (int bank);
173 u32 (*status) (int bank);
174 u32 (*addr) (int bank);
175 u32 (*misc) (int bank);
178 extern struct mca_msr_regs msr_ops;
180 /* Decide whether to add MCE record to MCE event pool or filter it out. */
181 extern bool filter_mce(struct mce *m);
183 #ifdef CONFIG_X86_MCE_AMD
184 extern bool amd_filter_mce(struct mce *m);
186 static inline bool amd_filter_mce(struct mce *m) { return false; };
189 __visible bool ex_handler_rdmsr_fault(const struct exception_table_entry *fixup,
190 struct pt_regs *regs, int trapnr,
191 unsigned long error_code,
192 unsigned long fault_addr);
194 __visible bool ex_handler_wrmsr_fault(const struct exception_table_entry *fixup,
195 struct pt_regs *regs, int trapnr,
196 unsigned long error_code,
197 unsigned long fault_addr);
199 #endif /* __X86_MCE_INTERNAL_H__ */