1 // SPDX-License-Identifier: GPL-2.0-only
3 * Machine check handler.
5 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
6 * Rest from unknown author(s).
7 * 2004 Andi Kleen. Rewrote most of it.
8 * Copyright 2008 Intel Corporation
12 #include <linux/thread_info.h>
13 #include <linux/capability.h>
14 #include <linux/miscdevice.h>
15 #include <linux/ratelimit.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/device.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/delay.h>
26 #include <linux/ctype.h>
27 #include <linux/sched.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/kmod.h>
33 #include <linux/poll.h>
34 #include <linux/nmi.h>
35 #include <linux/cpu.h>
36 #include <linux/ras.h>
37 #include <linux/smp.h>
40 #include <linux/debugfs.h>
41 #include <linux/irq_work.h>
42 #include <linux/export.h>
43 #include <linux/set_memory.h>
44 #include <linux/sync_core.h>
45 #include <linux/task_work.h>
46 #include <linux/hardirq.h>
48 #include <asm/intel-family.h>
49 #include <asm/processor.h>
50 #include <asm/traps.h>
51 #include <asm/tlbflush.h>
54 #include <asm/reboot.h>
58 /* sysfs synchronization */
59 static DEFINE_MUTEX(mce_sysfs_mutex);
61 #define CREATE_TRACE_POINTS
62 #include <trace/events/mce.h>
64 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
68 DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
71 u64 ctl; /* subevents to enable */
72 bool init; /* initialise bank? */
74 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
77 /* One object for each MCE bank, shared by all CPUs */
79 struct device_attribute attr; /* device attribute */
80 char attrname[ATTR_LEN]; /* attribute name */
81 u8 bank; /* bank number */
83 static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS];
85 struct mce_vendor_flags mce_flags __read_mostly;
87 struct mca_config mca_cfg __read_mostly = {
91 * 0: always panic on uncorrected errors, log corrected errors
92 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
93 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
94 * 3: never panic or SIGBUS, log all errors (for testing only)
100 static DEFINE_PER_CPU(struct mce, mces_seen);
101 static unsigned long mce_need_notify;
102 static int cpu_missing;
105 * MCA banks polled by the period polling timer for corrected events.
106 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
108 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
109 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
113 * MCA banks controlled through firmware first for corrected errors.
114 * This is a global list of banks for which we won't enable CMCI and we
115 * won't poll. Firmware controls these banks and is responsible for
116 * reporting corrected errors through GHES. Uncorrected/recoverable
117 * errors are still notified through a machine check.
119 mce_banks_t mce_banks_ce_disabled;
121 static struct work_struct mce_work;
122 static struct irq_work mce_irq_work;
124 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
127 * CPU/chipset specific EDAC code can register a notifier call here to print
128 * MCE errors in a human-readable form.
130 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
132 /* Do initial initialization of a struct mce */
133 noinstr void mce_setup(struct mce *m)
135 memset(m, 0, sizeof(struct mce));
136 m->cpu = m->extcpu = smp_processor_id();
137 /* need the internal __ version to avoid deadlocks */
138 m->time = __ktime_get_real_seconds();
139 m->cpuvendor = boot_cpu_data.x86_vendor;
140 m->cpuid = cpuid_eax(1);
141 m->socketid = cpu_data(m->extcpu).phys_proc_id;
142 m->apicid = cpu_data(m->extcpu).initial_apicid;
143 m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP);
145 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
146 m->ppin = __rdmsr(MSR_PPIN);
147 else if (this_cpu_has(X86_FEATURE_AMD_PPIN))
148 m->ppin = __rdmsr(MSR_AMD_PPIN);
150 m->microcode = boot_cpu_data.microcode;
153 DEFINE_PER_CPU(struct mce, injectm);
154 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
156 void mce_log(struct mce *m)
158 if (!mce_gen_pool_add(m))
159 irq_work_queue(&mce_irq_work);
161 EXPORT_SYMBOL_GPL(mce_log);
163 void mce_register_decode_chain(struct notifier_block *nb)
165 if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC))
168 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
170 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
172 void mce_unregister_decode_chain(struct notifier_block *nb)
174 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
176 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
178 static inline u32 ctl_reg(int bank)
180 return MSR_IA32_MCx_CTL(bank);
183 static inline u32 status_reg(int bank)
185 return MSR_IA32_MCx_STATUS(bank);
188 static inline u32 addr_reg(int bank)
190 return MSR_IA32_MCx_ADDR(bank);
193 static inline u32 misc_reg(int bank)
195 return MSR_IA32_MCx_MISC(bank);
198 static inline u32 smca_ctl_reg(int bank)
200 return MSR_AMD64_SMCA_MCx_CTL(bank);
203 static inline u32 smca_status_reg(int bank)
205 return MSR_AMD64_SMCA_MCx_STATUS(bank);
208 static inline u32 smca_addr_reg(int bank)
210 return MSR_AMD64_SMCA_MCx_ADDR(bank);
213 static inline u32 smca_misc_reg(int bank)
215 return MSR_AMD64_SMCA_MCx_MISC(bank);
218 struct mca_msr_regs msr_ops = {
220 .status = status_reg,
225 static void __print_mce(struct mce *m)
227 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
229 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
230 m->mcgstatus, m->bank, m->status);
233 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
234 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
237 if (m->cs == __KERNEL_CS)
238 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
242 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
244 pr_cont("ADDR %llx ", m->addr);
246 pr_cont("MISC %llx ", m->misc);
248 pr_cont("PPIN %llx ", m->ppin);
250 if (mce_flags.smca) {
252 pr_cont("SYND %llx ", m->synd);
254 pr_cont("IPID %llx ", m->ipid);
260 * Note this output is parsed by external tools and old fields
261 * should not be changed.
263 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
264 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
268 static void print_mce(struct mce *m)
272 if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
273 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
276 #define PANIC_TIMEOUT 5 /* 5 seconds */
278 static atomic_t mce_panicked;
280 static int fake_panic;
281 static atomic_t mce_fake_panicked;
283 /* Panic in progress. Enable interrupts and wait for final IPI */
284 static void wait_for_panic(void)
286 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
290 while (timeout-- > 0)
292 if (panic_timeout == 0)
293 panic_timeout = mca_cfg.panic_timeout;
294 panic("Panicing machine check CPU died");
297 static void mce_panic(const char *msg, struct mce *final, char *exp)
300 struct llist_node *pending;
301 struct mce_evt_llist *l;
305 * Make sure only one CPU runs in machine check panic
307 if (atomic_inc_return(&mce_panicked) > 1)
314 /* Don't log too much for fake panic */
315 if (atomic_inc_return(&mce_fake_panicked) > 1)
318 pending = mce_gen_pool_prepare_records();
319 /* First print corrected ones that are still unlogged */
320 llist_for_each_entry(l, pending, llnode) {
321 struct mce *m = &l->mce;
322 if (!(m->status & MCI_STATUS_UC)) {
325 apei_err = apei_write_mce(m);
328 /* Now print uncorrected but with the final one last */
329 llist_for_each_entry(l, pending, llnode) {
330 struct mce *m = &l->mce;
331 if (!(m->status & MCI_STATUS_UC))
333 if (!final || mce_cmp(m, final)) {
336 apei_err = apei_write_mce(m);
342 apei_err = apei_write_mce(final);
345 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
347 pr_emerg(HW_ERR "Machine check: %s\n", exp);
349 if (panic_timeout == 0)
350 panic_timeout = mca_cfg.panic_timeout;
353 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
356 /* Support code for software error injection */
358 static int msr_to_offset(u32 msr)
360 unsigned bank = __this_cpu_read(injectm.bank);
362 if (msr == mca_cfg.rip_msr)
363 return offsetof(struct mce, ip);
364 if (msr == msr_ops.status(bank))
365 return offsetof(struct mce, status);
366 if (msr == msr_ops.addr(bank))
367 return offsetof(struct mce, addr);
368 if (msr == msr_ops.misc(bank))
369 return offsetof(struct mce, misc);
370 if (msr == MSR_IA32_MCG_STATUS)
371 return offsetof(struct mce, mcgstatus);
375 __visible bool ex_handler_rdmsr_fault(const struct exception_table_entry *fixup,
376 struct pt_regs *regs, int trapnr,
377 unsigned long error_code,
378 unsigned long fault_addr)
380 pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n",
381 (unsigned int)regs->cx, regs->ip, (void *)regs->ip);
383 show_stack_regs(regs);
385 panic("MCA architectural violation!\n");
393 /* MSR access wrappers used for error injection */
394 static noinstr u64 mce_rdmsrl(u32 msr)
396 DECLARE_ARGS(val, low, high);
398 if (__this_cpu_read(injectm.finished)) {
402 instrumentation_begin();
404 offset = msr_to_offset(msr);
408 ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
410 instrumentation_end();
416 * RDMSR on MCA MSRs should not fault. If they do, this is very much an
417 * architectural violation and needs to be reported to hw vendor. Panic
418 * the box to not allow any further progress.
420 asm volatile("1: rdmsr\n"
422 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_rdmsr_fault)
423 : EAX_EDX_RET(val, low, high) : "c" (msr));
426 return EAX_EDX_VAL(val, low, high);
429 __visible bool ex_handler_wrmsr_fault(const struct exception_table_entry *fixup,
430 struct pt_regs *regs, int trapnr,
431 unsigned long error_code,
432 unsigned long fault_addr)
434 pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n",
435 (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax,
436 regs->ip, (void *)regs->ip);
438 show_stack_regs(regs);
440 panic("MCA architectural violation!\n");
448 static noinstr void mce_wrmsrl(u32 msr, u64 v)
452 if (__this_cpu_read(injectm.finished)) {
455 instrumentation_begin();
457 offset = msr_to_offset(msr);
459 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
461 instrumentation_end();
467 high = (u32)(v >> 32);
469 /* See comment in mce_rdmsrl() */
470 asm volatile("1: wrmsr\n"
472 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_fault)
473 : : "c" (msr), "a"(low), "d" (high) : "memory");
477 * Collect all global (w.r.t. this processor) status about this machine
478 * check into our "mce" struct so that we can use it later to assess
479 * the severity of the problem as we read per-bank specific details.
481 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
485 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
488 * Get the address of the instruction at the time of
489 * the machine check error.
491 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
496 * When in VM86 mode make the cs look like ring 3
497 * always. This is a lie, but it's better than passing
498 * the additional vm86 bit around everywhere.
500 if (v8086_mode(regs))
503 /* Use accurate RIP reporting if available. */
505 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
509 int mce_available(struct cpuinfo_x86 *c)
511 if (mca_cfg.disabled)
513 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
516 static void mce_schedule_work(void)
518 if (!mce_gen_pool_empty())
519 schedule_work(&mce_work);
522 static void mce_irq_work_cb(struct irq_work *entry)
528 * Check if the address reported by the CPU is in a format we can parse.
529 * It would be possible to add code for most other cases, but all would
530 * be somewhat complicated (e.g. segment offset would require an instruction
531 * parser). So only support physical addresses up to page granuality for now.
533 int mce_usable_address(struct mce *m)
535 if (!(m->status & MCI_STATUS_ADDRV))
538 /* Checks after this one are Intel/Zhaoxin-specific: */
539 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
540 boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
543 if (!(m->status & MCI_STATUS_MISCV))
546 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
549 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
554 EXPORT_SYMBOL_GPL(mce_usable_address);
556 bool mce_is_memory_error(struct mce *m)
558 switch (m->cpuvendor) {
560 case X86_VENDOR_HYGON:
561 return amd_mce_is_memory_error(m);
563 case X86_VENDOR_INTEL:
564 case X86_VENDOR_ZHAOXIN:
566 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
568 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
569 * indicating a memory error. Bit 8 is used for indicating a
570 * cache hierarchy error. The combination of bit 2 and bit 3
571 * is used for indicating a `generic' cache hierarchy error
572 * But we can't just blindly check the above bits, because if
573 * bit 11 is set, then it is a bus/interconnect error - and
574 * either way the above bits just gives more detail on what
575 * bus/interconnect error happened. Note that bit 12 can be
576 * ignored, as it's the "filter" bit.
578 return (m->status & 0xef80) == BIT(7) ||
579 (m->status & 0xef00) == BIT(8) ||
580 (m->status & 0xeffc) == 0xc;
586 EXPORT_SYMBOL_GPL(mce_is_memory_error);
588 static bool whole_page(struct mce *m)
590 if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV))
593 return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT;
596 bool mce_is_correctable(struct mce *m)
598 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
601 if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
604 if (m->status & MCI_STATUS_UC)
609 EXPORT_SYMBOL_GPL(mce_is_correctable);
611 static int mce_early_notifier(struct notifier_block *nb, unsigned long val,
614 struct mce *m = (struct mce *)data;
619 /* Emit the trace record: */
622 set_bit(0, &mce_need_notify);
629 static struct notifier_block early_nb = {
630 .notifier_call = mce_early_notifier,
631 .priority = MCE_PRIO_EARLY,
634 static int uc_decode_notifier(struct notifier_block *nb, unsigned long val,
637 struct mce *mce = (struct mce *)data;
640 if (!mce || !mce_usable_address(mce))
643 if (mce->severity != MCE_AO_SEVERITY &&
644 mce->severity != MCE_DEFERRED_SEVERITY)
647 pfn = mce->addr >> PAGE_SHIFT;
648 if (!memory_failure(pfn, 0)) {
649 set_mce_nospec(pfn, whole_page(mce));
650 mce->kflags |= MCE_HANDLED_UC;
656 static struct notifier_block mce_uc_nb = {
657 .notifier_call = uc_decode_notifier,
658 .priority = MCE_PRIO_UC,
661 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
664 struct mce *m = (struct mce *)data;
669 if (mca_cfg.print_all || !m->kflags)
675 static struct notifier_block mce_default_nb = {
676 .notifier_call = mce_default_notifier,
677 /* lowest prio, we want it to run last. */
678 .priority = MCE_PRIO_LOWEST,
682 * Read ADDR and MISC registers.
684 static void mce_read_aux(struct mce *m, int i)
686 if (m->status & MCI_STATUS_MISCV)
687 m->misc = mce_rdmsrl(msr_ops.misc(i));
689 if (m->status & MCI_STATUS_ADDRV) {
690 m->addr = mce_rdmsrl(msr_ops.addr(i));
693 * Mask the reported address by the reported granularity.
695 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
696 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
702 * Extract [55:<lsb>] where lsb is the least significant
703 * *valid* bit of the address bits.
705 if (mce_flags.smca) {
706 u8 lsb = (m->addr >> 56) & 0x3f;
708 m->addr &= GENMASK_ULL(55, lsb);
712 if (mce_flags.smca) {
713 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
715 if (m->status & MCI_STATUS_SYNDV)
716 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
720 DEFINE_PER_CPU(unsigned, mce_poll_count);
723 * Poll for corrected events or events that happened before reset.
724 * Those are just logged through /dev/mcelog.
726 * This is executed in standard interrupt context.
728 * Note: spec recommends to panic for fatal unsignalled
729 * errors here. However this would be quite problematic --
730 * we would need to reimplement the Monarch handling and
731 * it would mess up the exclusion between exception handler
732 * and poll handler -- * so we skip this for now.
733 * These cases should not happen anyways, or only when the CPU
734 * is already totally * confused. In this case it's likely it will
735 * not fully execute the machine check handler either.
737 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
739 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
740 bool error_seen = false;
744 this_cpu_inc(mce_poll_count);
746 mce_gather_info(&m, NULL);
748 if (flags & MCP_TIMESTAMP)
751 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
752 if (!mce_banks[i].ctl || !test_bit(i, *b))
760 m.status = mce_rdmsrl(msr_ops.status(i));
762 /* If this entry is not valid, ignore it */
763 if (!(m.status & MCI_STATUS_VAL))
767 * If we are logging everything (at CPU online) or this
768 * is a corrected error, then we must log it.
770 if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
774 * Newer Intel systems that support software error
775 * recovery need to make additional checks. Other
776 * CPUs should skip over uncorrected errors, but log
780 if (m.status & MCI_STATUS_UC)
785 /* Log "not enabled" (speculative) errors */
786 if (!(m.status & MCI_STATUS_EN))
790 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
791 * UC == 1 && PCC == 0 && S == 0
793 if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
797 * Skip anything else. Presumption is that our read of this
798 * bank is racing with a machine check. Leave the log alone
799 * for do_machine_check() to deal with it.
806 if (flags & MCP_DONTLOG)
810 m.severity = mce_severity(&m, NULL, mca_cfg.tolerant, NULL, false);
812 * Don't get the IP here because it's unlikely to
813 * have anything to do with the actual error location.
816 if (mca_cfg.dont_log_ce && !mce_usable_address(&m))
823 * Clear state for this bank.
825 mce_wrmsrl(msr_ops.status(i), 0);
829 * Don't clear MCG_STATUS here because it's only defined for
837 EXPORT_SYMBOL_GPL(machine_check_poll);
840 * Do a quick check if any of the events requires a panic.
841 * This decides if we keep the events around or clear them.
843 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
844 struct pt_regs *regs)
849 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
850 m->status = mce_rdmsrl(msr_ops.status(i));
851 if (!(m->status & MCI_STATUS_VAL))
854 __set_bit(i, validp);
855 if (quirk_no_way_out)
856 quirk_no_way_out(i, m, regs);
859 if (mce_severity(m, regs, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
869 * Variable to establish order between CPUs while scanning.
870 * Each CPU spins initially until executing is equal its number.
872 static atomic_t mce_executing;
875 * Defines order of CPUs on entry. First CPU becomes Monarch.
877 static atomic_t mce_callin;
880 * Check if a timeout waiting for other CPUs happened.
882 static int mce_timed_out(u64 *t, const char *msg)
885 * The others already did panic for some reason.
886 * Bail out like in a timeout.
887 * rmb() to tell the compiler that system_state
888 * might have been modified by someone else.
891 if (atomic_read(&mce_panicked))
893 if (!mca_cfg.monarch_timeout)
895 if ((s64)*t < SPINUNIT) {
896 if (mca_cfg.tolerant <= 1)
897 mce_panic(msg, NULL, NULL);
903 touch_nmi_watchdog();
908 * The Monarch's reign. The Monarch is the CPU who entered
909 * the machine check handler first. It waits for the others to
910 * raise the exception too and then grades them. When any
911 * error is fatal panic. Only then let the others continue.
913 * The other CPUs entering the MCE handler will be controlled by the
914 * Monarch. They are called Subjects.
916 * This way we prevent any potential data corruption in a unrecoverable case
917 * and also makes sure always all CPU's errors are examined.
919 * Also this detects the case of a machine check event coming from outer
920 * space (not detected by any CPUs) In this case some external agent wants
921 * us to shut down, so panic too.
923 * The other CPUs might still decide to panic if the handler happens
924 * in a unrecoverable place, but in this case the system is in a semi-stable
925 * state and won't corrupt anything by itself. It's ok to let the others
926 * continue for a bit first.
928 * All the spin loops have timeouts; when a timeout happens a CPU
929 * typically elects itself to be Monarch.
931 static void mce_reign(void)
934 struct mce *m = NULL;
935 int global_worst = 0;
939 * This CPU is the Monarch and the other CPUs have run
940 * through their handlers.
941 * Grade the severity of the errors of all the CPUs.
943 for_each_possible_cpu(cpu) {
944 struct mce *mtmp = &per_cpu(mces_seen, cpu);
946 if (mtmp->severity > global_worst) {
947 global_worst = mtmp->severity;
948 m = &per_cpu(mces_seen, cpu);
953 * Cannot recover? Panic here then.
954 * This dumps all the mces in the log buffer and stops the
957 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
958 /* call mce_severity() to get "msg" for panic */
959 mce_severity(m, NULL, mca_cfg.tolerant, &msg, true);
960 mce_panic("Fatal machine check", m, msg);
964 * For UC somewhere we let the CPU who detects it handle it.
965 * Also must let continue the others, otherwise the handling
966 * CPU could deadlock on a lock.
970 * No machine check event found. Must be some external
971 * source or one CPU is hung. Panic.
973 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
974 mce_panic("Fatal machine check from unknown source", NULL, NULL);
977 * Now clear all the mces_seen so that they don't reappear on
980 for_each_possible_cpu(cpu)
981 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
984 static atomic_t global_nwo;
987 * Start of Monarch synchronization. This waits until all CPUs have
988 * entered the exception handler and then determines if any of them
989 * saw a fatal event that requires panic. Then it executes them
990 * in the entry order.
991 * TBD double check parallel CPU hotunplug
993 static int mce_start(int *no_way_out)
996 int cpus = num_online_cpus();
997 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1002 atomic_add(*no_way_out, &global_nwo);
1004 * Rely on the implied barrier below, such that global_nwo
1005 * is updated before mce_callin.
1007 order = atomic_inc_return(&mce_callin);
1010 * Wait for everyone.
1012 while (atomic_read(&mce_callin) != cpus) {
1013 if (mce_timed_out(&timeout,
1014 "Timeout: Not all CPUs entered broadcast exception handler")) {
1015 atomic_set(&global_nwo, 0);
1022 * mce_callin should be read before global_nwo
1028 * Monarch: Starts executing now, the others wait.
1030 atomic_set(&mce_executing, 1);
1033 * Subject: Now start the scanning loop one by one in
1034 * the original callin order.
1035 * This way when there are any shared banks it will be
1036 * only seen by one CPU before cleared, avoiding duplicates.
1038 while (atomic_read(&mce_executing) < order) {
1039 if (mce_timed_out(&timeout,
1040 "Timeout: Subject CPUs unable to finish machine check processing")) {
1041 atomic_set(&global_nwo, 0);
1049 * Cache the global no_way_out state.
1051 *no_way_out = atomic_read(&global_nwo);
1057 * Synchronize between CPUs after main scanning loop.
1058 * This invokes the bulk of the Monarch processing.
1060 static int mce_end(int order)
1063 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1071 * Allow others to run.
1073 atomic_inc(&mce_executing);
1076 /* CHECKME: Can this race with a parallel hotplug? */
1077 int cpus = num_online_cpus();
1080 * Monarch: Wait for everyone to go through their scanning
1083 while (atomic_read(&mce_executing) <= cpus) {
1084 if (mce_timed_out(&timeout,
1085 "Timeout: Monarch CPU unable to finish machine check processing"))
1095 * Subject: Wait for Monarch to finish.
1097 while (atomic_read(&mce_executing) != 0) {
1098 if (mce_timed_out(&timeout,
1099 "Timeout: Monarch CPU did not finish machine check processing"))
1105 * Don't reset anything. That's done by the Monarch.
1111 * Reset all global state.
1114 atomic_set(&global_nwo, 0);
1115 atomic_set(&mce_callin, 0);
1119 * Let others run again.
1121 atomic_set(&mce_executing, 0);
1125 static void mce_clear_state(unsigned long *toclear)
1129 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1130 if (test_bit(i, toclear))
1131 mce_wrmsrl(msr_ops.status(i), 0);
1136 * Cases where we avoid rendezvous handler timeout:
1137 * 1) If this CPU is offline.
1139 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1140 * skip those CPUs which remain looping in the 1st kernel - see
1141 * crash_nmi_callback().
1143 * Note: there still is a small window between kexec-ing and the new,
1144 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1145 * might not get handled properly.
1147 static noinstr bool mce_check_crashing_cpu(void)
1149 unsigned int cpu = smp_processor_id();
1151 if (arch_cpu_is_offline(cpu) ||
1152 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1155 mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS);
1157 if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
1158 if (mcgstatus & MCG_STATUS_LMCES)
1162 if (mcgstatus & MCG_STATUS_RIPV) {
1163 __wrmsr(MSR_IA32_MCG_STATUS, 0, 0);
1170 static void __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final,
1171 unsigned long *toclear, unsigned long *valid_banks,
1172 int no_way_out, int *worst)
1174 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1175 struct mca_config *cfg = &mca_cfg;
1178 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1179 __clear_bit(i, toclear);
1180 if (!test_bit(i, valid_banks))
1183 if (!mce_banks[i].ctl)
1190 m->status = mce_rdmsrl(msr_ops.status(i));
1191 if (!(m->status & MCI_STATUS_VAL))
1195 * Corrected or non-signaled errors are handled by
1196 * machine_check_poll(). Leave them alone, unless this panics.
1198 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1202 /* Set taint even when machine check was not enabled. */
1203 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1205 severity = mce_severity(m, regs, cfg->tolerant, NULL, true);
1208 * When machine check was for corrected/deferred handler don't
1209 * touch, unless we're panicking.
1211 if ((severity == MCE_KEEP_SEVERITY ||
1212 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1215 __set_bit(i, toclear);
1217 /* Machine check event was not enabled. Clear, but ignore. */
1218 if (severity == MCE_NO_SEVERITY)
1223 /* assuming valid severity level != 0 */
1224 m->severity = severity;
1228 if (severity > *worst) {
1234 /* mce_clear_state will clear *final, save locally for use later */
1238 static void kill_me_now(struct callback_head *ch)
1243 static void kill_me_maybe(struct callback_head *cb)
1245 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1246 int flags = MF_ACTION_REQUIRED;
1248 pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr);
1251 flags |= MF_MUST_KILL;
1253 if (!memory_failure(p->mce_addr >> PAGE_SHIFT, flags) &&
1254 !(p->mce_kflags & MCE_IN_KERNEL_COPYIN)) {
1255 set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page);
1260 if (p->mce_vaddr != (void __user *)-1l) {
1261 force_sig_mceerr(BUS_MCEERR_AR, p->mce_vaddr, PAGE_SHIFT);
1263 pr_err("Memory error not recovered");
1268 static void queue_task_work(struct mce *m, int kill_it)
1270 current->mce_addr = m->addr;
1271 current->mce_kflags = m->kflags;
1272 current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV);
1273 current->mce_whole_page = whole_page(m);
1276 current->mce_kill_me.func = kill_me_now;
1278 current->mce_kill_me.func = kill_me_maybe;
1280 task_work_add(current, ¤t->mce_kill_me, TWA_RESUME);
1284 * The actual machine check handler. This only handles real
1285 * exceptions when something got corrupted coming in through int 18.
1287 * This is executed in NMI context not subject to normal locking rules. This
1288 * implies that most kernel services cannot be safely used. Don't even
1289 * think about putting a printk in there!
1291 * On Intel systems this is entered on all CPUs in parallel through
1292 * MCE broadcast. However some CPUs might be broken beyond repair,
1293 * so be always careful when synchronizing with others.
1295 * Tracing and kprobes are disabled: if we interrupted a kernel context
1296 * with IF=1, we need to minimize stack usage. There are also recursion
1297 * issues: if the machine check was due to a failure of the memory
1298 * backing the user stack, tracing that reads the user stack will cause
1299 * potentially infinite recursion.
1301 noinstr void do_machine_check(struct pt_regs *regs)
1303 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1304 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1305 struct mca_config *cfg = &mca_cfg;
1306 struct mce m, *final;
1311 * Establish sequential order between the CPUs entering the machine
1317 * If no_way_out gets set, there is no safe way to recover from this
1318 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1323 * If kill_it gets set, there might be a way to recover from this
1329 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1334 this_cpu_inc(mce_exception_count);
1336 mce_gather_info(&m, regs);
1339 final = this_cpu_ptr(&mces_seen);
1342 memset(valid_banks, 0, sizeof(valid_banks));
1343 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1348 * When no restart IP might need to kill or panic.
1349 * Assume the worst for now, but if we find the
1350 * severity is MCE_AR_SEVERITY we have other options.
1352 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1356 * Check if this MCE is signaled to only this logical processor,
1357 * on Intel, Zhaoxin only.
1359 if (m.cpuvendor == X86_VENDOR_INTEL ||
1360 m.cpuvendor == X86_VENDOR_ZHAOXIN)
1361 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1364 * Local machine check may already know that we have to panic.
1365 * Broadcast machine check begins rendezvous in mce_start()
1366 * Go through all banks in exclusion of the other CPUs. This way we
1367 * don't report duplicated events on shared banks because the first one
1368 * to see it will clear it.
1372 mce_panic("Fatal local machine check", &m, msg);
1374 order = mce_start(&no_way_out);
1377 __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst);
1380 mce_clear_state(toclear);
1383 * Do most of the synchronization with other CPUs.
1384 * When there's any problem use only local no_way_out state.
1387 if (mce_end(order) < 0)
1388 no_way_out = worst >= MCE_PANIC_SEVERITY;
1391 * If there was a fatal machine check we should have
1392 * already called mce_panic earlier in this function.
1393 * Since we re-read the banks, we might have found
1394 * something new. Check again to see if we found a
1395 * fatal error. We call "mce_severity()" again to
1396 * make sure we have the right "msg".
1398 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
1399 mce_severity(&m, regs, cfg->tolerant, &msg, true);
1400 mce_panic("Local fatal machine check!", &m, msg);
1405 * If tolerant is at an insane level we drop requests to kill
1406 * processes and continue even when there is no way out.
1408 if (cfg->tolerant == 3)
1410 else if (no_way_out)
1411 mce_panic("Fatal machine check on current CPU", &m, msg);
1414 irq_work_queue(&mce_irq_work);
1416 if (worst != MCE_AR_SEVERITY && !kill_it)
1419 /* Fault was in user mode and we need to take some action */
1420 if ((m.cs & 3) == 3) {
1421 /* If this triggers there is no way to recover. Die hard. */
1422 BUG_ON(!on_thread_stack() || !user_mode(regs));
1424 queue_task_work(&m, kill_it);
1428 * Handle an MCE which has happened in kernel space but from
1429 * which the kernel can recover: ex_has_fault_handler() has
1430 * already verified that the rIP at which the error happened is
1431 * a rIP from which the kernel can recover (by jumping to
1432 * recovery code specified in _ASM_EXTABLE_FAULT()) and the
1433 * corresponding exception handler which would do that is the
1436 if (m.kflags & MCE_IN_KERNEL_RECOV) {
1437 if (!fixup_exception(regs, X86_TRAP_MC, 0, 0))
1438 mce_panic("Failed kernel mode recovery", &m, msg);
1441 if (m.kflags & MCE_IN_KERNEL_COPYIN)
1442 queue_task_work(&m, kill_it);
1445 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1447 EXPORT_SYMBOL_GPL(do_machine_check);
1449 #ifndef CONFIG_MEMORY_FAILURE
1450 int memory_failure(unsigned long pfn, int flags)
1452 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1453 BUG_ON(flags & MF_ACTION_REQUIRED);
1454 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1455 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1463 * Periodic polling timer for "silent" machine check errors. If the
1464 * poller finds an MCE, poll 2x faster. When the poller finds no more
1465 * errors, poll 2x slower (up to check_interval seconds).
1467 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1469 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1470 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1472 static unsigned long mce_adjust_timer_default(unsigned long interval)
1477 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1479 static void __start_timer(struct timer_list *t, unsigned long interval)
1481 unsigned long when = jiffies + interval;
1482 unsigned long flags;
1484 local_irq_save(flags);
1486 if (!timer_pending(t) || time_before(when, t->expires))
1487 mod_timer(t, round_jiffies(when));
1489 local_irq_restore(flags);
1492 static void mce_timer_fn(struct timer_list *t)
1494 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1497 WARN_ON(cpu_t != t);
1499 iv = __this_cpu_read(mce_next_interval);
1501 if (mce_available(this_cpu_ptr(&cpu_info))) {
1502 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1504 if (mce_intel_cmci_poll()) {
1505 iv = mce_adjust_timer(iv);
1511 * Alert userspace if needed. If we logged an MCE, reduce the polling
1512 * interval, otherwise increase the polling interval.
1514 if (mce_notify_irq())
1515 iv = max(iv / 2, (unsigned long) HZ/100);
1517 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1520 __this_cpu_write(mce_next_interval, iv);
1521 __start_timer(t, iv);
1525 * Ensure that the timer is firing in @interval from now.
1527 void mce_timer_kick(unsigned long interval)
1529 struct timer_list *t = this_cpu_ptr(&mce_timer);
1530 unsigned long iv = __this_cpu_read(mce_next_interval);
1532 __start_timer(t, interval);
1535 __this_cpu_write(mce_next_interval, interval);
1538 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1539 static void mce_timer_delete_all(void)
1543 for_each_online_cpu(cpu)
1544 del_timer_sync(&per_cpu(mce_timer, cpu));
1548 * Notify the user(s) about new machine check events.
1549 * Can be called from interrupt context, but not from machine check/NMI
1552 int mce_notify_irq(void)
1554 /* Not more than two messages every minute */
1555 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1557 if (test_and_clear_bit(0, &mce_need_notify)) {
1560 if (__ratelimit(&ratelimit))
1561 pr_info(HW_ERR "Machine check events logged\n");
1567 EXPORT_SYMBOL_GPL(mce_notify_irq);
1569 static void __mcheck_cpu_mce_banks_init(void)
1571 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1572 u8 n_banks = this_cpu_read(mce_num_banks);
1575 for (i = 0; i < n_banks; i++) {
1576 struct mce_bank *b = &mce_banks[i];
1579 * Init them all, __mcheck_cpu_apply_quirks() is going to apply
1580 * the required vendor quirks before
1581 * __mcheck_cpu_init_clear_banks() does the final bank setup.
1589 * Initialize Machine Checks for a CPU.
1591 static void __mcheck_cpu_cap_init(void)
1596 rdmsrl(MSR_IA32_MCG_CAP, cap);
1598 b = cap & MCG_BANKCNT_MASK;
1600 if (b > MAX_NR_BANKS) {
1601 pr_warn("CPU%d: Using only %u machine check banks out of %u\n",
1602 smp_processor_id(), MAX_NR_BANKS, b);
1606 this_cpu_write(mce_num_banks, b);
1608 __mcheck_cpu_mce_banks_init();
1610 /* Use accurate RIP reporting if available. */
1611 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1612 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1614 if (cap & MCG_SER_P)
1618 static void __mcheck_cpu_init_generic(void)
1620 enum mcp_flags m_fl = 0;
1621 mce_banks_t all_banks;
1624 if (!mca_cfg.bootlog)
1628 * Log the machine checks left over from the previous reset.
1630 bitmap_fill(all_banks, MAX_NR_BANKS);
1631 machine_check_poll(MCP_UC | m_fl, &all_banks);
1633 cr4_set_bits(X86_CR4_MCE);
1635 rdmsrl(MSR_IA32_MCG_CAP, cap);
1636 if (cap & MCG_CTL_P)
1637 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1640 static void __mcheck_cpu_init_clear_banks(void)
1642 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1645 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1646 struct mce_bank *b = &mce_banks[i];
1650 wrmsrl(msr_ops.ctl(i), b->ctl);
1651 wrmsrl(msr_ops.status(i), 0);
1656 * Do a final check to see if there are any unused/RAZ banks.
1658 * This must be done after the banks have been initialized and any quirks have
1661 * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs.
1662 * Otherwise, a user who disables a bank will not be able to re-enable it
1663 * without a system reboot.
1665 static void __mcheck_cpu_check_banks(void)
1667 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1671 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1672 struct mce_bank *b = &mce_banks[i];
1677 rdmsrl(msr_ops.ctl(i), msrval);
1683 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1684 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1685 * Vol 3B Table 15-20). But this confuses both the code that determines
1686 * whether the machine check occurred in kernel or user mode, and also
1687 * the severity assessment code. Pretend that EIPV was set, and take the
1688 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1690 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1694 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1696 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1697 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1698 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1700 (MCI_STATUS_UC|MCI_STATUS_EN|
1701 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1702 MCI_STATUS_AR|MCACOD_INSTR))
1705 m->mcgstatus |= MCG_STATUS_EIPV;
1710 /* Add per CPU specific workarounds here */
1711 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1713 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1714 struct mca_config *cfg = &mca_cfg;
1716 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1717 pr_info("unknown CPU type - not enabling MCE support\n");
1721 /* This should be disabled by the BIOS, but isn't always */
1722 if (c->x86_vendor == X86_VENDOR_AMD) {
1723 if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
1725 * disable GART TBL walk error reporting, which
1726 * trips off incorrectly with the IOMMU & 3ware
1729 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1731 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1733 * Lots of broken BIOS around that don't clear them
1734 * by default and leave crap in there. Don't log:
1739 * Various K7s with broken bank 0 around. Always disable
1742 if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1743 mce_banks[0].ctl = 0;
1746 * overflow_recov is supported for F15h Models 00h-0fh
1747 * even though we don't have a CPUID bit for it.
1749 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1750 mce_flags.overflow_recov = 1;
1754 if (c->x86_vendor == X86_VENDOR_INTEL) {
1756 * SDM documents that on family 6 bank 0 should not be written
1757 * because it aliases to another special BIOS controlled
1759 * But it's not aliased anymore on model 0x1a+
1760 * Don't ignore bank 0 completely because there could be a
1761 * valid event later, merely don't write CTL0.
1764 if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1765 mce_banks[0].init = 0;
1768 * All newer Intel systems support MCE broadcasting. Enable
1769 * synchronization with a one second timeout.
1771 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1772 cfg->monarch_timeout < 0)
1773 cfg->monarch_timeout = USEC_PER_SEC;
1776 * There are also broken BIOSes on some Pentium M and
1779 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1782 if (c->x86 == 6 && c->x86_model == 45)
1783 quirk_no_way_out = quirk_sandybridge_ifu;
1786 if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
1788 * All newer Zhaoxin CPUs support MCE broadcasting. Enable
1789 * synchronization with a one second timeout.
1791 if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1792 if (cfg->monarch_timeout < 0)
1793 cfg->monarch_timeout = USEC_PER_SEC;
1797 if (cfg->monarch_timeout < 0)
1798 cfg->monarch_timeout = 0;
1799 if (cfg->bootlog != 0)
1800 cfg->panic_timeout = 30;
1805 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1810 switch (c->x86_vendor) {
1811 case X86_VENDOR_INTEL:
1812 intel_p5_mcheck_init(c);
1815 case X86_VENDOR_CENTAUR:
1816 winchip_mcheck_init(c);
1827 * Init basic CPU features needed for early decoding of MCEs.
1829 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1831 if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
1832 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1833 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1834 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1835 mce_flags.amd_threshold = 1;
1837 if (mce_flags.smca) {
1838 msr_ops.ctl = smca_ctl_reg;
1839 msr_ops.status = smca_status_reg;
1840 msr_ops.addr = smca_addr_reg;
1841 msr_ops.misc = smca_misc_reg;
1846 static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1848 struct mca_config *cfg = &mca_cfg;
1851 * All newer Centaur CPUs support MCE broadcasting. Enable
1852 * synchronization with a one second timeout.
1854 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1856 if (cfg->monarch_timeout < 0)
1857 cfg->monarch_timeout = USEC_PER_SEC;
1861 static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
1863 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1866 * These CPUs have MCA bank 8 which reports only one error type called
1867 * SVAD (System View Address Decoder). The reporting of that error is
1868 * controlled by IA32_MC8.CTL.0.
1870 * If enabled, prefetching on these CPUs will cause SVAD MCE when
1871 * virtual machines start and result in a system panic. Always disable
1872 * bank 8 SVAD error by default.
1874 if ((c->x86 == 7 && c->x86_model == 0x1b) ||
1875 (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1876 if (this_cpu_read(mce_num_banks) > 8)
1877 mce_banks[8].ctl = 0;
1882 mce_adjust_timer = cmci_intel_adjust_timer;
1885 static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
1890 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1892 switch (c->x86_vendor) {
1893 case X86_VENDOR_INTEL:
1894 mce_intel_feature_init(c);
1895 mce_adjust_timer = cmci_intel_adjust_timer;
1898 case X86_VENDOR_AMD: {
1899 mce_amd_feature_init(c);
1903 case X86_VENDOR_HYGON:
1904 mce_hygon_feature_init(c);
1907 case X86_VENDOR_CENTAUR:
1908 mce_centaur_feature_init(c);
1911 case X86_VENDOR_ZHAOXIN:
1912 mce_zhaoxin_feature_init(c);
1920 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1922 switch (c->x86_vendor) {
1923 case X86_VENDOR_INTEL:
1924 mce_intel_feature_clear(c);
1927 case X86_VENDOR_ZHAOXIN:
1928 mce_zhaoxin_feature_clear(c);
1936 static void mce_start_timer(struct timer_list *t)
1938 unsigned long iv = check_interval * HZ;
1940 if (mca_cfg.ignore_ce || !iv)
1943 this_cpu_write(mce_next_interval, iv);
1944 __start_timer(t, iv);
1947 static void __mcheck_cpu_setup_timer(void)
1949 struct timer_list *t = this_cpu_ptr(&mce_timer);
1951 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1954 static void __mcheck_cpu_init_timer(void)
1956 struct timer_list *t = this_cpu_ptr(&mce_timer);
1958 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1962 bool filter_mce(struct mce *m)
1964 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1965 return amd_filter_mce(m);
1966 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1967 return intel_filter_mce(m);
1972 /* Handle unconfigured int18 (should never happen) */
1973 static noinstr void unexpected_machine_check(struct pt_regs *regs)
1975 instrumentation_begin();
1976 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1977 smp_processor_id());
1978 instrumentation_end();
1981 /* Call the installed machine check handler for this CPU setup. */
1982 void (*machine_check_vector)(struct pt_regs *) = unexpected_machine_check;
1984 static __always_inline void exc_machine_check_kernel(struct pt_regs *regs)
1986 irqentry_state_t irq_state;
1988 WARN_ON_ONCE(user_mode(regs));
1991 * Only required when from kernel mode. See
1992 * mce_check_crashing_cpu() for details.
1994 if (machine_check_vector == do_machine_check &&
1995 mce_check_crashing_cpu())
1998 irq_state = irqentry_nmi_enter(regs);
2000 * The call targets are marked noinstr, but objtool can't figure
2001 * that out because it's an indirect call. Annotate it.
2003 instrumentation_begin();
2004 trace_hardirqs_off_finish();
2005 machine_check_vector(regs);
2006 if (regs->flags & X86_EFLAGS_IF)
2007 trace_hardirqs_on_prepare();
2008 instrumentation_end();
2009 irqentry_nmi_exit(regs, irq_state);
2012 static __always_inline void exc_machine_check_user(struct pt_regs *regs)
2014 irqentry_enter_from_user_mode(regs);
2015 instrumentation_begin();
2016 machine_check_vector(regs);
2017 instrumentation_end();
2018 irqentry_exit_to_user_mode(regs);
2021 #ifdef CONFIG_X86_64
2022 /* MCE hit kernel mode */
2023 DEFINE_IDTENTRY_MCE(exc_machine_check)
2027 dr7 = local_db_save();
2028 exc_machine_check_kernel(regs);
2029 local_db_restore(dr7);
2032 /* The user mode variant. */
2033 DEFINE_IDTENTRY_MCE_USER(exc_machine_check)
2037 dr7 = local_db_save();
2038 exc_machine_check_user(regs);
2039 local_db_restore(dr7);
2042 /* 32bit unified entry point */
2043 DEFINE_IDTENTRY_RAW(exc_machine_check)
2047 dr7 = local_db_save();
2048 if (user_mode(regs))
2049 exc_machine_check_user(regs);
2051 exc_machine_check_kernel(regs);
2052 local_db_restore(dr7);
2057 * Called for each booted CPU to set up machine checks.
2058 * Must be called with preempt off:
2060 void mcheck_cpu_init(struct cpuinfo_x86 *c)
2062 if (mca_cfg.disabled)
2065 if (__mcheck_cpu_ancient_init(c))
2068 if (!mce_available(c))
2071 __mcheck_cpu_cap_init();
2073 if (__mcheck_cpu_apply_quirks(c) < 0) {
2074 mca_cfg.disabled = 1;
2078 if (mce_gen_pool_init()) {
2079 mca_cfg.disabled = 1;
2080 pr_emerg("Couldn't allocate MCE records pool!\n");
2084 machine_check_vector = do_machine_check;
2086 __mcheck_cpu_init_early(c);
2087 __mcheck_cpu_init_generic();
2088 __mcheck_cpu_init_vendor(c);
2089 __mcheck_cpu_init_clear_banks();
2090 __mcheck_cpu_check_banks();
2091 __mcheck_cpu_setup_timer();
2095 * Called for each booted CPU to clear some machine checks opt-ins
2097 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
2099 if (mca_cfg.disabled)
2102 if (!mce_available(c))
2106 * Possibly to clear general settings generic to x86
2107 * __mcheck_cpu_clear_generic(c);
2109 __mcheck_cpu_clear_vendor(c);
2113 static void __mce_disable_bank(void *arg)
2115 int bank = *((int *)arg);
2116 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
2117 cmci_disable_bank(bank);
2120 void mce_disable_bank(int bank)
2122 if (bank >= this_cpu_read(mce_num_banks)) {
2124 "Ignoring request to disable invalid MCA bank %d.\n",
2128 set_bit(bank, mce_banks_ce_disabled);
2129 on_each_cpu(__mce_disable_bank, &bank, 1);
2133 * mce=off Disables machine check
2134 * mce=no_cmci Disables CMCI
2135 * mce=no_lmce Disables LMCE
2136 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2137 * mce=print_all Print all machine check logs to console
2138 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2139 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2140 * monarchtimeout is how long to wait for other CPUs on machine
2141 * check, or 0 to not wait
2142 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
2144 * mce=nobootlog Don't log MCEs from before booting.
2145 * mce=bios_cmci_threshold Don't program the CMCI threshold
2146 * mce=recovery force enable copy_mc_fragile()
2148 static int __init mcheck_enable(char *str)
2150 struct mca_config *cfg = &mca_cfg;
2158 if (!strcmp(str, "off"))
2160 else if (!strcmp(str, "no_cmci"))
2161 cfg->cmci_disabled = true;
2162 else if (!strcmp(str, "no_lmce"))
2163 cfg->lmce_disabled = 1;
2164 else if (!strcmp(str, "dont_log_ce"))
2165 cfg->dont_log_ce = true;
2166 else if (!strcmp(str, "print_all"))
2167 cfg->print_all = true;
2168 else if (!strcmp(str, "ignore_ce"))
2169 cfg->ignore_ce = true;
2170 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2171 cfg->bootlog = (str[0] == 'b');
2172 else if (!strcmp(str, "bios_cmci_threshold"))
2173 cfg->bios_cmci_threshold = 1;
2174 else if (!strcmp(str, "recovery"))
2176 else if (isdigit(str[0])) {
2177 if (get_option(&str, &cfg->tolerant) == 2)
2178 get_option(&str, &(cfg->monarch_timeout));
2180 pr_info("mce argument %s ignored. Please use /sys\n", str);
2185 __setup("mce", mcheck_enable);
2187 int __init mcheck_init(void)
2189 mcheck_intel_therm_init();
2190 mce_register_decode_chain(&early_nb);
2191 mce_register_decode_chain(&mce_uc_nb);
2192 mce_register_decode_chain(&mce_default_nb);
2193 mcheck_vendor_init_severity();
2195 INIT_WORK(&mce_work, mce_gen_pool_process);
2196 init_irq_work(&mce_irq_work, mce_irq_work_cb);
2202 * mce_syscore: PM support
2206 * Disable machine checks on suspend and shutdown. We can't really handle
2209 static void mce_disable_error_reporting(void)
2211 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2214 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2215 struct mce_bank *b = &mce_banks[i];
2218 wrmsrl(msr_ops.ctl(i), 0);
2223 static void vendor_disable_error_reporting(void)
2226 * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
2227 * MSRs are socket-wide. Disabling them for just a single offlined CPU
2228 * is bad, since it will inhibit reporting for all shared resources on
2229 * the socket like the last level cache (LLC), the integrated memory
2230 * controller (iMC), etc.
2232 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
2233 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
2234 boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
2235 boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
2238 mce_disable_error_reporting();
2241 static int mce_syscore_suspend(void)
2243 vendor_disable_error_reporting();
2247 static void mce_syscore_shutdown(void)
2249 vendor_disable_error_reporting();
2253 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2254 * Only one CPU is active at this time, the others get re-added later using
2257 static void mce_syscore_resume(void)
2259 __mcheck_cpu_init_generic();
2260 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2261 __mcheck_cpu_init_clear_banks();
2264 static struct syscore_ops mce_syscore_ops = {
2265 .suspend = mce_syscore_suspend,
2266 .shutdown = mce_syscore_shutdown,
2267 .resume = mce_syscore_resume,
2271 * mce_device: Sysfs support
2274 static void mce_cpu_restart(void *data)
2276 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2278 __mcheck_cpu_init_generic();
2279 __mcheck_cpu_init_clear_banks();
2280 __mcheck_cpu_init_timer();
2283 /* Reinit MCEs after user configuration changes */
2284 static void mce_restart(void)
2286 mce_timer_delete_all();
2287 on_each_cpu(mce_cpu_restart, NULL, 1);
2290 /* Toggle features for corrected errors */
2291 static void mce_disable_cmci(void *data)
2293 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2298 static void mce_enable_ce(void *all)
2300 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2305 __mcheck_cpu_init_timer();
2308 static struct bus_type mce_subsys = {
2309 .name = "machinecheck",
2310 .dev_name = "machinecheck",
2313 DEFINE_PER_CPU(struct device *, mce_device);
2315 static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr)
2317 return container_of(attr, struct mce_bank_dev, attr);
2320 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2323 u8 bank = attr_to_bank(attr)->bank;
2326 if (bank >= per_cpu(mce_num_banks, s->id))
2329 b = &per_cpu(mce_banks_array, s->id)[bank];
2334 return sprintf(buf, "%llx\n", b->ctl);
2337 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2338 const char *buf, size_t size)
2340 u8 bank = attr_to_bank(attr)->bank;
2344 if (kstrtou64(buf, 0, &new) < 0)
2347 if (bank >= per_cpu(mce_num_banks, s->id))
2350 b = &per_cpu(mce_banks_array, s->id)[bank];
2361 static ssize_t set_ignore_ce(struct device *s,
2362 struct device_attribute *attr,
2363 const char *buf, size_t size)
2367 if (kstrtou64(buf, 0, &new) < 0)
2370 mutex_lock(&mce_sysfs_mutex);
2371 if (mca_cfg.ignore_ce ^ !!new) {
2373 /* disable ce features */
2374 mce_timer_delete_all();
2375 on_each_cpu(mce_disable_cmci, NULL, 1);
2376 mca_cfg.ignore_ce = true;
2378 /* enable ce features */
2379 mca_cfg.ignore_ce = false;
2380 on_each_cpu(mce_enable_ce, (void *)1, 1);
2383 mutex_unlock(&mce_sysfs_mutex);
2388 static ssize_t set_cmci_disabled(struct device *s,
2389 struct device_attribute *attr,
2390 const char *buf, size_t size)
2394 if (kstrtou64(buf, 0, &new) < 0)
2397 mutex_lock(&mce_sysfs_mutex);
2398 if (mca_cfg.cmci_disabled ^ !!new) {
2401 on_each_cpu(mce_disable_cmci, NULL, 1);
2402 mca_cfg.cmci_disabled = true;
2405 mca_cfg.cmci_disabled = false;
2406 on_each_cpu(mce_enable_ce, NULL, 1);
2409 mutex_unlock(&mce_sysfs_mutex);
2414 static ssize_t store_int_with_restart(struct device *s,
2415 struct device_attribute *attr,
2416 const char *buf, size_t size)
2418 unsigned long old_check_interval = check_interval;
2419 ssize_t ret = device_store_ulong(s, attr, buf, size);
2421 if (check_interval == old_check_interval)
2424 mutex_lock(&mce_sysfs_mutex);
2426 mutex_unlock(&mce_sysfs_mutex);
2431 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2432 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2433 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2434 static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all);
2436 static struct dev_ext_attribute dev_attr_check_interval = {
2437 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2441 static struct dev_ext_attribute dev_attr_ignore_ce = {
2442 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2446 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2447 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2448 &mca_cfg.cmci_disabled
2451 static struct device_attribute *mce_device_attrs[] = {
2452 &dev_attr_tolerant.attr,
2453 &dev_attr_check_interval.attr,
2454 #ifdef CONFIG_X86_MCELOG_LEGACY
2457 &dev_attr_monarch_timeout.attr,
2458 &dev_attr_dont_log_ce.attr,
2459 &dev_attr_print_all.attr,
2460 &dev_attr_ignore_ce.attr,
2461 &dev_attr_cmci_disabled.attr,
2465 static cpumask_var_t mce_device_initialized;
2467 static void mce_device_release(struct device *dev)
2472 /* Per CPU device init. All of the CPUs still share the same bank device: */
2473 static int mce_device_create(unsigned int cpu)
2479 if (!mce_available(&boot_cpu_data))
2482 dev = per_cpu(mce_device, cpu);
2486 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2490 dev->bus = &mce_subsys;
2491 dev->release = &mce_device_release;
2493 err = device_register(dev);
2499 for (i = 0; mce_device_attrs[i]; i++) {
2500 err = device_create_file(dev, mce_device_attrs[i]);
2504 for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) {
2505 err = device_create_file(dev, &mce_bank_devs[j].attr);
2509 cpumask_set_cpu(cpu, mce_device_initialized);
2510 per_cpu(mce_device, cpu) = dev;
2515 device_remove_file(dev, &mce_bank_devs[j].attr);
2518 device_remove_file(dev, mce_device_attrs[i]);
2520 device_unregister(dev);
2525 static void mce_device_remove(unsigned int cpu)
2527 struct device *dev = per_cpu(mce_device, cpu);
2530 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2533 for (i = 0; mce_device_attrs[i]; i++)
2534 device_remove_file(dev, mce_device_attrs[i]);
2536 for (i = 0; i < per_cpu(mce_num_banks, cpu); i++)
2537 device_remove_file(dev, &mce_bank_devs[i].attr);
2539 device_unregister(dev);
2540 cpumask_clear_cpu(cpu, mce_device_initialized);
2541 per_cpu(mce_device, cpu) = NULL;
2544 /* Make sure there are no machine checks on offlined CPUs. */
2545 static void mce_disable_cpu(void)
2547 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2550 if (!cpuhp_tasks_frozen)
2553 vendor_disable_error_reporting();
2556 static void mce_reenable_cpu(void)
2558 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2561 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2564 if (!cpuhp_tasks_frozen)
2566 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2567 struct mce_bank *b = &mce_banks[i];
2570 wrmsrl(msr_ops.ctl(i), b->ctl);
2574 static int mce_cpu_dead(unsigned int cpu)
2576 mce_intel_hcpu_update(cpu);
2578 /* intentionally ignoring frozen here */
2579 if (!cpuhp_tasks_frozen)
2584 static int mce_cpu_online(unsigned int cpu)
2586 struct timer_list *t = this_cpu_ptr(&mce_timer);
2589 mce_device_create(cpu);
2591 ret = mce_threshold_create_device(cpu);
2593 mce_device_remove(cpu);
2601 static int mce_cpu_pre_down(unsigned int cpu)
2603 struct timer_list *t = this_cpu_ptr(&mce_timer);
2607 mce_threshold_remove_device(cpu);
2608 mce_device_remove(cpu);
2612 static __init void mce_init_banks(void)
2616 for (i = 0; i < MAX_NR_BANKS; i++) {
2617 struct mce_bank_dev *b = &mce_bank_devs[i];
2618 struct device_attribute *a = &b->attr;
2622 sysfs_attr_init(&a->attr);
2623 a->attr.name = b->attrname;
2624 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2626 a->attr.mode = 0644;
2627 a->show = show_bank;
2628 a->store = set_bank;
2633 * When running on XEN, this initcall is ordered against the XEN mcelog
2636 * device_initcall(xen_late_init_mcelog);
2637 * device_initcall_sync(mcheck_init_device);
2639 static __init int mcheck_init_device(void)
2644 * Check if we have a spare virtual bit. This will only become
2645 * a problem if/when we move beyond 5-level page tables.
2647 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2649 if (!mce_available(&boot_cpu_data)) {
2654 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2661 err = subsys_system_register(&mce_subsys, NULL);
2665 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2671 * Invokes mce_cpu_online() on all CPUs which are online when
2672 * the state is installed.
2674 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2675 mce_cpu_online, mce_cpu_pre_down);
2677 goto err_out_online;
2679 register_syscore_ops(&mce_syscore_ops);
2684 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2687 free_cpumask_var(mce_device_initialized);
2690 pr_err("Unable to init MCE device (rc: %d)\n", err);
2694 device_initcall_sync(mcheck_init_device);
2697 * Old style boot options parsing. Only for compatibility.
2699 static int __init mcheck_disable(char *str)
2701 mca_cfg.disabled = 1;
2704 __setup("nomce", mcheck_disable);
2706 #ifdef CONFIG_DEBUG_FS
2707 struct dentry *mce_get_debugfs_dir(void)
2709 static struct dentry *dmce;
2712 dmce = debugfs_create_dir("mce", NULL);
2717 static void mce_reset(void)
2720 atomic_set(&mce_fake_panicked, 0);
2721 atomic_set(&mce_executing, 0);
2722 atomic_set(&mce_callin, 0);
2723 atomic_set(&global_nwo, 0);
2726 static int fake_panic_get(void *data, u64 *val)
2732 static int fake_panic_set(void *data, u64 val)
2739 DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set,
2742 static void __init mcheck_debugfs_init(void)
2744 struct dentry *dmce;
2746 dmce = mce_get_debugfs_dir();
2747 debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL,
2751 static void __init mcheck_debugfs_init(void) { }
2754 static int __init mcheck_late_init(void)
2756 if (mca_cfg.recovery)
2757 enable_copy_mc_fragile();
2759 mcheck_debugfs_init();
2762 * Flush out everything that has been logged during early boot, now that
2763 * everything has been initialized (workqueues, decoders, ...).
2765 mce_schedule_work();
2769 late_initcall(mcheck_late_init);