1 // SPDX-License-Identifier: GPL-2.0-only
3 * Machine check handler.
5 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
6 * Rest from unknown author(s).
7 * 2004 Andi Kleen. Rewrote most of it.
8 * Copyright 2008 Intel Corporation
12 #include <linux/thread_info.h>
13 #include <linux/capability.h>
14 #include <linux/miscdevice.h>
15 #include <linux/ratelimit.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/device.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/delay.h>
26 #include <linux/ctype.h>
27 #include <linux/sched.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/kmod.h>
33 #include <linux/poll.h>
34 #include <linux/nmi.h>
35 #include <linux/cpu.h>
36 #include <linux/ras.h>
37 #include <linux/smp.h>
40 #include <linux/debugfs.h>
41 #include <linux/irq_work.h>
42 #include <linux/export.h>
43 #include <linux/jump_label.h>
44 #include <linux/set_memory.h>
45 #include <linux/task_work.h>
46 #include <linux/hardirq.h>
48 #include <asm/intel-family.h>
49 #include <asm/processor.h>
50 #include <asm/traps.h>
51 #include <asm/tlbflush.h>
54 #include <asm/reboot.h>
58 /* sysfs synchronization */
59 static DEFINE_MUTEX(mce_sysfs_mutex);
61 #define CREATE_TRACE_POINTS
62 #include <trace/events/mce.h>
64 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
68 DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
71 u64 ctl; /* subevents to enable */
72 bool init; /* initialise bank? */
74 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
77 /* One object for each MCE bank, shared by all CPUs */
79 struct device_attribute attr; /* device attribute */
80 char attrname[ATTR_LEN]; /* attribute name */
81 u8 bank; /* bank number */
83 static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS];
85 struct mce_vendor_flags mce_flags __read_mostly;
87 struct mca_config mca_cfg __read_mostly = {
91 * 0: always panic on uncorrected errors, log corrected errors
92 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
93 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
94 * 3: never panic or SIGBUS, log all errors (for testing only)
100 static DEFINE_PER_CPU(struct mce, mces_seen);
101 static unsigned long mce_need_notify;
102 static int cpu_missing;
105 * MCA banks polled by the period polling timer for corrected events.
106 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
108 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
109 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
113 * MCA banks controlled through firmware first for corrected errors.
114 * This is a global list of banks for which we won't enable CMCI and we
115 * won't poll. Firmware controls these banks and is responsible for
116 * reporting corrected errors through GHES. Uncorrected/recoverable
117 * errors are still notified through a machine check.
119 mce_banks_t mce_banks_ce_disabled;
121 static struct work_struct mce_work;
122 static struct irq_work mce_irq_work;
124 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
127 * CPU/chipset specific EDAC code can register a notifier call here to print
128 * MCE errors in a human-readable form.
130 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
132 /* Do initial initialization of a struct mce */
133 void mce_setup(struct mce *m)
135 memset(m, 0, sizeof(struct mce));
136 m->cpu = m->extcpu = smp_processor_id();
137 /* need the internal __ version to avoid deadlocks */
138 m->time = __ktime_get_real_seconds();
139 m->cpuvendor = boot_cpu_data.x86_vendor;
140 m->cpuid = cpuid_eax(1);
141 m->socketid = cpu_data(m->extcpu).phys_proc_id;
142 m->apicid = cpu_data(m->extcpu).initial_apicid;
143 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
145 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
146 rdmsrl(MSR_PPIN, m->ppin);
147 else if (this_cpu_has(X86_FEATURE_AMD_PPIN))
148 rdmsrl(MSR_AMD_PPIN, m->ppin);
150 m->microcode = boot_cpu_data.microcode;
153 DEFINE_PER_CPU(struct mce, injectm);
154 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
156 void mce_log(struct mce *m)
158 if (!mce_gen_pool_add(m))
159 irq_work_queue(&mce_irq_work);
161 EXPORT_SYMBOL_GPL(mce_log);
164 * We run the default notifier if we have only the UC, the first and the
165 * default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS
166 * notifiers registered on the chain.
168 #define NUM_DEFAULT_NOTIFIERS 3
169 static atomic_t num_notifiers;
171 void mce_register_decode_chain(struct notifier_block *nb)
173 if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC))
176 atomic_inc(&num_notifiers);
178 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
180 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
182 void mce_unregister_decode_chain(struct notifier_block *nb)
184 atomic_dec(&num_notifiers);
186 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
188 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
190 static inline u32 ctl_reg(int bank)
192 return MSR_IA32_MCx_CTL(bank);
195 static inline u32 status_reg(int bank)
197 return MSR_IA32_MCx_STATUS(bank);
200 static inline u32 addr_reg(int bank)
202 return MSR_IA32_MCx_ADDR(bank);
205 static inline u32 misc_reg(int bank)
207 return MSR_IA32_MCx_MISC(bank);
210 static inline u32 smca_ctl_reg(int bank)
212 return MSR_AMD64_SMCA_MCx_CTL(bank);
215 static inline u32 smca_status_reg(int bank)
217 return MSR_AMD64_SMCA_MCx_STATUS(bank);
220 static inline u32 smca_addr_reg(int bank)
222 return MSR_AMD64_SMCA_MCx_ADDR(bank);
225 static inline u32 smca_misc_reg(int bank)
227 return MSR_AMD64_SMCA_MCx_MISC(bank);
230 struct mca_msr_regs msr_ops = {
232 .status = status_reg,
237 static void __print_mce(struct mce *m)
239 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
241 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
242 m->mcgstatus, m->bank, m->status);
245 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
246 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
249 if (m->cs == __KERNEL_CS)
250 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
254 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
256 pr_cont("ADDR %llx ", m->addr);
258 pr_cont("MISC %llx ", m->misc);
260 if (mce_flags.smca) {
262 pr_cont("SYND %llx ", m->synd);
264 pr_cont("IPID %llx ", m->ipid);
269 * Note this output is parsed by external tools and old fields
270 * should not be changed.
272 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
273 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
277 static void print_mce(struct mce *m)
281 if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
282 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
285 #define PANIC_TIMEOUT 5 /* 5 seconds */
287 static atomic_t mce_panicked;
289 static int fake_panic;
290 static atomic_t mce_fake_panicked;
292 /* Panic in progress. Enable interrupts and wait for final IPI */
293 static void wait_for_panic(void)
295 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
299 while (timeout-- > 0)
301 if (panic_timeout == 0)
302 panic_timeout = mca_cfg.panic_timeout;
303 panic("Panicing machine check CPU died");
306 static void mce_panic(const char *msg, struct mce *final, char *exp)
309 struct llist_node *pending;
310 struct mce_evt_llist *l;
314 * Make sure only one CPU runs in machine check panic
316 if (atomic_inc_return(&mce_panicked) > 1)
323 /* Don't log too much for fake panic */
324 if (atomic_inc_return(&mce_fake_panicked) > 1)
327 pending = mce_gen_pool_prepare_records();
328 /* First print corrected ones that are still unlogged */
329 llist_for_each_entry(l, pending, llnode) {
330 struct mce *m = &l->mce;
331 if (!(m->status & MCI_STATUS_UC)) {
334 apei_err = apei_write_mce(m);
337 /* Now print uncorrected but with the final one last */
338 llist_for_each_entry(l, pending, llnode) {
339 struct mce *m = &l->mce;
340 if (!(m->status & MCI_STATUS_UC))
342 if (!final || mce_cmp(m, final)) {
345 apei_err = apei_write_mce(m);
351 apei_err = apei_write_mce(final);
354 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
356 pr_emerg(HW_ERR "Machine check: %s\n", exp);
358 if (panic_timeout == 0)
359 panic_timeout = mca_cfg.panic_timeout;
362 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
365 /* Support code for software error injection */
367 static int msr_to_offset(u32 msr)
369 unsigned bank = __this_cpu_read(injectm.bank);
371 if (msr == mca_cfg.rip_msr)
372 return offsetof(struct mce, ip);
373 if (msr == msr_ops.status(bank))
374 return offsetof(struct mce, status);
375 if (msr == msr_ops.addr(bank))
376 return offsetof(struct mce, addr);
377 if (msr == msr_ops.misc(bank))
378 return offsetof(struct mce, misc);
379 if (msr == MSR_IA32_MCG_STATUS)
380 return offsetof(struct mce, mcgstatus);
384 /* MSR access wrappers used for error injection */
385 static u64 mce_rdmsrl(u32 msr)
389 if (__this_cpu_read(injectm.finished)) {
390 int offset = msr_to_offset(msr);
394 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
397 if (rdmsrl_safe(msr, &v)) {
398 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
400 * Return zero in case the access faulted. This should
401 * not happen normally but can happen if the CPU does
402 * something weird, or if the code is buggy.
410 static void mce_wrmsrl(u32 msr, u64 v)
412 if (__this_cpu_read(injectm.finished)) {
413 int offset = msr_to_offset(msr);
416 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
423 * Collect all global (w.r.t. this processor) status about this machine
424 * check into our "mce" struct so that we can use it later to assess
425 * the severity of the problem as we read per-bank specific details.
427 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
431 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
434 * Get the address of the instruction at the time of
435 * the machine check error.
437 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
442 * When in VM86 mode make the cs look like ring 3
443 * always. This is a lie, but it's better than passing
444 * the additional vm86 bit around everywhere.
446 if (v8086_mode(regs))
449 /* Use accurate RIP reporting if available. */
451 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
455 int mce_available(struct cpuinfo_x86 *c)
457 if (mca_cfg.disabled)
459 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
462 static void mce_schedule_work(void)
464 if (!mce_gen_pool_empty())
465 schedule_work(&mce_work);
468 static void mce_irq_work_cb(struct irq_work *entry)
474 * Check if the address reported by the CPU is in a format we can parse.
475 * It would be possible to add code for most other cases, but all would
476 * be somewhat complicated (e.g. segment offset would require an instruction
477 * parser). So only support physical addresses up to page granuality for now.
479 int mce_usable_address(struct mce *m)
481 if (!(m->status & MCI_STATUS_ADDRV))
484 /* Checks after this one are Intel/Zhaoxin-specific: */
485 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
486 boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
489 if (!(m->status & MCI_STATUS_MISCV))
492 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
495 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
500 EXPORT_SYMBOL_GPL(mce_usable_address);
502 bool mce_is_memory_error(struct mce *m)
504 switch (m->cpuvendor) {
506 case X86_VENDOR_HYGON:
507 return amd_mce_is_memory_error(m);
509 case X86_VENDOR_INTEL:
510 case X86_VENDOR_ZHAOXIN:
512 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
514 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
515 * indicating a memory error. Bit 8 is used for indicating a
516 * cache hierarchy error. The combination of bit 2 and bit 3
517 * is used for indicating a `generic' cache hierarchy error
518 * But we can't just blindly check the above bits, because if
519 * bit 11 is set, then it is a bus/interconnect error - and
520 * either way the above bits just gives more detail on what
521 * bus/interconnect error happened. Note that bit 12 can be
522 * ignored, as it's the "filter" bit.
524 return (m->status & 0xef80) == BIT(7) ||
525 (m->status & 0xef00) == BIT(8) ||
526 (m->status & 0xeffc) == 0xc;
532 EXPORT_SYMBOL_GPL(mce_is_memory_error);
534 bool mce_is_correctable(struct mce *m)
536 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
539 if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
542 if (m->status & MCI_STATUS_UC)
547 EXPORT_SYMBOL_GPL(mce_is_correctable);
549 static bool cec_add_mce(struct mce *m)
554 /* We eat only correctable DRAM errors with usable addresses. */
555 if (mce_is_memory_error(m) &&
556 mce_is_correctable(m) &&
557 mce_usable_address(m))
558 if (!cec_add_elem(m->addr >> PAGE_SHIFT))
564 static int mce_first_notifier(struct notifier_block *nb, unsigned long val,
567 struct mce *m = (struct mce *)data;
575 /* Emit the trace record: */
578 set_bit(0, &mce_need_notify);
585 static struct notifier_block first_nb = {
586 .notifier_call = mce_first_notifier,
587 .priority = MCE_PRIO_FIRST,
590 static int uc_decode_notifier(struct notifier_block *nb, unsigned long val,
593 struct mce *mce = (struct mce *)data;
596 if (!mce || !mce_usable_address(mce))
599 if (mce->severity != MCE_AO_SEVERITY &&
600 mce->severity != MCE_DEFERRED_SEVERITY)
603 pfn = mce->addr >> PAGE_SHIFT;
604 if (!memory_failure(pfn, 0))
610 static struct notifier_block mce_uc_nb = {
611 .notifier_call = uc_decode_notifier,
612 .priority = MCE_PRIO_UC,
615 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
618 struct mce *m = (struct mce *)data;
623 if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS)
631 static struct notifier_block mce_default_nb = {
632 .notifier_call = mce_default_notifier,
633 /* lowest prio, we want it to run last. */
634 .priority = MCE_PRIO_LOWEST,
638 * Read ADDR and MISC registers.
640 static void mce_read_aux(struct mce *m, int i)
642 if (m->status & MCI_STATUS_MISCV)
643 m->misc = mce_rdmsrl(msr_ops.misc(i));
645 if (m->status & MCI_STATUS_ADDRV) {
646 m->addr = mce_rdmsrl(msr_ops.addr(i));
649 * Mask the reported address by the reported granularity.
651 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
652 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
658 * Extract [55:<lsb>] where lsb is the least significant
659 * *valid* bit of the address bits.
661 if (mce_flags.smca) {
662 u8 lsb = (m->addr >> 56) & 0x3f;
664 m->addr &= GENMASK_ULL(55, lsb);
668 if (mce_flags.smca) {
669 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
671 if (m->status & MCI_STATUS_SYNDV)
672 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
676 DEFINE_PER_CPU(unsigned, mce_poll_count);
679 * Poll for corrected events or events that happened before reset.
680 * Those are just logged through /dev/mcelog.
682 * This is executed in standard interrupt context.
684 * Note: spec recommends to panic for fatal unsignalled
685 * errors here. However this would be quite problematic --
686 * we would need to reimplement the Monarch handling and
687 * it would mess up the exclusion between exception handler
688 * and poll handler -- * so we skip this for now.
689 * These cases should not happen anyways, or only when the CPU
690 * is already totally * confused. In this case it's likely it will
691 * not fully execute the machine check handler either.
693 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
695 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
696 bool error_seen = false;
700 this_cpu_inc(mce_poll_count);
702 mce_gather_info(&m, NULL);
704 if (flags & MCP_TIMESTAMP)
707 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
708 if (!mce_banks[i].ctl || !test_bit(i, *b))
716 m.status = mce_rdmsrl(msr_ops.status(i));
718 /* If this entry is not valid, ignore it */
719 if (!(m.status & MCI_STATUS_VAL))
723 * If we are logging everything (at CPU online) or this
724 * is a corrected error, then we must log it.
726 if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
730 * Newer Intel systems that support software error
731 * recovery need to make additional checks. Other
732 * CPUs should skip over uncorrected errors, but log
736 if (m.status & MCI_STATUS_UC)
741 /* Log "not enabled" (speculative) errors */
742 if (!(m.status & MCI_STATUS_EN))
746 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
747 * UC == 1 && PCC == 0 && S == 0
749 if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
753 * Skip anything else. Presumption is that our read of this
754 * bank is racing with a machine check. Leave the log alone
755 * for do_machine_check() to deal with it.
762 if (flags & MCP_DONTLOG)
766 m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
768 * Don't get the IP here because it's unlikely to
769 * have anything to do with the actual error location.
772 if (mca_cfg.dont_log_ce && !mce_usable_address(&m))
779 * Clear state for this bank.
781 mce_wrmsrl(msr_ops.status(i), 0);
785 * Don't clear MCG_STATUS here because it's only defined for
793 EXPORT_SYMBOL_GPL(machine_check_poll);
796 * Do a quick check if any of the events requires a panic.
797 * This decides if we keep the events around or clear them.
799 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
800 struct pt_regs *regs)
805 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
806 m->status = mce_rdmsrl(msr_ops.status(i));
807 if (!(m->status & MCI_STATUS_VAL))
810 __set_bit(i, validp);
811 if (quirk_no_way_out)
812 quirk_no_way_out(i, m, regs);
815 if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
825 * Variable to establish order between CPUs while scanning.
826 * Each CPU spins initially until executing is equal its number.
828 static atomic_t mce_executing;
831 * Defines order of CPUs on entry. First CPU becomes Monarch.
833 static atomic_t mce_callin;
836 * Check if a timeout waiting for other CPUs happened.
838 static int mce_timed_out(u64 *t, const char *msg)
841 * The others already did panic for some reason.
842 * Bail out like in a timeout.
843 * rmb() to tell the compiler that system_state
844 * might have been modified by someone else.
847 if (atomic_read(&mce_panicked))
849 if (!mca_cfg.monarch_timeout)
851 if ((s64)*t < SPINUNIT) {
852 if (mca_cfg.tolerant <= 1)
853 mce_panic(msg, NULL, NULL);
859 touch_nmi_watchdog();
864 * The Monarch's reign. The Monarch is the CPU who entered
865 * the machine check handler first. It waits for the others to
866 * raise the exception too and then grades them. When any
867 * error is fatal panic. Only then let the others continue.
869 * The other CPUs entering the MCE handler will be controlled by the
870 * Monarch. They are called Subjects.
872 * This way we prevent any potential data corruption in a unrecoverable case
873 * and also makes sure always all CPU's errors are examined.
875 * Also this detects the case of a machine check event coming from outer
876 * space (not detected by any CPUs) In this case some external agent wants
877 * us to shut down, so panic too.
879 * The other CPUs might still decide to panic if the handler happens
880 * in a unrecoverable place, but in this case the system is in a semi-stable
881 * state and won't corrupt anything by itself. It's ok to let the others
882 * continue for a bit first.
884 * All the spin loops have timeouts; when a timeout happens a CPU
885 * typically elects itself to be Monarch.
887 static void mce_reign(void)
890 struct mce *m = NULL;
891 int global_worst = 0;
896 * This CPU is the Monarch and the other CPUs have run
897 * through their handlers.
898 * Grade the severity of the errors of all the CPUs.
900 for_each_possible_cpu(cpu) {
901 int severity = mce_severity(&per_cpu(mces_seen, cpu),
904 if (severity > global_worst) {
906 global_worst = severity;
907 m = &per_cpu(mces_seen, cpu);
912 * Cannot recover? Panic here then.
913 * This dumps all the mces in the log buffer and stops the
916 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
917 mce_panic("Fatal machine check", m, msg);
920 * For UC somewhere we let the CPU who detects it handle it.
921 * Also must let continue the others, otherwise the handling
922 * CPU could deadlock on a lock.
926 * No machine check event found. Must be some external
927 * source or one CPU is hung. Panic.
929 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
930 mce_panic("Fatal machine check from unknown source", NULL, NULL);
933 * Now clear all the mces_seen so that they don't reappear on
936 for_each_possible_cpu(cpu)
937 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
940 static atomic_t global_nwo;
943 * Start of Monarch synchronization. This waits until all CPUs have
944 * entered the exception handler and then determines if any of them
945 * saw a fatal event that requires panic. Then it executes them
946 * in the entry order.
947 * TBD double check parallel CPU hotunplug
949 static int mce_start(int *no_way_out)
952 int cpus = num_online_cpus();
953 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
958 atomic_add(*no_way_out, &global_nwo);
960 * Rely on the implied barrier below, such that global_nwo
961 * is updated before mce_callin.
963 order = atomic_inc_return(&mce_callin);
968 while (atomic_read(&mce_callin) != cpus) {
969 if (mce_timed_out(&timeout,
970 "Timeout: Not all CPUs entered broadcast exception handler")) {
971 atomic_set(&global_nwo, 0);
978 * mce_callin should be read before global_nwo
984 * Monarch: Starts executing now, the others wait.
986 atomic_set(&mce_executing, 1);
989 * Subject: Now start the scanning loop one by one in
990 * the original callin order.
991 * This way when there are any shared banks it will be
992 * only seen by one CPU before cleared, avoiding duplicates.
994 while (atomic_read(&mce_executing) < order) {
995 if (mce_timed_out(&timeout,
996 "Timeout: Subject CPUs unable to finish machine check processing")) {
997 atomic_set(&global_nwo, 0);
1005 * Cache the global no_way_out state.
1007 *no_way_out = atomic_read(&global_nwo);
1013 * Synchronize between CPUs after main scanning loop.
1014 * This invokes the bulk of the Monarch processing.
1016 static int mce_end(int order)
1019 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1027 * Allow others to run.
1029 atomic_inc(&mce_executing);
1032 /* CHECKME: Can this race with a parallel hotplug? */
1033 int cpus = num_online_cpus();
1036 * Monarch: Wait for everyone to go through their scanning
1039 while (atomic_read(&mce_executing) <= cpus) {
1040 if (mce_timed_out(&timeout,
1041 "Timeout: Monarch CPU unable to finish machine check processing"))
1051 * Subject: Wait for Monarch to finish.
1053 while (atomic_read(&mce_executing) != 0) {
1054 if (mce_timed_out(&timeout,
1055 "Timeout: Monarch CPU did not finish machine check processing"))
1061 * Don't reset anything. That's done by the Monarch.
1067 * Reset all global state.
1070 atomic_set(&global_nwo, 0);
1071 atomic_set(&mce_callin, 0);
1075 * Let others run again.
1077 atomic_set(&mce_executing, 0);
1081 static void mce_clear_state(unsigned long *toclear)
1085 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1086 if (test_bit(i, toclear))
1087 mce_wrmsrl(msr_ops.status(i), 0);
1092 * Cases where we avoid rendezvous handler timeout:
1093 * 1) If this CPU is offline.
1095 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1096 * skip those CPUs which remain looping in the 1st kernel - see
1097 * crash_nmi_callback().
1099 * Note: there still is a small window between kexec-ing and the new,
1100 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1101 * might not get handled properly.
1103 static noinstr bool mce_check_crashing_cpu(void)
1105 unsigned int cpu = smp_processor_id();
1107 if (cpu_is_offline(cpu) ||
1108 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1111 mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS);
1113 if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
1114 if (mcgstatus & MCG_STATUS_LMCES)
1118 if (mcgstatus & MCG_STATUS_RIPV) {
1119 __wrmsr(MSR_IA32_MCG_STATUS, 0, 0);
1126 static void __mc_scan_banks(struct mce *m, struct mce *final,
1127 unsigned long *toclear, unsigned long *valid_banks,
1128 int no_way_out, int *worst)
1130 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1131 struct mca_config *cfg = &mca_cfg;
1134 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1135 __clear_bit(i, toclear);
1136 if (!test_bit(i, valid_banks))
1139 if (!mce_banks[i].ctl)
1146 m->status = mce_rdmsrl(msr_ops.status(i));
1147 if (!(m->status & MCI_STATUS_VAL))
1151 * Corrected or non-signaled errors are handled by
1152 * machine_check_poll(). Leave them alone, unless this panics.
1154 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1158 /* Set taint even when machine check was not enabled. */
1159 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1161 severity = mce_severity(m, cfg->tolerant, NULL, true);
1164 * When machine check was for corrected/deferred handler don't
1165 * touch, unless we're panicking.
1167 if ((severity == MCE_KEEP_SEVERITY ||
1168 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1171 __set_bit(i, toclear);
1173 /* Machine check event was not enabled. Clear, but ignore. */
1174 if (severity == MCE_NO_SEVERITY)
1179 /* assuming valid severity level != 0 */
1180 m->severity = severity;
1184 if (severity > *worst) {
1190 /* mce_clear_state will clear *final, save locally for use later */
1194 static void kill_me_now(struct callback_head *ch)
1199 static void kill_me_maybe(struct callback_head *cb)
1201 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1202 int flags = MF_ACTION_REQUIRED;
1204 pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr);
1205 if (!(p->mce_status & MCG_STATUS_RIPV))
1206 flags |= MF_MUST_KILL;
1208 if (!memory_failure(p->mce_addr >> PAGE_SHIFT, flags)) {
1209 set_mce_nospec(p->mce_addr >> PAGE_SHIFT);
1213 pr_err("Memory error not recovered");
1218 * The actual machine check handler. This only handles real
1219 * exceptions when something got corrupted coming in through int 18.
1221 * This is executed in NMI context not subject to normal locking rules. This
1222 * implies that most kernel services cannot be safely used. Don't even
1223 * think about putting a printk in there!
1225 * On Intel systems this is entered on all CPUs in parallel through
1226 * MCE broadcast. However some CPUs might be broken beyond repair,
1227 * so be always careful when synchronizing with others.
1229 * Tracing and kprobes are disabled: if we interrupted a kernel context
1230 * with IF=1, we need to minimize stack usage. There are also recursion
1231 * issues: if the machine check was due to a failure of the memory
1232 * backing the user stack, tracing that reads the user stack will cause
1233 * potentially infinite recursion.
1235 void noinstr do_machine_check(struct pt_regs *regs)
1237 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1238 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1239 struct mca_config *cfg = &mca_cfg;
1240 struct mce m, *final;
1245 * Establish sequential order between the CPUs entering the machine
1251 * If no_way_out gets set, there is no safe way to recover from this
1252 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1257 * If kill_it gets set, there might be a way to recover from this
1263 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1268 this_cpu_inc(mce_exception_count);
1270 mce_gather_info(&m, regs);
1273 final = this_cpu_ptr(&mces_seen);
1276 memset(valid_banks, 0, sizeof(valid_banks));
1277 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1282 * When no restart IP might need to kill or panic.
1283 * Assume the worst for now, but if we find the
1284 * severity is MCE_AR_SEVERITY we have other options.
1286 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1290 * Check if this MCE is signaled to only this logical processor,
1291 * on Intel, Zhaoxin only.
1293 if (m.cpuvendor == X86_VENDOR_INTEL ||
1294 m.cpuvendor == X86_VENDOR_ZHAOXIN)
1295 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1298 * Local machine check may already know that we have to panic.
1299 * Broadcast machine check begins rendezvous in mce_start()
1300 * Go through all banks in exclusion of the other CPUs. This way we
1301 * don't report duplicated events on shared banks because the first one
1302 * to see it will clear it.
1306 mce_panic("Fatal local machine check", &m, msg);
1308 order = mce_start(&no_way_out);
1311 __mc_scan_banks(&m, final, toclear, valid_banks, no_way_out, &worst);
1314 mce_clear_state(toclear);
1317 * Do most of the synchronization with other CPUs.
1318 * When there's any problem use only local no_way_out state.
1321 if (mce_end(order) < 0)
1322 no_way_out = worst >= MCE_PANIC_SEVERITY;
1325 * If there was a fatal machine check we should have
1326 * already called mce_panic earlier in this function.
1327 * Since we re-read the banks, we might have found
1328 * something new. Check again to see if we found a
1329 * fatal error. We call "mce_severity()" again to
1330 * make sure we have the right "msg".
1332 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
1333 mce_severity(&m, cfg->tolerant, &msg, true);
1334 mce_panic("Local fatal machine check!", &m, msg);
1339 * If tolerant is at an insane level we drop requests to kill
1340 * processes and continue even when there is no way out.
1342 if (cfg->tolerant == 3)
1344 else if (no_way_out)
1345 mce_panic("Fatal machine check on current CPU", &m, msg);
1348 irq_work_queue(&mce_irq_work);
1350 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1354 if (worst != MCE_AR_SEVERITY && !kill_it)
1357 /* Fault was in user mode and we need to take some action */
1358 if ((m.cs & 3) == 3) {
1359 /* If this triggers there is no way to recover. Die hard. */
1360 BUG_ON(!on_thread_stack() || !user_mode(regs));
1362 current->mce_addr = m.addr;
1363 current->mce_status = m.mcgstatus;
1364 current->mce_kill_me.func = kill_me_maybe;
1366 current->mce_kill_me.func = kill_me_now;
1367 task_work_add(current, ¤t->mce_kill_me, true);
1369 if (!fixup_exception(regs, X86_TRAP_MC, 0, 0))
1370 mce_panic("Failed kernel mode recovery", &m, msg);
1373 EXPORT_SYMBOL_GPL(do_machine_check);
1375 #ifndef CONFIG_MEMORY_FAILURE
1376 int memory_failure(unsigned long pfn, int flags)
1378 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1379 BUG_ON(flags & MF_ACTION_REQUIRED);
1380 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1381 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1389 * Periodic polling timer for "silent" machine check errors. If the
1390 * poller finds an MCE, poll 2x faster. When the poller finds no more
1391 * errors, poll 2x slower (up to check_interval seconds).
1393 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1395 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1396 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1398 static unsigned long mce_adjust_timer_default(unsigned long interval)
1403 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1405 static void __start_timer(struct timer_list *t, unsigned long interval)
1407 unsigned long when = jiffies + interval;
1408 unsigned long flags;
1410 local_irq_save(flags);
1412 if (!timer_pending(t) || time_before(when, t->expires))
1413 mod_timer(t, round_jiffies(when));
1415 local_irq_restore(flags);
1418 static void mce_timer_fn(struct timer_list *t)
1420 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1423 WARN_ON(cpu_t != t);
1425 iv = __this_cpu_read(mce_next_interval);
1427 if (mce_available(this_cpu_ptr(&cpu_info))) {
1428 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1430 if (mce_intel_cmci_poll()) {
1431 iv = mce_adjust_timer(iv);
1437 * Alert userspace if needed. If we logged an MCE, reduce the polling
1438 * interval, otherwise increase the polling interval.
1440 if (mce_notify_irq())
1441 iv = max(iv / 2, (unsigned long) HZ/100);
1443 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1446 __this_cpu_write(mce_next_interval, iv);
1447 __start_timer(t, iv);
1451 * Ensure that the timer is firing in @interval from now.
1453 void mce_timer_kick(unsigned long interval)
1455 struct timer_list *t = this_cpu_ptr(&mce_timer);
1456 unsigned long iv = __this_cpu_read(mce_next_interval);
1458 __start_timer(t, interval);
1461 __this_cpu_write(mce_next_interval, interval);
1464 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1465 static void mce_timer_delete_all(void)
1469 for_each_online_cpu(cpu)
1470 del_timer_sync(&per_cpu(mce_timer, cpu));
1474 * Notify the user(s) about new machine check events.
1475 * Can be called from interrupt context, but not from machine check/NMI
1478 int mce_notify_irq(void)
1480 /* Not more than two messages every minute */
1481 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1483 if (test_and_clear_bit(0, &mce_need_notify)) {
1486 if (__ratelimit(&ratelimit))
1487 pr_info(HW_ERR "Machine check events logged\n");
1493 EXPORT_SYMBOL_GPL(mce_notify_irq);
1495 static void __mcheck_cpu_mce_banks_init(void)
1497 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1498 u8 n_banks = this_cpu_read(mce_num_banks);
1501 for (i = 0; i < n_banks; i++) {
1502 struct mce_bank *b = &mce_banks[i];
1505 * Init them all, __mcheck_cpu_apply_quirks() is going to apply
1506 * the required vendor quirks before
1507 * __mcheck_cpu_init_clear_banks() does the final bank setup.
1515 * Initialize Machine Checks for a CPU.
1517 static void __mcheck_cpu_cap_init(void)
1522 rdmsrl(MSR_IA32_MCG_CAP, cap);
1524 b = cap & MCG_BANKCNT_MASK;
1526 if (b > MAX_NR_BANKS) {
1527 pr_warn("CPU%d: Using only %u machine check banks out of %u\n",
1528 smp_processor_id(), MAX_NR_BANKS, b);
1532 this_cpu_write(mce_num_banks, b);
1534 __mcheck_cpu_mce_banks_init();
1536 /* Use accurate RIP reporting if available. */
1537 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1538 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1540 if (cap & MCG_SER_P)
1544 static void __mcheck_cpu_init_generic(void)
1546 enum mcp_flags m_fl = 0;
1547 mce_banks_t all_banks;
1550 if (!mca_cfg.bootlog)
1554 * Log the machine checks left over from the previous reset.
1556 bitmap_fill(all_banks, MAX_NR_BANKS);
1557 machine_check_poll(MCP_UC | m_fl, &all_banks);
1559 cr4_set_bits(X86_CR4_MCE);
1561 rdmsrl(MSR_IA32_MCG_CAP, cap);
1562 if (cap & MCG_CTL_P)
1563 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1566 static void __mcheck_cpu_init_clear_banks(void)
1568 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1571 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1572 struct mce_bank *b = &mce_banks[i];
1576 wrmsrl(msr_ops.ctl(i), b->ctl);
1577 wrmsrl(msr_ops.status(i), 0);
1582 * Do a final check to see if there are any unused/RAZ banks.
1584 * This must be done after the banks have been initialized and any quirks have
1587 * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs.
1588 * Otherwise, a user who disables a bank will not be able to re-enable it
1589 * without a system reboot.
1591 static void __mcheck_cpu_check_banks(void)
1593 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1597 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1598 struct mce_bank *b = &mce_banks[i];
1603 rdmsrl(msr_ops.ctl(i), msrval);
1609 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1610 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1611 * Vol 3B Table 15-20). But this confuses both the code that determines
1612 * whether the machine check occurred in kernel or user mode, and also
1613 * the severity assessment code. Pretend that EIPV was set, and take the
1614 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1616 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1620 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1622 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1623 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1624 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1626 (MCI_STATUS_UC|MCI_STATUS_EN|
1627 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1628 MCI_STATUS_AR|MCACOD_INSTR))
1631 m->mcgstatus |= MCG_STATUS_EIPV;
1636 /* Add per CPU specific workarounds here */
1637 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1639 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1640 struct mca_config *cfg = &mca_cfg;
1642 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1643 pr_info("unknown CPU type - not enabling MCE support\n");
1647 /* This should be disabled by the BIOS, but isn't always */
1648 if (c->x86_vendor == X86_VENDOR_AMD) {
1649 if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
1651 * disable GART TBL walk error reporting, which
1652 * trips off incorrectly with the IOMMU & 3ware
1655 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1657 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1659 * Lots of broken BIOS around that don't clear them
1660 * by default and leave crap in there. Don't log:
1665 * Various K7s with broken bank 0 around. Always disable
1668 if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1669 mce_banks[0].ctl = 0;
1672 * overflow_recov is supported for F15h Models 00h-0fh
1673 * even though we don't have a CPUID bit for it.
1675 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1676 mce_flags.overflow_recov = 1;
1680 if (c->x86_vendor == X86_VENDOR_INTEL) {
1682 * SDM documents that on family 6 bank 0 should not be written
1683 * because it aliases to another special BIOS controlled
1685 * But it's not aliased anymore on model 0x1a+
1686 * Don't ignore bank 0 completely because there could be a
1687 * valid event later, merely don't write CTL0.
1690 if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1691 mce_banks[0].init = 0;
1694 * All newer Intel systems support MCE broadcasting. Enable
1695 * synchronization with a one second timeout.
1697 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1698 cfg->monarch_timeout < 0)
1699 cfg->monarch_timeout = USEC_PER_SEC;
1702 * There are also broken BIOSes on some Pentium M and
1705 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1708 if (c->x86 == 6 && c->x86_model == 45)
1709 quirk_no_way_out = quirk_sandybridge_ifu;
1712 if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
1714 * All newer Zhaoxin CPUs support MCE broadcasting. Enable
1715 * synchronization with a one second timeout.
1717 if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1718 if (cfg->monarch_timeout < 0)
1719 cfg->monarch_timeout = USEC_PER_SEC;
1723 if (cfg->monarch_timeout < 0)
1724 cfg->monarch_timeout = 0;
1725 if (cfg->bootlog != 0)
1726 cfg->panic_timeout = 30;
1731 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1736 switch (c->x86_vendor) {
1737 case X86_VENDOR_INTEL:
1738 intel_p5_mcheck_init(c);
1741 case X86_VENDOR_CENTAUR:
1742 winchip_mcheck_init(c);
1753 * Init basic CPU features needed for early decoding of MCEs.
1755 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1757 if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
1758 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1759 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1760 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1762 if (mce_flags.smca) {
1763 msr_ops.ctl = smca_ctl_reg;
1764 msr_ops.status = smca_status_reg;
1765 msr_ops.addr = smca_addr_reg;
1766 msr_ops.misc = smca_misc_reg;
1771 static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1773 struct mca_config *cfg = &mca_cfg;
1776 * All newer Centaur CPUs support MCE broadcasting. Enable
1777 * synchronization with a one second timeout.
1779 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1781 if (cfg->monarch_timeout < 0)
1782 cfg->monarch_timeout = USEC_PER_SEC;
1786 static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
1788 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1791 * These CPUs have MCA bank 8 which reports only one error type called
1792 * SVAD (System View Address Decoder). The reporting of that error is
1793 * controlled by IA32_MC8.CTL.0.
1795 * If enabled, prefetching on these CPUs will cause SVAD MCE when
1796 * virtual machines start and result in a system panic. Always disable
1797 * bank 8 SVAD error by default.
1799 if ((c->x86 == 7 && c->x86_model == 0x1b) ||
1800 (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1801 if (this_cpu_read(mce_num_banks) > 8)
1802 mce_banks[8].ctl = 0;
1807 mce_adjust_timer = cmci_intel_adjust_timer;
1810 static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
1815 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1817 switch (c->x86_vendor) {
1818 case X86_VENDOR_INTEL:
1819 mce_intel_feature_init(c);
1820 mce_adjust_timer = cmci_intel_adjust_timer;
1823 case X86_VENDOR_AMD: {
1824 mce_amd_feature_init(c);
1828 case X86_VENDOR_HYGON:
1829 mce_hygon_feature_init(c);
1832 case X86_VENDOR_CENTAUR:
1833 mce_centaur_feature_init(c);
1836 case X86_VENDOR_ZHAOXIN:
1837 mce_zhaoxin_feature_init(c);
1845 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1847 switch (c->x86_vendor) {
1848 case X86_VENDOR_INTEL:
1849 mce_intel_feature_clear(c);
1852 case X86_VENDOR_ZHAOXIN:
1853 mce_zhaoxin_feature_clear(c);
1861 static void mce_start_timer(struct timer_list *t)
1863 unsigned long iv = check_interval * HZ;
1865 if (mca_cfg.ignore_ce || !iv)
1868 this_cpu_write(mce_next_interval, iv);
1869 __start_timer(t, iv);
1872 static void __mcheck_cpu_setup_timer(void)
1874 struct timer_list *t = this_cpu_ptr(&mce_timer);
1876 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1879 static void __mcheck_cpu_init_timer(void)
1881 struct timer_list *t = this_cpu_ptr(&mce_timer);
1883 timer_setup(t, mce_timer_fn, TIMER_PINNED);
1887 bool filter_mce(struct mce *m)
1889 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1890 return amd_filter_mce(m);
1891 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1892 return intel_filter_mce(m);
1897 /* Handle unconfigured int18 (should never happen) */
1898 static void unexpected_machine_check(struct pt_regs *regs)
1900 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1901 smp_processor_id());
1904 /* Call the installed machine check handler for this CPU setup. */
1905 void (*machine_check_vector)(struct pt_regs *) = unexpected_machine_check;
1907 static __always_inline void exc_machine_check_kernel(struct pt_regs *regs)
1910 * Only required when from kernel mode. See
1911 * mce_check_crashing_cpu() for details.
1913 if (machine_check_vector == do_machine_check &&
1914 mce_check_crashing_cpu())
1918 machine_check_vector(regs);
1922 static __always_inline void exc_machine_check_user(struct pt_regs *regs)
1924 idtentry_enter(regs);
1925 machine_check_vector(regs);
1926 idtentry_exit(regs);
1929 #ifdef CONFIG_X86_64
1930 /* MCE hit kernel mode */
1931 DEFINE_IDTENTRY_MCE(exc_machine_check)
1933 exc_machine_check_kernel(regs);
1936 /* The user mode variant. */
1937 DEFINE_IDTENTRY_MCE_USER(exc_machine_check)
1939 exc_machine_check_user(regs);
1942 /* 32bit unified entry point */
1943 DEFINE_IDTENTRY_MCE(exc_machine_check)
1945 if (user_mode(regs))
1946 exc_machine_check_user(regs);
1948 exc_machine_check_kernel(regs);
1953 * Called for each booted CPU to set up machine checks.
1954 * Must be called with preempt off:
1956 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1958 if (mca_cfg.disabled)
1961 if (__mcheck_cpu_ancient_init(c))
1964 if (!mce_available(c))
1967 __mcheck_cpu_cap_init();
1969 if (__mcheck_cpu_apply_quirks(c) < 0) {
1970 mca_cfg.disabled = 1;
1974 if (mce_gen_pool_init()) {
1975 mca_cfg.disabled = 1;
1976 pr_emerg("Couldn't allocate MCE records pool!\n");
1980 machine_check_vector = do_machine_check;
1982 __mcheck_cpu_init_early(c);
1983 __mcheck_cpu_init_generic();
1984 __mcheck_cpu_init_vendor(c);
1985 __mcheck_cpu_init_clear_banks();
1986 __mcheck_cpu_check_banks();
1987 __mcheck_cpu_setup_timer();
1991 * Called for each booted CPU to clear some machine checks opt-ins
1993 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
1995 if (mca_cfg.disabled)
1998 if (!mce_available(c))
2002 * Possibly to clear general settings generic to x86
2003 * __mcheck_cpu_clear_generic(c);
2005 __mcheck_cpu_clear_vendor(c);
2009 static void __mce_disable_bank(void *arg)
2011 int bank = *((int *)arg);
2012 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
2013 cmci_disable_bank(bank);
2016 void mce_disable_bank(int bank)
2018 if (bank >= this_cpu_read(mce_num_banks)) {
2020 "Ignoring request to disable invalid MCA bank %d.\n",
2024 set_bit(bank, mce_banks_ce_disabled);
2025 on_each_cpu(__mce_disable_bank, &bank, 1);
2029 * mce=off Disables machine check
2030 * mce=no_cmci Disables CMCI
2031 * mce=no_lmce Disables LMCE
2032 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2033 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2034 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2035 * monarchtimeout is how long to wait for other CPUs on machine
2036 * check, or 0 to not wait
2037 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
2039 * mce=nobootlog Don't log MCEs from before booting.
2040 * mce=bios_cmci_threshold Don't program the CMCI threshold
2041 * mce=recovery force enable memcpy_mcsafe()
2043 static int __init mcheck_enable(char *str)
2045 struct mca_config *cfg = &mca_cfg;
2053 if (!strcmp(str, "off"))
2055 else if (!strcmp(str, "no_cmci"))
2056 cfg->cmci_disabled = true;
2057 else if (!strcmp(str, "no_lmce"))
2058 cfg->lmce_disabled = 1;
2059 else if (!strcmp(str, "dont_log_ce"))
2060 cfg->dont_log_ce = true;
2061 else if (!strcmp(str, "ignore_ce"))
2062 cfg->ignore_ce = true;
2063 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2064 cfg->bootlog = (str[0] == 'b');
2065 else if (!strcmp(str, "bios_cmci_threshold"))
2066 cfg->bios_cmci_threshold = 1;
2067 else if (!strcmp(str, "recovery"))
2069 else if (isdigit(str[0])) {
2070 if (get_option(&str, &cfg->tolerant) == 2)
2071 get_option(&str, &(cfg->monarch_timeout));
2073 pr_info("mce argument %s ignored. Please use /sys\n", str);
2078 __setup("mce", mcheck_enable);
2080 int __init mcheck_init(void)
2082 mcheck_intel_therm_init();
2083 mce_register_decode_chain(&first_nb);
2084 mce_register_decode_chain(&mce_uc_nb);
2085 mce_register_decode_chain(&mce_default_nb);
2086 mcheck_vendor_init_severity();
2088 INIT_WORK(&mce_work, mce_gen_pool_process);
2089 init_irq_work(&mce_irq_work, mce_irq_work_cb);
2095 * mce_syscore: PM support
2099 * Disable machine checks on suspend and shutdown. We can't really handle
2102 static void mce_disable_error_reporting(void)
2104 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2107 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2108 struct mce_bank *b = &mce_banks[i];
2111 wrmsrl(msr_ops.ctl(i), 0);
2116 static void vendor_disable_error_reporting(void)
2119 * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
2120 * MSRs are socket-wide. Disabling them for just a single offlined CPU
2121 * is bad, since it will inhibit reporting for all shared resources on
2122 * the socket like the last level cache (LLC), the integrated memory
2123 * controller (iMC), etc.
2125 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
2126 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
2127 boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
2128 boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
2131 mce_disable_error_reporting();
2134 static int mce_syscore_suspend(void)
2136 vendor_disable_error_reporting();
2140 static void mce_syscore_shutdown(void)
2142 vendor_disable_error_reporting();
2146 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2147 * Only one CPU is active at this time, the others get re-added later using
2150 static void mce_syscore_resume(void)
2152 __mcheck_cpu_init_generic();
2153 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2154 __mcheck_cpu_init_clear_banks();
2157 static struct syscore_ops mce_syscore_ops = {
2158 .suspend = mce_syscore_suspend,
2159 .shutdown = mce_syscore_shutdown,
2160 .resume = mce_syscore_resume,
2164 * mce_device: Sysfs support
2167 static void mce_cpu_restart(void *data)
2169 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2171 __mcheck_cpu_init_generic();
2172 __mcheck_cpu_init_clear_banks();
2173 __mcheck_cpu_init_timer();
2176 /* Reinit MCEs after user configuration changes */
2177 static void mce_restart(void)
2179 mce_timer_delete_all();
2180 on_each_cpu(mce_cpu_restart, NULL, 1);
2183 /* Toggle features for corrected errors */
2184 static void mce_disable_cmci(void *data)
2186 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2191 static void mce_enable_ce(void *all)
2193 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2198 __mcheck_cpu_init_timer();
2201 static struct bus_type mce_subsys = {
2202 .name = "machinecheck",
2203 .dev_name = "machinecheck",
2206 DEFINE_PER_CPU(struct device *, mce_device);
2208 static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr)
2210 return container_of(attr, struct mce_bank_dev, attr);
2213 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2216 u8 bank = attr_to_bank(attr)->bank;
2219 if (bank >= per_cpu(mce_num_banks, s->id))
2222 b = &per_cpu(mce_banks_array, s->id)[bank];
2227 return sprintf(buf, "%llx\n", b->ctl);
2230 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2231 const char *buf, size_t size)
2233 u8 bank = attr_to_bank(attr)->bank;
2237 if (kstrtou64(buf, 0, &new) < 0)
2240 if (bank >= per_cpu(mce_num_banks, s->id))
2243 b = &per_cpu(mce_banks_array, s->id)[bank];
2254 static ssize_t set_ignore_ce(struct device *s,
2255 struct device_attribute *attr,
2256 const char *buf, size_t size)
2260 if (kstrtou64(buf, 0, &new) < 0)
2263 mutex_lock(&mce_sysfs_mutex);
2264 if (mca_cfg.ignore_ce ^ !!new) {
2266 /* disable ce features */
2267 mce_timer_delete_all();
2268 on_each_cpu(mce_disable_cmci, NULL, 1);
2269 mca_cfg.ignore_ce = true;
2271 /* enable ce features */
2272 mca_cfg.ignore_ce = false;
2273 on_each_cpu(mce_enable_ce, (void *)1, 1);
2276 mutex_unlock(&mce_sysfs_mutex);
2281 static ssize_t set_cmci_disabled(struct device *s,
2282 struct device_attribute *attr,
2283 const char *buf, size_t size)
2287 if (kstrtou64(buf, 0, &new) < 0)
2290 mutex_lock(&mce_sysfs_mutex);
2291 if (mca_cfg.cmci_disabled ^ !!new) {
2294 on_each_cpu(mce_disable_cmci, NULL, 1);
2295 mca_cfg.cmci_disabled = true;
2298 mca_cfg.cmci_disabled = false;
2299 on_each_cpu(mce_enable_ce, NULL, 1);
2302 mutex_unlock(&mce_sysfs_mutex);
2307 static ssize_t store_int_with_restart(struct device *s,
2308 struct device_attribute *attr,
2309 const char *buf, size_t size)
2311 unsigned long old_check_interval = check_interval;
2312 ssize_t ret = device_store_ulong(s, attr, buf, size);
2314 if (check_interval == old_check_interval)
2317 mutex_lock(&mce_sysfs_mutex);
2319 mutex_unlock(&mce_sysfs_mutex);
2324 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2325 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2326 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2328 static struct dev_ext_attribute dev_attr_check_interval = {
2329 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2333 static struct dev_ext_attribute dev_attr_ignore_ce = {
2334 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2338 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2339 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2340 &mca_cfg.cmci_disabled
2343 static struct device_attribute *mce_device_attrs[] = {
2344 &dev_attr_tolerant.attr,
2345 &dev_attr_check_interval.attr,
2346 #ifdef CONFIG_X86_MCELOG_LEGACY
2349 &dev_attr_monarch_timeout.attr,
2350 &dev_attr_dont_log_ce.attr,
2351 &dev_attr_ignore_ce.attr,
2352 &dev_attr_cmci_disabled.attr,
2356 static cpumask_var_t mce_device_initialized;
2358 static void mce_device_release(struct device *dev)
2363 /* Per CPU device init. All of the CPUs still share the same bank device: */
2364 static int mce_device_create(unsigned int cpu)
2370 if (!mce_available(&boot_cpu_data))
2373 dev = per_cpu(mce_device, cpu);
2377 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2381 dev->bus = &mce_subsys;
2382 dev->release = &mce_device_release;
2384 err = device_register(dev);
2390 for (i = 0; mce_device_attrs[i]; i++) {
2391 err = device_create_file(dev, mce_device_attrs[i]);
2395 for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) {
2396 err = device_create_file(dev, &mce_bank_devs[j].attr);
2400 cpumask_set_cpu(cpu, mce_device_initialized);
2401 per_cpu(mce_device, cpu) = dev;
2406 device_remove_file(dev, &mce_bank_devs[j].attr);
2409 device_remove_file(dev, mce_device_attrs[i]);
2411 device_unregister(dev);
2416 static void mce_device_remove(unsigned int cpu)
2418 struct device *dev = per_cpu(mce_device, cpu);
2421 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2424 for (i = 0; mce_device_attrs[i]; i++)
2425 device_remove_file(dev, mce_device_attrs[i]);
2427 for (i = 0; i < per_cpu(mce_num_banks, cpu); i++)
2428 device_remove_file(dev, &mce_bank_devs[i].attr);
2430 device_unregister(dev);
2431 cpumask_clear_cpu(cpu, mce_device_initialized);
2432 per_cpu(mce_device, cpu) = NULL;
2435 /* Make sure there are no machine checks on offlined CPUs. */
2436 static void mce_disable_cpu(void)
2438 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2441 if (!cpuhp_tasks_frozen)
2444 vendor_disable_error_reporting();
2447 static void mce_reenable_cpu(void)
2449 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2452 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2455 if (!cpuhp_tasks_frozen)
2457 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2458 struct mce_bank *b = &mce_banks[i];
2461 wrmsrl(msr_ops.ctl(i), b->ctl);
2465 static int mce_cpu_dead(unsigned int cpu)
2467 mce_intel_hcpu_update(cpu);
2469 /* intentionally ignoring frozen here */
2470 if (!cpuhp_tasks_frozen)
2475 static int mce_cpu_online(unsigned int cpu)
2477 struct timer_list *t = this_cpu_ptr(&mce_timer);
2480 mce_device_create(cpu);
2482 ret = mce_threshold_create_device(cpu);
2484 mce_device_remove(cpu);
2492 static int mce_cpu_pre_down(unsigned int cpu)
2494 struct timer_list *t = this_cpu_ptr(&mce_timer);
2498 mce_threshold_remove_device(cpu);
2499 mce_device_remove(cpu);
2503 static __init void mce_init_banks(void)
2507 for (i = 0; i < MAX_NR_BANKS; i++) {
2508 struct mce_bank_dev *b = &mce_bank_devs[i];
2509 struct device_attribute *a = &b->attr;
2513 sysfs_attr_init(&a->attr);
2514 a->attr.name = b->attrname;
2515 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2517 a->attr.mode = 0644;
2518 a->show = show_bank;
2519 a->store = set_bank;
2523 static __init int mcheck_init_device(void)
2528 * Check if we have a spare virtual bit. This will only become
2529 * a problem if/when we move beyond 5-level page tables.
2531 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2533 if (!mce_available(&boot_cpu_data)) {
2538 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2545 err = subsys_system_register(&mce_subsys, NULL);
2549 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2554 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2555 mce_cpu_online, mce_cpu_pre_down);
2557 goto err_out_online;
2559 register_syscore_ops(&mce_syscore_ops);
2564 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2567 free_cpumask_var(mce_device_initialized);
2570 pr_err("Unable to init MCE device (rc: %d)\n", err);
2574 device_initcall_sync(mcheck_init_device);
2577 * Old style boot options parsing. Only for compatibility.
2579 static int __init mcheck_disable(char *str)
2581 mca_cfg.disabled = 1;
2584 __setup("nomce", mcheck_disable);
2586 #ifdef CONFIG_DEBUG_FS
2587 struct dentry *mce_get_debugfs_dir(void)
2589 static struct dentry *dmce;
2592 dmce = debugfs_create_dir("mce", NULL);
2597 static void mce_reset(void)
2600 atomic_set(&mce_fake_panicked, 0);
2601 atomic_set(&mce_executing, 0);
2602 atomic_set(&mce_callin, 0);
2603 atomic_set(&global_nwo, 0);
2606 static int fake_panic_get(void *data, u64 *val)
2612 static int fake_panic_set(void *data, u64 val)
2619 DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set,
2622 static void __init mcheck_debugfs_init(void)
2624 struct dentry *dmce;
2626 dmce = mce_get_debugfs_dir();
2627 debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL,
2631 static void __init mcheck_debugfs_init(void) { }
2634 DEFINE_STATIC_KEY_FALSE(mcsafe_key);
2635 EXPORT_SYMBOL_GPL(mcsafe_key);
2637 static int __init mcheck_late_init(void)
2639 if (mca_cfg.recovery)
2640 static_branch_inc(&mcsafe_key);
2642 mcheck_debugfs_init();
2646 * Flush out everything that has been logged during early boot, now that
2647 * everything has been initialized (workqueues, decoders, ...).
2649 mce_schedule_work();
2653 late_initcall(mcheck_late_init);