arch/x86/kernel/cpu/mce/amd.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  (c) 2005-2016 Advanced Micro Devices, Inc.
   4  *
   5  *  Written by Jacob Shin - AMD, Inc.
   6  *  Maintained by: Borislav Petkov <bp@alien8.de>
   7  *
   8  *  All MC4_MISCi registers are shared between cores on a node.
   9  */
  10 #include <linux/interrupt.h>
  11 #include <linux/notifier.h>
  12 #include <linux/kobject.h>
  13 #include <linux/percpu.h>
  14 #include <linux/errno.h>
  15 #include <linux/sched.h>
  16 #include <linux/sysfs.h>
  17 #include <linux/slab.h>
  18 #include <linux/init.h>
  19 #include <linux/cpu.h>
  20 #include <linux/smp.h>
  21 #include <linux/string.h>
  22
  23 #include <asm/amd_nb.h>
  24 #include <asm/traps.h>
  25 #include <asm/apic.h>
  26 #include <asm/mce.h>
  27 #include <asm/msr.h>
  28 #include <asm/trace/irq_vectors.h>
  29
  30 #include "internal.h"
  31
  32 #define NR_BLOCKS         5
  33 #define THRESHOLD_MAX     0xFFF
  34 #define INT_TYPE_APIC     0x00020000
  35 #define MASK_VALID_HI     0x80000000
  36 #define MASK_CNTP_HI      0x40000000
  37 #define MASK_LOCKED_HI    0x20000000
  38 #define MASK_LVTOFF_HI    0x00F00000
  39 #define MASK_COUNT_EN_HI  0x00080000
  40 #define MASK_INT_TYPE_HI  0x00060000
  41 #define MASK_OVERFLOW_HI  0x00010000
  42 #define MASK_ERR_COUNT_HI 0x00000FFF
  43 #define MASK_BLKPTR_LO    0xFF000000
  44 #define MCG_XBLK_ADDR     0xC0000400
  45
  46 /* Deferred error settings */
  47 #define MSR_CU_DEF_ERR          0xC0000410
  48 #define MASK_DEF_LVTOFF         0x000000F0
  49 #define MASK_DEF_INT_TYPE       0x00000006
  50 #define DEF_LVT_OFF             0x2
  51 #define DEF_INT_TYPE_APIC       0x2
  52
  53 /* Scalable MCA: */
  54
  55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
  56 #define SMCA_THR_LVT_OFF        0xF000
  57
  58 static bool thresholding_irq_en;
  59
  60 static const char * const th_names[] = {
  61         "load_store",
  62         "insn_fetch",
  63         "combined_unit",
  64         "decode_unit",
  65         "northbridge",
  66         "execution_unit",
  67 };
  68
  69 static const char * const smca_umc_block_names[] = {
  70         "dram_ecc",
  71         "misc_umc"
  72 };
  73
  74 struct smca_bank_name {
  75         const char *name;       /* Short name for sysfs */
  76         const char *long_name;  /* Long name for pretty-printing */
  77 };
  78
  79 static struct smca_bank_name smca_names[] = {
  80         [SMCA_LS]       = { "load_store",       "Load Store Unit" },
  81         [SMCA_LS_V2]    = { "load_store",       "Load Store Unit" },
  82         [SMCA_IF]       = { "insn_fetch",       "Instruction Fetch Unit" },
  83         [SMCA_L2_CACHE] = { "l2_cache",         "L2 Cache" },
  84         [SMCA_DE]       = { "decode_unit",      "Decode Unit" },
  85         [SMCA_RESERVED] = { "reserved",         "Reserved" },
  86         [SMCA_EX]       = { "execution_unit",   "Execution Unit" },
  87         [SMCA_FP]       = { "floating_point",   "Floating Point Unit" },
  88         [SMCA_L3_CACHE] = { "l3_cache",         "L3 Cache" },
  89         [SMCA_CS]       = { "coherent_slave",   "Coherent Slave" },
  90         [SMCA_CS_V2]    = { "coherent_slave",   "Coherent Slave" },
  91         [SMCA_PIE]      = { "pie",              "Power, Interrupts, etc." },
  92         [SMCA_UMC]      = { "umc",              "Unified Memory Controller" },
  93         [SMCA_PB]       = { "param_block",      "Parameter Block" },
  94         [SMCA_PSP]      = { "psp",              "Platform Security Processor" },
  95         [SMCA_PSP_V2]   = { "psp",              "Platform Security Processor" },
  96         [SMCA_SMU]      = { "smu",              "System Management Unit" },
  97         [SMCA_SMU_V2]   = { "smu",              "System Management Unit" },
  98         [SMCA_MP5]      = { "mp5",              "Microprocessor 5 Unit" },
  99         [SMCA_NBIO]     = { "nbio",             "Northbridge IO Unit" },
 100         [SMCA_PCIE]     = { "pcie",             "PCI Express Unit" },
 101 };
 102
 103 static const char *smca_get_name(enum smca_bank_types t)
 104 {
 105         if (t >= N_SMCA_BANK_TYPES)
 106                 return NULL;
 107
 108         return smca_names[t].name;
 109 }
 110
 111 const char *smca_get_long_name(enum smca_bank_types t)
 112 {
 113         if (t >= N_SMCA_BANK_TYPES)
 114                 return NULL;
 115
 116         return smca_names[t].long_name;
 117 }
 118 EXPORT_SYMBOL_GPL(smca_get_long_name);
 119
 120 static enum smca_bank_types smca_get_bank_type(unsigned int bank)
 121 {
 122         struct smca_bank *b;
 123
 124         if (bank >= MAX_NR_BANKS)
 125                 return N_SMCA_BANK_TYPES;
 126
 127         b = &smca_banks[bank];
 128         if (!b->hwid)
 129                 return N_SMCA_BANK_TYPES;
 130
 131         return b->hwid->bank_type;
 132 }
 133
 134 static struct smca_hwid smca_hwid_mcatypes[] = {
 135         /* { bank_type, hwid_mcatype, xec_bitmap } */
 136
 137         /* Reserved type */
 138         { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 },
 139
 140         /* ZN Core (HWID=0xB0) MCA types */
 141         { SMCA_LS,       HWID_MCATYPE(0xB0, 0x0), 0x1FFFFF },
 142         { SMCA_LS_V2,    HWID_MCATYPE(0xB0, 0x10), 0xFFFFFF },
 143         { SMCA_IF,       HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
 144         { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
 145         { SMCA_DE,       HWID_MCATYPE(0xB0, 0x3), 0x1FF },
 146         /* HWID 0xB0 MCATYPE 0x4 is Reserved */
 147         { SMCA_EX,       HWID_MCATYPE(0xB0, 0x5), 0xFFF },
 148         { SMCA_FP,       HWID_MCATYPE(0xB0, 0x6), 0x7F },
 149         { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },
 150
 151         /* Data Fabric MCA types */
 152         { SMCA_CS,       HWID_MCATYPE(0x2E, 0x0), 0x1FF },
 153         { SMCA_PIE,      HWID_MCATYPE(0x2E, 0x1), 0x1F },
 154         { SMCA_CS_V2,    HWID_MCATYPE(0x2E, 0x2), 0x3FFF },
 155
 156         /* Unified Memory Controller MCA type */
 157         { SMCA_UMC,      HWID_MCATYPE(0x96, 0x0), 0xFF },
 158
 159         /* Parameter Block MCA type */
 160         { SMCA_PB,       HWID_MCATYPE(0x05, 0x0), 0x1 },
 161
 162         /* Platform Security Processor MCA type */
 163         { SMCA_PSP,      HWID_MCATYPE(0xFF, 0x0), 0x1 },
 164         { SMCA_PSP_V2,   HWID_MCATYPE(0xFF, 0x1), 0x3FFFF },
 165
 166         /* System Management Unit MCA type */
 167         { SMCA_SMU,      HWID_MCATYPE(0x01, 0x0), 0x1 },
 168         { SMCA_SMU_V2,   HWID_MCATYPE(0x01, 0x1), 0x7FF },
 169
 170         /* Microprocessor 5 Unit MCA type */
 171         { SMCA_MP5,      HWID_MCATYPE(0x01, 0x2), 0x3FF },
 172
 173         /* Northbridge IO Unit MCA type */
 174         { SMCA_NBIO,     HWID_MCATYPE(0x18, 0x0), 0x1F },
 175
 176         /* PCI Express Unit MCA type */
 177         { SMCA_PCIE,     HWID_MCATYPE(0x46, 0x0), 0x1F },
 178 };
 179
 180 struct smca_bank smca_banks[MAX_NR_BANKS];
 181 EXPORT_SYMBOL_GPL(smca_banks);
 182
 183 /*
 184  * In SMCA enabled processors, we can have multiple banks for a given IP type.
 185  * So to define a unique name for each bank, we use a temp c-string to append
 186  * the MCA_IPID[InstanceId] to type's name in get_name().
 187  *
 188  * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
 189  * is greater than 8 plus 1 (for underscore) plus length of longest type name.
 190  */
 191 #define MAX_MCATYPE_NAME_LEN    30
 192 static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
 193
 194 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
 195 static DEFINE_PER_CPU(unsigned int, bank_map);  /* see which banks are on */
 196
 197 /* Map of banks that have more than MCA_MISC0 available. */
 198 static DEFINE_PER_CPU(u32, smca_misc_banks_map);
 199
 200 static void amd_threshold_interrupt(void);
 201 static void amd_deferred_error_interrupt(void);
 202
 203 static void default_deferred_error_interrupt(void)
 204 {
 205         pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
 206 }
 207 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
 208
 209 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu)
 210 {
 211         u32 low, high;
 212
 213         /*
 214          * For SMCA enabled processors, BLKPTR field of the first MISC register
 215          * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4).
 216          */
 217         if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
 218                 return;
 219
 220         if (!(low & MCI_CONFIG_MCAX))
 221                 return;
 222
 223         if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high))
 224                 return;
 225
 226         if (low & MASK_BLKPTR_LO)
 227                 per_cpu(smca_misc_banks_map, cpu) |= BIT(bank);
 228
 229 }
 230
 231 static void smca_configure(unsigned int bank, unsigned int cpu)
 232 {
 233         unsigned int i, hwid_mcatype;
 234         struct smca_hwid *s_hwid;
 235         u32 high, low;
 236         u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
 237
 238         /* Set appropriate bits in MCA_CONFIG */
 239         if (!rdmsr_safe(smca_config, &low, &high)) {
 240                 /*
 241                  * OS is required to set the MCAX bit to acknowledge that it is
 242                  * now using the new MSR ranges and new registers under each
 243                  * bank. It also means that the OS will configure deferred
 244                  * errors in the new MCx_CONFIG register. If the bit is not set,
 245                  * uncorrectable errors will cause a system panic.
 246                  *
 247                  * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
 248                  */
 249                 high |= BIT(0);
 250
 251                 /*
 252                  * SMCA sets the Deferred Error Interrupt type per bank.
 253                  *
 254                  * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
 255                  * if the DeferredIntType bit field is available.
 256                  *
 257                  * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
 258                  * high portion of the MSR). OS should set this to 0x1 to enable
 259                  * APIC based interrupt. First, check that no interrupt has been
 260                  * set.
 261                  */
 262                 if ((low & BIT(5)) && !((high >> 5) & 0x3))
 263                         high |= BIT(5);
 264
 265                 wrmsr(smca_config, low, high);
 266         }
 267
 268         smca_set_misc_banks_map(bank, cpu);
 269
 270         /* Return early if this bank was already initialized. */
 271         if (smca_banks[bank].hwid && smca_banks[bank].hwid->hwid_mcatype != 0)
 272                 return;
 273
 274         if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
 275                 pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
 276                 return;
 277         }
 278
 279         hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
 280                                     (high & MCI_IPID_MCATYPE) >> 16);
 281
 282         for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
 283                 s_hwid = &smca_hwid_mcatypes[i];
 284                 if (hwid_mcatype == s_hwid->hwid_mcatype) {
 285                         smca_banks[bank].hwid = s_hwid;
 286                         smca_banks[bank].id = low;
 287                         smca_banks[bank].sysfs_id = s_hwid->count++;
 288                         break;
 289                 }
 290         }
 291 }
 292
 293 struct thresh_restart {
 294         struct threshold_block  *b;
 295         int                     reset;
 296         int                     set_lvt_off;
 297         int                     lvt_off;
 298         u16                     old_limit;
 299 };
 300
 301 static inline bool is_shared_bank(int bank)
 302 {
 303         /*
 304          * Scalable MCA provides for only one core to have access to the MSRs of
 305          * a shared bank.
 306          */
 307         if (mce_flags.smca)
 308                 return false;
 309
 310         /* Bank 4 is for northbridge reporting and is thus shared */
 311         return (bank == 4);
 312 }
 313
 314 static const char *bank4_names(const struct threshold_block *b)
 315 {
 316         switch (b->address) {
 317         /* MSR4_MISC0 */
 318         case 0x00000413:
 319                 return "dram";
 320
 321         case 0xc0000408:
 322                 return "ht_links";
 323
 324         case 0xc0000409:
 325                 return "l3_cache";
 326
 327         default:
 328                 WARN(1, "Funny MSR: 0x%08x\n", b->address);
 329                 return "";
 330         }
 331 };
 332
 333
 334 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
 335 {
 336         /*
 337          * bank 4 supports APIC LVT interrupts implicitly since forever.
 338          */
 339         if (bank == 4)
 340                 return true;
 341
 342         /*
 343          * IntP: interrupt present; if this bit is set, the thresholding
 344          * bank can generate APIC LVT interrupts
 345          */
 346         return msr_high_bits & BIT(28);
 347 }
 348
 349 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 350 {
 351         int msr = (hi & MASK_LVTOFF_HI) >> 20;
 352
 353         if (apic < 0) {
 354                 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
 355                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
 356                        b->bank, b->block, b->address, hi, lo);
 357                 return 0;
 358         }
 359
 360         if (apic != msr) {
 361                 /*
 362                  * On SMCA CPUs, LVT offset is programmed at a different MSR, and
 363                  * the BIOS provides the value. The original field where LVT offset
 364                  * was set is reserved. Return early here:
 365                  */
 366                 if (mce_flags.smca)
 367                         return 0;
 368
 369                 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
 370                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
 371                        b->cpu, apic, b->bank, b->block, b->address, hi, lo);
 372                 return 0;
 373         }
 374
 375         return 1;
 376 };
 377
 378 /* Reprogram MCx_MISC MSR behind this threshold bank. */
 379 static void threshold_restart_bank(void *_tr)
 380 {
 381         struct thresh_restart *tr = _tr;
 382         u32 hi, lo;
 383
 384         rdmsr(tr->b->address, lo, hi);
 385
 386         if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
 387                 tr->reset = 1;  /* limit cannot be lower than err count */
 388
 389         if (tr->reset) {                /* reset err count and overflow bit */
 390                 hi =
 391                     (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
 392                     (THRESHOLD_MAX - tr->b->threshold_limit);
 393         } else if (tr->old_limit) {     /* change limit w/o reset */
 394                 int new_count = (hi & THRESHOLD_MAX) +
 395                     (tr->old_limit - tr->b->threshold_limit);
 396
 397                 hi = (hi & ~MASK_ERR_COUNT_HI) |
 398                     (new_count & THRESHOLD_MAX);
 399         }
 400
 401         /* clear IntType */
 402         hi &= ~MASK_INT_TYPE_HI;
 403
 404         if (!tr->b->interrupt_capable)
 405                 goto done;
 406
 407         if (tr->set_lvt_off) {
 408                 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
 409                         /* set new lvt offset */
 410                         hi &= ~MASK_LVTOFF_HI;
 411                         hi |= tr->lvt_off << 20;
 412                 }
 413         }
 414
 415         if (tr->b->interrupt_enable)
 416                 hi |= INT_TYPE_APIC;
 417
 418  done:
 419
 420         hi |= MASK_COUNT_EN_HI;
 421         wrmsr(tr->b->address, lo, hi);
 422 }
 423
 424 static void mce_threshold_block_init(struct threshold_block *b, int offset)
 425 {
 426         struct thresh_restart tr = {
 427                 .b                      = b,
 428                 .set_lvt_off            = 1,
 429                 .lvt_off                = offset,
 430         };
 431
 432         b->threshold_limit              = THRESHOLD_MAX;
 433         threshold_restart_bank(&tr);
 434 };
 435
 436 static int setup_APIC_mce_threshold(int reserved, int new)
 437 {
 438         if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
 439                                               APIC_EILVT_MSG_FIX, 0))
 440                 return new;
 441
 442         return reserved;
 443 }
 444
 445 static int setup_APIC_deferred_error(int reserved, int new)
 446 {
 447         if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
 448                                               APIC_EILVT_MSG_FIX, 0))
 449                 return new;
 450
 451         return reserved;
 452 }
 453
 454 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 455 {
 456         u32 low = 0, high = 0;
 457         int def_offset = -1, def_new;
 458
 459         if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
 460                 return;
 461
 462         def_new = (low & MASK_DEF_LVTOFF) >> 4;
 463         if (!(low & MASK_DEF_LVTOFF)) {
 464                 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
 465                 def_new = DEF_LVT_OFF;
 466                 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
 467         }
 468
 469         def_offset = setup_APIC_deferred_error(def_offset, def_new);
 470         if ((def_offset == def_new) &&
 471             (deferred_error_int_vector != amd_deferred_error_interrupt))
 472                 deferred_error_int_vector = amd_deferred_error_interrupt;
 473
 474         if (!mce_flags.smca)
 475                 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
 476
 477         wrmsr(MSR_CU_DEF_ERR, low, high);
 478 }
 479
 480 static u32 smca_get_block_address(unsigned int bank, unsigned int block,
 481                                   unsigned int cpu)
 482 {
 483         if (!block)
 484                 return MSR_AMD64_SMCA_MCx_MISC(bank);
 485
 486         if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank)))
 487                 return 0;
 488
 489         return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
 490 }
 491
 492 static u32 get_block_address(u32 current_addr, u32 low, u32 high,
 493                              unsigned int bank, unsigned int block,
 494                              unsigned int cpu)
 495 {
 496         u32 addr = 0, offset = 0;
 497
 498         if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))
 499                 return addr;
 500
 501         if (mce_flags.smca)
 502                 return smca_get_block_address(bank, block, cpu);
 503
 504         /* Fall back to method we used for older processors: */
 505         switch (block) {
 506         case 0:
 507                 addr = msr_ops.misc(bank);
 508                 break;
 509         case 1:
 510                 offset = ((low & MASK_BLKPTR_LO) >> 21);
 511                 if (offset)
 512                         addr = MCG_XBLK_ADDR + offset;
 513                 break;
 514         default:
 515                 addr = ++current_addr;
 516         }
 517         return addr;
 518 }
 519
 520 static int
 521 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 522                         int offset, u32 misc_high)
 523 {
 524         unsigned int cpu = smp_processor_id();
 525         u32 smca_low, smca_high;
 526         struct threshold_block b;
 527         int new;
 528
 529         if (!block)
 530                 per_cpu(bank_map, cpu) |= (1 << bank);
 531
 532         memset(&b, 0, sizeof(b));
 533         b.cpu                   = cpu;
 534         b.bank                  = bank;
 535         b.block                 = block;
 536         b.address               = addr;
 537         b.interrupt_capable     = lvt_interrupt_supported(bank, misc_high);
 538
 539         if (!b.interrupt_capable)
 540                 goto done;
 541
 542         b.interrupt_enable = 1;
 543
 544         if (!mce_flags.smca) {
 545                 new = (misc_high & MASK_LVTOFF_HI) >> 20;
 546                 goto set_offset;
 547         }
 548
 549         /* Gather LVT offset for thresholding: */
 550         if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
 551                 goto out;
 552
 553         new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
 554
 555 set_offset:
 556         offset = setup_APIC_mce_threshold(offset, new);
 557         if (offset == new)
 558                 thresholding_irq_en = true;
 559
 560 done:
 561         mce_threshold_block_init(&b, offset);
 562
 563 out:
 564         return offset;
 565 }
 566
 567 bool amd_filter_mce(struct mce *m)
 568 {
 569         enum smca_bank_types bank_type = smca_get_bank_type(m->bank);
 570         struct cpuinfo_x86 *c = &boot_cpu_data;
 571         u8 xec = (m->status >> 16) & 0x3F;
 572
 573         /* See Family 17h Models 10h-2Fh Erratum #1114. */
 574         if (c->x86 == 0x17 &&
 575             c->x86_model >= 0x10 && c->x86_model <= 0x2F &&
 576             bank_type == SMCA_IF && xec == 10)
 577                 return true;
 578
 579         return false;
 580 }
 581
 582 /*
 583  * Turn off thresholding banks for the following conditions:
 584  * - MC4_MISC thresholding is not supported on Family 0x15.
 585  * - Prevent possible spurious interrupts from the IF bank on Family 0x17
 586  *   Models 0x10-0x2F due to Erratum #1114.
 587  */
 588 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
 589 {
 590         int i, num_msrs;
 591         u64 hwcr;
 592         bool need_toggle;
 593         u32 msrs[NR_BLOCKS];
 594
 595         if (c->x86 == 0x15 && bank == 4) {
 596                 msrs[0] = 0x00000413; /* MC4_MISC0 */
 597                 msrs[1] = 0xc0000408; /* MC4_MISC1 */
 598                 num_msrs = 2;
 599         } else if (c->x86 == 0x17 &&
 600                    (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) {
 601
 602                 if (smca_get_bank_type(bank) != SMCA_IF)
 603                         return;
 604
 605                 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);
 606                 num_msrs = 1;
 607         } else {
 608                 return;
 609         }
 610
 611         rdmsrl(MSR_K7_HWCR, hwcr);
 612
 613         /* McStatusWrEn has to be set */
 614         need_toggle = !(hwcr & BIT(18));
 615         if (need_toggle)
 616                 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
 617
 618         /* Clear CntP bit safely */
 619         for (i = 0; i < num_msrs; i++)
 620                 msr_clear_bit(msrs[i], 62);
 621
 622         /* restore old settings */
 623         if (need_toggle)
 624                 wrmsrl(MSR_K7_HWCR, hwcr);
 625 }
 626
 627 /* cpu init entry point, called from mce.c with preempt off */
 628 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 629 {
 630         unsigned int bank, block, cpu = smp_processor_id();
 631         u32 low = 0, high = 0, address = 0;
 632         int offset = -1;
 633
 634
 635         for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
 636                 if (mce_flags.smca)
 637                         smca_configure(bank, cpu);
 638
 639                 disable_err_thresholding(c, bank);
 640
 641                 for (block = 0; block < NR_BLOCKS; ++block) {
 642                         address = get_block_address(address, low, high, bank, block, cpu);
 643                         if (!address)
 644                                 break;
 645
 646                         if (rdmsr_safe(address, &low, &high))
 647                                 break;
 648
 649                         if (!(high & MASK_VALID_HI))
 650                                 continue;
 651
 652                         if (!(high & MASK_CNTP_HI)  ||
 653                              (high & MASK_LOCKED_HI))
 654                                 continue;
 655
 656                         offset = prepare_threshold_block(bank, block, address, offset, high);
 657                 }
 658         }
 659
 660         if (mce_flags.succor)
 661                 deferred_error_interrupt_enable(c);
 662 }
 663
 664 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
 665 {
 666         u64 dram_base_addr, dram_limit_addr, dram_hole_base;
 667         /* We start from the normalized address */
 668         u64 ret_addr = norm_addr;
 669
 670         u32 tmp;
 671
 672         u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
 673         u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
 674         u8 intlv_addr_sel, intlv_addr_bit;
 675         u8 num_intlv_bits, hashed_bit;
 676         u8 lgcy_mmio_hole_en, base = 0;
 677         u8 cs_mask, cs_id = 0;
 678         bool hash_enabled = false;
 679
 680         /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
 681         if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
 682                 goto out_err;
 683
 684         /* Remove HiAddrOffset from normalized address, if enabled: */
 685         if (tmp & BIT(0)) {
 686                 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
 687
 688                 if (norm_addr >= hi_addr_offset) {
 689                         ret_addr -= hi_addr_offset;
 690                         base = 1;
 691                 }
 692         }
 693
 694         /* Read D18F0x110 (DramBaseAddress). */
 695         if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp))
 696                 goto out_err;
 697
 698         /* Check if address range is valid. */
 699         if (!(tmp & BIT(0))) {
 700                 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
 701                         __func__, tmp);
 702                 goto out_err;
 703         }
 704
 705         lgcy_mmio_hole_en = tmp & BIT(1);
 706         intlv_num_chan    = (tmp >> 4) & 0xF;
 707         intlv_addr_sel    = (tmp >> 8) & 0x7;
 708         dram_base_addr    = (tmp & GENMASK_ULL(31, 12)) << 16;
 709
 710         /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
 711         if (intlv_addr_sel > 3) {
 712                 pr_err("%s: Invalid interleave address select %d.\n",
 713                         __func__, intlv_addr_sel);
 714                 goto out_err;
 715         }
 716
 717         /* Read D18F0x114 (DramLimitAddress). */
 718         if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
 719                 goto out_err;
 720
 721         intlv_num_sockets = (tmp >> 8) & 0x1;
 722         intlv_num_dies    = (tmp >> 10) & 0x3;
 723         dram_limit_addr   = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
 724
 725         intlv_addr_bit = intlv_addr_sel + 8;
 726
 727         /* Re-use intlv_num_chan by setting it equal to log2(#channels) */
 728         switch (intlv_num_chan) {
 729         case 0: intlv_num_chan = 0; break;
 730         case 1: intlv_num_chan = 1; break;
 731         case 3: intlv_num_chan = 2; break;
 732         case 5: intlv_num_chan = 3; break;
 733         case 7: intlv_num_chan = 4; break;
 734
 735         case 8: intlv_num_chan = 1;
 736                 hash_enabled = true;
 737                 break;
 738         default:
 739                 pr_err("%s: Invalid number of interleaved channels %d.\n",
 740                         __func__, intlv_num_chan);
 741                 goto out_err;
 742         }
 743
 744         num_intlv_bits = intlv_num_chan;
 745
 746         if (intlv_num_dies > 2) {
 747                 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
 748                         __func__, intlv_num_dies);
 749                 goto out_err;
 750         }
 751
 752         num_intlv_bits += intlv_num_dies;
 753
 754         /* Add a bit if sockets are interleaved. */
 755         num_intlv_bits += intlv_num_sockets;
 756
 757         /* Assert num_intlv_bits <= 4 */
 758         if (num_intlv_bits > 4) {
 759                 pr_err("%s: Invalid interleave bits %d.\n",
 760                         __func__, num_intlv_bits);
 761                 goto out_err;
 762         }
 763
 764         if (num_intlv_bits > 0) {
 765                 u64 temp_addr_x, temp_addr_i, temp_addr_y;
 766                 u8 die_id_bit, sock_id_bit, cs_fabric_id;
 767
 768                 /*
 769                  * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
 770                  * This is the fabric id for this coherent slave. Use
 771                  * umc/channel# as instance id of the coherent slave
 772                  * for FICAA.
 773                  */
 774                 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
 775                         goto out_err;
 776
 777                 cs_fabric_id = (tmp >> 8) & 0xFF;
 778                 die_id_bit   = 0;
 779
 780                 /* If interleaved over more than 1 channel: */
 781                 if (intlv_num_chan) {
 782                         die_id_bit = intlv_num_chan;
 783                         cs_mask    = (1 << die_id_bit) - 1;
 784                         cs_id      = cs_fabric_id & cs_mask;
 785                 }
 786
 787                 sock_id_bit = die_id_bit;
 788
 789                 /* Read D18F1x208 (SystemFabricIdMask). */
 790                 if (intlv_num_dies || intlv_num_sockets)
 791                         if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp))
 792                                 goto out_err;
 793
 794                 /* If interleaved over more than 1 die. */
 795                 if (intlv_num_dies) {
 796                         sock_id_bit  = die_id_bit + intlv_num_dies;
 797                         die_id_shift = (tmp >> 24) & 0xF;
 798                         die_id_mask  = (tmp >> 8) & 0xFF;
 799
 800                         cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
 801                 }
 802
 803                 /* If interleaved over more than 1 socket. */
 804                 if (intlv_num_sockets) {
 805                         socket_id_shift = (tmp >> 28) & 0xF;
 806                         socket_id_mask  = (tmp >> 16) & 0xFF;
 807
 808                         cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
 809                 }
 810
 811                 /*
 812                  * The pre-interleaved address consists of XXXXXXIIIYYYYY
 813                  * where III is the ID for this CS, and XXXXXXYYYYY are the
 814                  * address bits from the post-interleaved address.
 815                  * "num_intlv_bits" has been calculated to tell us how many "I"
 816                  * bits there are. "intlv_addr_bit" tells us how many "Y" bits
 817                  * there are (where "I" starts).
 818                  */
 819                 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0);
 820                 temp_addr_i = (cs_id << intlv_addr_bit);
 821                 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
 822                 ret_addr    = temp_addr_x | temp_addr_i | temp_addr_y;
 823         }
 824
 825         /* Add dram base address */
 826         ret_addr += dram_base_addr;
 827
 828         /* If legacy MMIO hole enabled */
 829         if (lgcy_mmio_hole_en) {
 830                 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp))
 831                         goto out_err;
 832
 833                 dram_hole_base = tmp & GENMASK(31, 24);
 834                 if (ret_addr >= dram_hole_base)
 835                         ret_addr += (BIT_ULL(32) - dram_hole_base);
 836         }
 837
 838         if (hash_enabled) {
 839                 /* Save some parentheses and grab ls-bit at the end. */
 840                 hashed_bit =    (ret_addr >> 12) ^
 841                                 (ret_addr >> 18) ^
 842                                 (ret_addr >> 21) ^
 843                                 (ret_addr >> 30) ^
 844                                 cs_id;
 845
 846                 hashed_bit &= BIT(0);
 847
 848                 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0)))
 849                         ret_addr ^= BIT(intlv_addr_bit);
 850         }
 851
 852         /* Is calculated system address is above DRAM limit address? */
 853         if (ret_addr > dram_limit_addr)
 854                 goto out_err;
 855
 856         *sys_addr = ret_addr;
 857         return 0;
 858
 859 out_err:
 860         return -EINVAL;
 861 }
 862 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);
 863
 864 bool amd_mce_is_memory_error(struct mce *m)
 865 {
 866         /* ErrCodeExt[20:16] */
 867         u8 xec = (m->status >> 16) & 0x1f;
 868
 869         if (mce_flags.smca)
 870                 return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0;
 871
 872         return m->bank == 4 && xec == 0x8;
 873 }
 874
 875 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
 876 {
 877         struct mce m;
 878
 879         mce_setup(&m);
 880
 881         m.status = status;
 882         m.misc   = misc;
 883         m.bank   = bank;
 884         m.tsc    = rdtsc();
 885
 886         if (m.status & MCI_STATUS_ADDRV) {
 887                 m.addr = addr;
 888
 889                 /*
 890                  * Extract [55:<lsb>] where lsb is the least significant
 891                  * *valid* bit of the address bits.
 892                  */
 893                 if (mce_flags.smca) {
 894                         u8 lsb = (m.addr >> 56) & 0x3f;
 895
 896                         m.addr &= GENMASK_ULL(55, lsb);
 897                 }
 898         }
 899
 900         if (mce_flags.smca) {
 901                 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);
 902
 903                 if (m.status & MCI_STATUS_SYNDV)
 904                         rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);
 905         }
 906
 907         mce_log(&m);
 908 }
 909
 910 asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(struct pt_regs *regs)
 911 {
 912         entering_irq();
 913         trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
 914         inc_irq_stat(irq_deferred_error_count);
 915         deferred_error_int_vector();
 916         trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
 917         exiting_ack_irq();
 918 }
 919
 920 /*
 921  * Returns true if the logged error is deferred. False, otherwise.
 922  */
 923 static inline bool
 924 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
 925 {
 926         u64 status, addr = 0;
 927
 928         rdmsrl(msr_stat, status);
 929         if (!(status & MCI_STATUS_VAL))
 930                 return false;
 931
 932         if (status & MCI_STATUS_ADDRV)
 933                 rdmsrl(msr_addr, addr);
 934
 935         __log_error(bank, status, addr, misc);
 936
 937         wrmsrl(msr_stat, 0);
 938
 939         return status & MCI_STATUS_DEFERRED;
 940 }
 941
 942 /*
 943  * We have three scenarios for checking for Deferred errors:
 944  *
 945  * 1) Non-SMCA systems check MCA_STATUS and log error if found.
 946  * 2) SMCA systems check MCA_STATUS. If error is found then log it and also
 947  *    clear MCA_DESTAT.
 948  * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
 949  *    log it.
 950  */
 951 static void log_error_deferred(unsigned int bank)
 952 {
 953         bool defrd;
 954
 955         defrd = _log_error_bank(bank, msr_ops.status(bank),
 956                                         msr_ops.addr(bank), 0);
 957
 958         if (!mce_flags.smca)
 959                 return;
 960
 961         /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */
 962         if (defrd) {
 963                 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
 964                 return;
 965         }
 966
 967         /*
 968          * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
 969          * for a valid error.
 970          */
 971         _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),
 972                               MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);
 973 }
 974
 975 /* APIC interrupt handler for deferred errors */
 976 static void amd_deferred_error_interrupt(void)
 977 {
 978         unsigned int bank;
 979
 980         for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank)
 981                 log_error_deferred(bank);
 982 }
 983
 984 static void log_error_thresholding(unsigned int bank, u64 misc)
 985 {
 986         _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc);
 987 }
 988
 989 static void log_and_reset_block(struct threshold_block *block)
 990 {
 991         struct thresh_restart tr;
 992         u32 low = 0, high = 0;
 993
 994         if (!block)
 995                 return;
 996
 997         if (rdmsr_safe(block->address, &low, &high))
 998                 return;
 999
1000         if (!(high & MASK_OVERFLOW_HI))
1001                 return;
1002
1003         /* Log the MCE which caused the threshold event. */
1004         log_error_thresholding(block->bank, ((u64)high << 32) | low);
1005
1006         /* Reset threshold block after logging error. */
1007         memset(&tr, 0, sizeof(tr));
1008         tr.b = block;
1009         threshold_restart_bank(&tr);
1010 }
1011
1012 /*
1013  * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
1014  * goes off when error_count reaches threshold_limit.
1015  */
1016 static void amd_threshold_interrupt(void)
1017 {
1018         struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL;
1019         unsigned int bank, cpu = smp_processor_id();
1020
1021         for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
1022                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1023                         continue;
1024
1025                 first_block = per_cpu(threshold_banks, cpu)[bank]->blocks;
1026                 if (!first_block)
1027                         continue;
1028
1029                 /*
1030                  * The first block is also the head of the list. Check it first
1031                  * before iterating over the rest.
1032                  */
1033                 log_and_reset_block(first_block);
1034                 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj)
1035                         log_and_reset_block(block);
1036         }
1037 }
1038
1039 /*
1040  * Sysfs Interface
1041  */
1042
1043 struct threshold_attr {
1044         struct attribute attr;
1045         ssize_t (*show) (struct threshold_block *, char *);
1046         ssize_t (*store) (struct threshold_block *, const char *, size_t count);
1047 };
1048
1049 #define SHOW_FIELDS(name)                                               \
1050 static ssize_t show_ ## name(struct threshold_block *b, char *buf)      \
1051 {                                                                       \
1052         return sprintf(buf, "%lu\n", (unsigned long) b->name);          \
1053 }
1054 SHOW_FIELDS(interrupt_enable)
1055 SHOW_FIELDS(threshold_limit)
1056
1057 static ssize_t
1058 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
1059 {
1060         struct thresh_restart tr;
1061         unsigned long new;
1062
1063         if (!b->interrupt_capable)
1064                 return -EINVAL;
1065
1066         if (kstrtoul(buf, 0, &new) < 0)
1067                 return -EINVAL;
1068
1069         b->interrupt_enable = !!new;
1070
1071         memset(&tr, 0, sizeof(tr));
1072         tr.b            = b;
1073
1074         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
1075
1076         return size;
1077 }
1078
1079 static ssize_t
1080 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
1081 {
1082         struct thresh_restart tr;
1083         unsigned long new;
1084
1085         if (kstrtoul(buf, 0, &new) < 0)
1086                 return -EINVAL;
1087
1088         if (new > THRESHOLD_MAX)
1089                 new = THRESHOLD_MAX;
1090         if (new < 1)
1091                 new = 1;
1092
1093         memset(&tr, 0, sizeof(tr));
1094         tr.old_limit = b->threshold_limit;
1095         b->threshold_limit = new;
1096         tr.b = b;
1097
1098         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
1099
1100         return size;
1101 }
1102
1103 static ssize_t show_error_count(struct threshold_block *b, char *buf)
1104 {
1105         u32 lo, hi;
1106
1107         rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
1108
1109         return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
1110                                      (THRESHOLD_MAX - b->threshold_limit)));
1111 }
1112
1113 static struct threshold_attr error_count = {
1114         .attr = {.name = __stringify(error_count), .mode = 0444 },
1115         .show = show_error_count,
1116 };
1117
1118 #define RW_ATTR(val)                                                    \
1119 static struct threshold_attr val = {                                    \
1120         .attr   = {.name = __stringify(val), .mode = 0644 },            \
1121         .show   = show_## val,                                          \
1122         .store  = store_## val,                                         \
1123 };
1124
1125 RW_ATTR(interrupt_enable);
1126 RW_ATTR(threshold_limit);
1127
1128 static struct attribute *default_attrs[] = {
1129         &threshold_limit.attr,
1130         &error_count.attr,
1131         NULL,   /* possibly interrupt_enable if supported, see below */
1132         NULL,
1133 };
1134
1135 #define to_block(k)     container_of(k, struct threshold_block, kobj)
1136 #define to_attr(a)      container_of(a, struct threshold_attr, attr)
1137
1138 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1139 {
1140         struct threshold_block *b = to_block(kobj);
1141         struct threshold_attr *a = to_attr(attr);
1142         ssize_t ret;
1143
1144         ret = a->show ? a->show(b, buf) : -EIO;
1145
1146         return ret;
1147 }
1148
1149 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1150                      const char *buf, size_t count)
1151 {
1152         struct threshold_block *b = to_block(kobj);
1153         struct threshold_attr *a = to_attr(attr);
1154         ssize_t ret;
1155
1156         ret = a->store ? a->store(b, buf, count) : -EIO;
1157
1158         return ret;
1159 }
1160
1161 static const struct sysfs_ops threshold_ops = {
1162         .show                   = show,
1163         .store                  = store,
1164 };
1165
1166 static void threshold_block_release(struct kobject *kobj);
1167
1168 static struct kobj_type threshold_ktype = {
1169         .sysfs_ops              = &threshold_ops,
1170         .default_attrs          = default_attrs,
1171         .release                = threshold_block_release,
1172 };
1173
1174 static const char *get_name(unsigned int bank, struct threshold_block *b)
1175 {
1176         enum smca_bank_types bank_type;
1177
1178         if (!mce_flags.smca) {
1179                 if (b && bank == 4)
1180                         return bank4_names(b);
1181
1182                 return th_names[bank];
1183         }
1184
1185         bank_type = smca_get_bank_type(bank);
1186         if (bank_type >= N_SMCA_BANK_TYPES)
1187                 return NULL;
1188
1189         if (b && bank_type == SMCA_UMC) {
1190                 if (b->block < ARRAY_SIZE(smca_umc_block_names))
1191                         return smca_umc_block_names[b->block];
1192                 return NULL;
1193         }
1194
1195         if (smca_banks[bank].hwid->count == 1)
1196                 return smca_get_name(bank_type);
1197
1198         snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
1199                  "%s_%x", smca_get_name(bank_type),
1200                           smca_banks[bank].sysfs_id);
1201         return buf_mcatype;
1202 }
1203
1204 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb,
1205                                      unsigned int bank, unsigned int block,
1206                                      u32 address)
1207 {
1208         struct threshold_block *b = NULL;
1209         u32 low, high;
1210         int err;
1211
1212         if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))
1213                 return 0;
1214
1215         if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
1216                 return 0;
1217
1218         if (!(high & MASK_VALID_HI)) {
1219                 if (block)
1220                         goto recurse;
1221                 else
1222                         return 0;
1223         }
1224
1225         if (!(high & MASK_CNTP_HI)  ||
1226              (high & MASK_LOCKED_HI))
1227                 goto recurse;
1228
1229         b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
1230         if (!b)
1231                 return -ENOMEM;
1232
1233         b->block                = block;
1234         b->bank                 = bank;
1235         b->cpu                  = cpu;
1236         b->address              = address;
1237         b->interrupt_enable     = 0;
1238         b->interrupt_capable    = lvt_interrupt_supported(bank, high);
1239         b->threshold_limit      = THRESHOLD_MAX;
1240
1241         if (b->interrupt_capable) {
1242                 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
1243                 b->interrupt_enable = 1;
1244         } else {
1245                 threshold_ktype.default_attrs[2] = NULL;
1246         }
1247
1248         INIT_LIST_HEAD(&b->miscj);
1249
1250         if (tb->blocks)
1251                 list_add(&b->miscj, &tb->blocks->miscj);
1252         else
1253                 tb->blocks = b;
1254
1255         err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(bank, b));
1256         if (err)
1257                 goto out_free;
1258 recurse:
1259         address = get_block_address(address, low, high, bank, ++block, cpu);
1260         if (!address)
1261                 return 0;
1262
1263         err = allocate_threshold_blocks(cpu, tb, bank, block, address);
1264         if (err)
1265                 goto out_free;
1266
1267         if (b)
1268                 kobject_uevent(&b->kobj, KOBJ_ADD);
1269
1270         return err;
1271
1272 out_free:
1273         if (b) {
1274                 kobject_put(&b->kobj);
1275                 list_del(&b->miscj);
1276                 kfree(b);
1277         }
1278         return err;
1279 }
1280
1281 static int __threshold_add_blocks(struct threshold_bank *b)
1282 {
1283         struct list_head *head = &b->blocks->miscj;
1284         struct threshold_block *pos = NULL;
1285         struct threshold_block *tmp = NULL;
1286         int err = 0;
1287
1288         err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
1289         if (err)
1290                 return err;
1291
1292         list_for_each_entry_safe(pos, tmp, head, miscj) {
1293
1294                 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
1295                 if (err) {
1296                         list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
1297                                 kobject_del(&pos->kobj);
1298
1299                         return err;
1300                 }
1301         }
1302         return err;
1303 }
1304
1305 static int threshold_create_bank(unsigned int cpu, unsigned int bank)
1306 {
1307         struct device *dev = per_cpu(mce_device, cpu);
1308         struct amd_northbridge *nb = NULL;
1309         struct threshold_bank *b = NULL;
1310         const char *name = get_name(bank, NULL);
1311         int err = 0;
1312
1313         if (!dev)
1314                 return -ENODEV;
1315
1316         if (is_shared_bank(bank)) {
1317                 nb = node_to_amd_nb(amd_get_nb_id(cpu));
1318
1319                 /* threshold descriptor already initialized on this node? */
1320                 if (nb && nb->bank4) {
1321                         /* yes, use it */
1322                         b = nb->bank4;
1323                         err = kobject_add(b->kobj, &dev->kobj, name);
1324                         if (err)
1325                                 goto out;
1326
1327                         per_cpu(threshold_banks, cpu)[bank] = b;
1328                         refcount_inc(&b->cpus);
1329
1330                         err = __threshold_add_blocks(b);
1331
1332                         goto out;
1333                 }
1334         }
1335
1336         b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1337         if (!b) {
1338                 err = -ENOMEM;
1339                 goto out;
1340         }
1341
1342         b->kobj = kobject_create_and_add(name, &dev->kobj);
1343         if (!b->kobj) {
1344                 err = -EINVAL;
1345                 goto out_free;
1346         }
1347
1348         if (is_shared_bank(bank)) {
1349                 refcount_set(&b->cpus, 1);
1350
1351                 /* nb is already initialized, see above */
1352                 if (nb) {
1353                         WARN_ON(nb->bank4);
1354                         nb->bank4 = b;
1355                 }
1356         }
1357
1358         err = allocate_threshold_blocks(cpu, b, bank, 0, msr_ops.misc(bank));
1359         if (err)
1360                 goto out_free;
1361
1362         per_cpu(threshold_banks, cpu)[bank] = b;
1363
1364         return 0;
1365
1366  out_free:
1367         kfree(b);
1368
1369  out:
1370         return err;
1371 }
1372
1373 static void threshold_block_release(struct kobject *kobj)
1374 {
1375         kfree(to_block(kobj));
1376 }
1377
1378 static void deallocate_threshold_block(unsigned int cpu, unsigned int bank)
1379 {
1380         struct threshold_block *pos = NULL;
1381         struct threshold_block *tmp = NULL;
1382         struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
1383
1384         if (!head)
1385                 return;
1386
1387         list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
1388                 list_del(&pos->miscj);
1389                 kobject_put(&pos->kobj);
1390         }
1391
1392         kobject_put(&head->blocks->kobj);
1393 }
1394
1395 static void __threshold_remove_blocks(struct threshold_bank *b)
1396 {
1397         struct threshold_block *pos = NULL;
1398         struct threshold_block *tmp = NULL;
1399
1400         kobject_del(b->kobj);
1401
1402         list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
1403                 kobject_del(&pos->kobj);
1404 }
1405
1406 static void threshold_remove_bank(unsigned int cpu, int bank)
1407 {
1408         struct amd_northbridge *nb;
1409         struct threshold_bank *b;
1410
1411         b = per_cpu(threshold_banks, cpu)[bank];
1412         if (!b)
1413                 return;
1414
1415         if (!b->blocks)
1416                 goto free_out;
1417
1418         if (is_shared_bank(bank)) {
1419                 if (!refcount_dec_and_test(&b->cpus)) {
1420                         __threshold_remove_blocks(b);
1421                         per_cpu(threshold_banks, cpu)[bank] = NULL;
1422                         return;
1423                 } else {
1424                         /*
1425                          * the last CPU on this node using the shared bank is
1426                          * going away, remove that bank now.
1427                          */
1428                         nb = node_to_amd_nb(amd_get_nb_id(cpu));
1429                         nb->bank4 = NULL;
1430                 }
1431         }
1432
1433         deallocate_threshold_block(cpu, bank);
1434
1435 free_out:
1436         kobject_del(b->kobj);
1437         kobject_put(b->kobj);
1438         kfree(b);
1439         per_cpu(threshold_banks, cpu)[bank] = NULL;
1440 }
1441
1442 int mce_threshold_remove_device(unsigned int cpu)
1443 {
1444         unsigned int bank;
1445
1446         for (bank = 0; bank < per_cpu(mce_num_banks, cpu); ++bank) {
1447                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1448                         continue;
1449                 threshold_remove_bank(cpu, bank);
1450         }
1451         kfree(per_cpu(threshold_banks, cpu));
1452         per_cpu(threshold_banks, cpu) = NULL;
1453         return 0;
1454 }
1455
1456 /* create dir/files for all valid threshold banks */
1457 int mce_threshold_create_device(unsigned int cpu)
1458 {
1459         unsigned int bank;
1460         struct threshold_bank **bp;
1461         int err = 0;
1462
1463         bp = per_cpu(threshold_banks, cpu);
1464         if (bp)
1465                 return 0;
1466
1467         bp = kcalloc(per_cpu(mce_num_banks, cpu), sizeof(struct threshold_bank *),
1468                      GFP_KERNEL);
1469         if (!bp)
1470                 return -ENOMEM;
1471
1472         per_cpu(threshold_banks, cpu) = bp;
1473
1474         for (bank = 0; bank < per_cpu(mce_num_banks, cpu); ++bank) {
1475                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1476                         continue;
1477                 err = threshold_create_bank(cpu, bank);
1478                 if (err)
1479                         goto err;
1480         }
1481         return err;
1482 err:
1483         mce_threshold_remove_device(cpu);
1484         return err;
1485 }
1486
1487 static __init int threshold_init_device(void)
1488 {
1489         unsigned lcpu = 0;
1490
1491         /* to hit CPUs online before the notifier is up */
1492         for_each_online_cpu(lcpu) {
1493                 int err = mce_threshold_create_device(lcpu);
1494
1495                 if (err)
1496                         return err;
1497         }
1498
1499         if (thresholding_irq_en)
1500                 mce_threshold_vector = amd_threshold_interrupt;
1501
1502         return 0;
1503 }
1504 /*
1505  * there are 3 funcs which need to be _initcalled in a logic sequence:
1506  * 1. xen_late_init_mcelog
1507  * 2. mcheck_init_device
1508  * 3. threshold_init_device
1509  *
1510  * xen_late_init_mcelog must register xen_mce_chrdev_device before
1511  * native mce_chrdev_device registration if running under xen platform;
1512  *
1513  * mcheck_init_device should be inited before threshold_init_device to
1514  * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
1515  *
1516  * so we use following _initcalls
1517  * 1. device_initcall(xen_late_init_mcelog);
1518  * 2. device_initcall_sync(mcheck_init_device);
1519  * 3. late_initcall(threshold_init_device);
1520  *
1521  * when running under xen, the initcall order is 1,2,3;
1522  * on baremetal, we skip 1 and we do only 2 and 3.
1523  */
1524 late_initcall(threshold_init_device);