1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
4 #include <linux/string.h>
5 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/sched/clock.h>
9 #include <linux/thread_info.h>
10 #include <linux/init.h>
11 #include <linux/uaccess.h>
13 #include <asm/cpufeature.h>
14 #include <asm/pgtable.h>
18 #include <asm/intel-family.h>
19 #include <asm/microcode_intel.h>
20 #include <asm/hwcap2.h>
22 #include <asm/cpu_device_id.h>
23 #include <asm/cmdline.h>
26 #include <linux/topology.h>
31 #ifdef CONFIG_X86_LOCAL_APIC
32 #include <asm/mpspec.h>
36 enum split_lock_detect_state {
43 * Default to sld_off because most systems do not support split lock detection
44 * split_lock_setup() will switch this to sld_warn on systems that support
45 * split lock detect, unless there is a command line override.
47 static enum split_lock_detect_state sld_state __ro_after_init = sld_off;
48 static u64 msr_test_ctrl_cache __ro_after_init;
51 * Processors which have self-snooping capability can handle conflicting
52 * memory type across CPUs by snooping its own cache. However, there exists
53 * CPU models in which having conflicting memory types still leads to
54 * unpredictable behavior, machine check errors, or hangs. Clear this
55 * feature to prevent its use on machines with known erratas.
57 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
59 switch (c->x86_model) {
60 case INTEL_FAM6_CORE_YONAH:
61 case INTEL_FAM6_CORE2_MEROM:
62 case INTEL_FAM6_CORE2_MEROM_L:
63 case INTEL_FAM6_CORE2_PENRYN:
64 case INTEL_FAM6_CORE2_DUNNINGTON:
65 case INTEL_FAM6_NEHALEM:
66 case INTEL_FAM6_NEHALEM_G:
67 case INTEL_FAM6_NEHALEM_EP:
68 case INTEL_FAM6_NEHALEM_EX:
69 case INTEL_FAM6_WESTMERE:
70 case INTEL_FAM6_WESTMERE_EP:
71 case INTEL_FAM6_SANDYBRIDGE:
72 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
76 static bool ring3mwait_disabled __read_mostly;
78 static int __init ring3mwait_disable(char *__unused)
80 ring3mwait_disabled = true;
83 __setup("ring3mwait=disable", ring3mwait_disable);
85 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
88 * Ring 3 MONITOR/MWAIT feature cannot be detected without
89 * cpu model and family comparison.
93 switch (c->x86_model) {
94 case INTEL_FAM6_XEON_PHI_KNL:
95 case INTEL_FAM6_XEON_PHI_KNM:
101 if (ring3mwait_disabled)
104 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
105 this_cpu_or(msr_misc_features_shadow,
106 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
108 if (c == &boot_cpu_data)
109 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
113 * Early microcode releases for the Spectre v2 mitigation were broken.
114 * Information taken from;
115 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
116 * - https://kb.vmware.com/s/article/52345
117 * - Microcode revisions observed in the wild
118 * - Release note from 20180108 microcode release
120 struct sku_microcode {
125 static const struct sku_microcode spectre_bad_microcodes[] = {
126 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
127 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
128 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
129 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
130 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
131 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
132 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
133 { INTEL_FAM6_BROADWELL, 0x04, 0x28 },
134 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
135 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
136 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
137 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
138 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
139 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
140 { INTEL_FAM6_HASWELL, 0x03, 0x23 },
141 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
142 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
143 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
144 /* Observed in the wild */
145 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
146 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
149 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
154 * We know that the hypervisor lie to us on the microcode version so
155 * we may as well hope that it is running the correct version.
157 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
163 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
164 if (c->x86_model == spectre_bad_microcodes[i].model &&
165 c->x86_stepping == spectre_bad_microcodes[i].stepping)
166 return (c->microcode <= spectre_bad_microcodes[i].microcode);
171 static void early_init_intel(struct cpuinfo_x86 *c)
175 /* Unmask CPUID levels if masked: */
176 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
177 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
178 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
179 c->cpuid_level = cpuid_eax(0);
184 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
185 (c->x86 == 0x6 && c->x86_model >= 0x0e))
186 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
188 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
189 c->microcode = intel_get_microcode_revision();
191 /* Now if any of them are set, check the blacklist and clear the lot */
192 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
193 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
194 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
195 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
196 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
197 setup_clear_cpu_cap(X86_FEATURE_IBRS);
198 setup_clear_cpu_cap(X86_FEATURE_IBPB);
199 setup_clear_cpu_cap(X86_FEATURE_STIBP);
200 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
201 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
202 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
203 setup_clear_cpu_cap(X86_FEATURE_SSBD);
204 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
208 * Atom erratum AAE44/AAF40/AAG38/AAH41:
210 * A race condition between speculative fetches and invalidating
211 * a large page. This is worked around in microcode, but we
212 * need the microcode to have already been loaded... so if it is
213 * not, recommend a BIOS update and disable large pages.
215 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
216 c->microcode < 0x20e) {
217 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
218 clear_cpu_cap(c, X86_FEATURE_PSE);
222 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
224 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
225 if (c->x86 == 15 && c->x86_cache_alignment == 64)
226 c->x86_cache_alignment = 128;
229 /* CPUID workaround for 0F33/0F34 CPU */
230 if (c->x86 == 0xF && c->x86_model == 0x3
231 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
232 c->x86_phys_bits = 36;
235 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
236 * with P/T states and does not stop in deep C-states.
238 * It is also reliable across cores and sockets. (but not across
239 * cabinets - we turn it off in that case explicitly.)
241 if (c->x86_power & (1 << 8)) {
242 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
243 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
246 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
248 switch (c->x86_model) {
249 case INTEL_FAM6_ATOM_SALTWELL_MID:
250 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
251 case INTEL_FAM6_ATOM_SILVERMONT_MID:
252 case INTEL_FAM6_ATOM_AIRMONT_NP:
253 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
261 * There is a known erratum on Pentium III and Core Solo
263 * " Page with PAT set to WC while associated MTRR is UC
264 * may consolidate to UC "
265 * Because of this erratum, it is better to stick with
266 * setting WC in MTRR rather than using PAT on these CPUs.
268 * Enable PAT WC only on P4, Core 2 or later CPUs.
270 if (c->x86 == 6 && c->x86_model < 15)
271 clear_cpu_cap(c, X86_FEATURE_PAT);
274 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
275 * clear the fast string and enhanced fast string CPU capabilities.
277 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
278 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
279 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
280 pr_info("Disabled fast string operations\n");
281 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
282 setup_clear_cpu_cap(X86_FEATURE_ERMS);
287 * Intel Quark Core DevMan_001.pdf section 6.4.11
288 * "The operating system also is required to invalidate (i.e., flush)
289 * the TLB when any changes are made to any of the page table entries.
290 * The operating system must reload CR3 to cause the TLB to be flushed"
292 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
293 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
296 if (c->x86 == 5 && c->x86_model == 9) {
297 pr_info("Disabling PGE capability bit\n");
298 setup_clear_cpu_cap(X86_FEATURE_PGE);
301 if (c->cpuid_level >= 0x00000001) {
302 u32 eax, ebx, ecx, edx;
304 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
306 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
307 * apicids which are reserved per package. Store the resulting
308 * shift value for the package management code.
310 if (edx & (1U << 28))
311 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
314 check_memory_type_self_snoop_errata(c);
317 * Get the number of SMT siblings early from the extended topology
318 * leaf, if available. Otherwise try the legacy SMT detection.
320 if (detect_extended_topology_early(c) < 0)
326 * Early probe support logic for ppro memory erratum #50
328 * This is called before we do cpu ident work
331 int ppro_with_ram_bug(void)
333 /* Uses data from early_cpu_detect now */
334 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
335 boot_cpu_data.x86 == 6 &&
336 boot_cpu_data.x86_model == 1 &&
337 boot_cpu_data.x86_stepping < 8) {
338 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
344 static void intel_smp_check(struct cpuinfo_x86 *c)
346 /* calling is from identify_secondary_cpu() ? */
351 * Mask B, Pentium, but not Pentium MMX
354 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
357 * Remember we have B step Pentia with bugs
359 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
360 "with B stepping processors.\n");
365 static int __init forcepae_setup(char *__unused)
370 __setup("forcepae", forcepae_setup);
372 static void intel_workarounds(struct cpuinfo_x86 *c)
374 #ifdef CONFIG_X86_F00F_BUG
376 * All models of Pentium and Pentium with MMX technology CPUs
377 * have the F0 0F bug, which lets nonprivileged users lock up the
378 * system. Announce that the fault handler will be checking for it.
379 * The Quark is also family 5, but does not have the same bug.
381 clear_cpu_bug(c, X86_BUG_F00F);
382 if (c->x86 == 5 && c->x86_model < 9) {
383 static int f00f_workaround_enabled;
385 set_cpu_bug(c, X86_BUG_F00F);
386 if (!f00f_workaround_enabled) {
387 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
388 f00f_workaround_enabled = 1;
394 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
397 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
398 clear_cpu_cap(c, X86_FEATURE_SEP);
401 * PAE CPUID issue: many Pentium M report no PAE but may have a
402 * functionally usable PAE implementation.
403 * Forcefully enable PAE if kernel parameter "forcepae" is present.
406 pr_warn("PAE forced!\n");
407 set_cpu_cap(c, X86_FEATURE_PAE);
408 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
412 * P4 Xeon erratum 037 workaround.
413 * Hardware prefetcher may cause stale data to be loaded into the cache.
415 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
416 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
417 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
418 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
419 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
424 * See if we have a good local APIC by checking for buggy Pentia,
425 * i.e. all B steppings and the C2 stepping of P54C when using their
426 * integrated APIC (see 11AP erratum in "Pentium Processor
427 * Specification Update").
429 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
430 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
431 set_cpu_bug(c, X86_BUG_11AP);
434 #ifdef CONFIG_X86_INTEL_USERCOPY
436 * Set up the preferred alignment for movsl bulk memory moves
439 case 4: /* 486: untested */
441 case 5: /* Old Pentia: untested */
443 case 6: /* PII/PIII only like movsl with 8-byte alignment */
446 case 15: /* P4 is OK down to 8-byte alignment */
455 static void intel_workarounds(struct cpuinfo_x86 *c)
460 static void srat_detect_node(struct cpuinfo_x86 *c)
464 int cpu = smp_processor_id();
466 /* Don't do the funky fallback heuristics the AMD version employs
468 node = numa_cpu_node(cpu);
469 if (node == NUMA_NO_NODE || !node_online(node)) {
470 /* reuse the value from init_cpu_to_node() */
471 node = cpu_to_node(cpu);
473 numa_set_node(cpu, node);
477 #define MSR_IA32_TME_ACTIVATE 0x982
479 /* Helpers to access TME_ACTIVATE MSR */
480 #define TME_ACTIVATE_LOCKED(x) (x & 0x1)
481 #define TME_ACTIVATE_ENABLED(x) (x & 0x2)
483 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
484 #define TME_ACTIVATE_POLICY_AES_XTS_128 0
486 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
488 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
489 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
491 /* Values for mktme_status (SW only construct) */
492 #define MKTME_ENABLED 0
493 #define MKTME_DISABLED 1
494 #define MKTME_UNINITIALIZED 2
495 static int mktme_status = MKTME_UNINITIALIZED;
497 static void detect_tme(struct cpuinfo_x86 *c)
499 u64 tme_activate, tme_policy, tme_crypto_algs;
500 int keyid_bits = 0, nr_keyids = 0;
501 static u64 tme_activate_cpu0 = 0;
503 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
505 if (mktme_status != MKTME_UNINITIALIZED) {
506 if (tme_activate != tme_activate_cpu0) {
508 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
509 pr_err_once("x86/tme: MKTME is not usable\n");
510 mktme_status = MKTME_DISABLED;
512 /* Proceed. We may need to exclude bits from x86_phys_bits. */
515 tme_activate_cpu0 = tme_activate;
518 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
519 pr_info_once("x86/tme: not enabled by BIOS\n");
520 mktme_status = MKTME_DISABLED;
524 if (mktme_status != MKTME_UNINITIALIZED)
525 goto detect_keyid_bits;
527 pr_info("x86/tme: enabled by BIOS\n");
529 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
530 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
531 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
533 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
534 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
535 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
537 mktme_status = MKTME_DISABLED;
540 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
541 nr_keyids = (1UL << keyid_bits) - 1;
543 pr_info_once("x86/mktme: enabled by BIOS\n");
544 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
546 pr_info_once("x86/mktme: disabled by BIOS\n");
549 if (mktme_status == MKTME_UNINITIALIZED) {
550 /* MKTME is usable */
551 mktme_status = MKTME_ENABLED;
555 * KeyID bits effectively lower the number of physical address
556 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
558 c->x86_phys_bits -= keyid_bits;
561 static void init_cpuid_fault(struct cpuinfo_x86 *c)
565 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
566 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
567 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
571 static void init_intel_misc_features(struct cpuinfo_x86 *c)
575 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
578 /* Clear all MISC features */
579 this_cpu_write(msr_misc_features_shadow, 0);
581 /* Check features and update capabilities and shadow control bits */
583 probe_xeon_phi_r3mwait(c);
585 msr = this_cpu_read(msr_misc_features_shadow);
586 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
589 static void split_lock_init(void);
591 static void init_intel(struct cpuinfo_x86 *c)
595 intel_workarounds(c);
598 * Detect the extended topology information if available. This
599 * will reinitialise the initial_apicid which will be used
600 * in init_intel_cacheinfo()
602 detect_extended_topology(c);
604 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
606 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
609 detect_num_cpu_cores(c);
615 init_intel_cacheinfo(c);
617 if (c->cpuid_level > 9) {
618 unsigned eax = cpuid_eax(10);
619 /* Check for version and the number of counters */
620 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
621 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
624 if (cpu_has(c, X86_FEATURE_XMM2))
625 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
627 if (boot_cpu_has(X86_FEATURE_DS)) {
630 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
632 set_cpu_cap(c, X86_FEATURE_BTS);
634 set_cpu_cap(c, X86_FEATURE_PEBS);
637 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
638 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
639 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
641 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
642 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
643 set_cpu_bug(c, X86_BUG_MONITOR);
647 c->x86_cache_alignment = c->x86_clflush_size * 2;
649 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
652 * Names for the Pentium II/Celeron processors
653 * detectable only by also checking the cache size.
654 * Dixon is NOT a Celeron.
657 unsigned int l2 = c->x86_cache_size;
660 switch (c->x86_model) {
663 p = "Celeron (Covington)";
665 p = "Mobile Pentium II (Dixon)";
670 p = "Celeron (Mendocino)";
671 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
677 p = "Celeron (Coppermine)";
682 strcpy(c->x86_model_id, p);
686 set_cpu_cap(c, X86_FEATURE_P4);
688 set_cpu_cap(c, X86_FEATURE_P3);
691 /* Work around errata */
694 init_ia32_feat_ctl(c);
696 if (cpu_has(c, X86_FEATURE_TME))
699 init_intel_misc_features(c);
701 if (tsx_ctrl_state == TSX_CTRL_ENABLE)
703 if (tsx_ctrl_state == TSX_CTRL_DISABLE)
710 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
713 * Intel PIII Tualatin. This comes in two flavours.
714 * One has 256kb of cache, the other 512. We have no way
715 * to determine which, so we use a boottime override
716 * for the 512kb model, and assume 256 otherwise.
718 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
722 * Intel Quark SoC X1000 contains a 4-way set associative
723 * 16K cache with a 16 byte cache line and 256 lines per tag
725 if ((c->x86 == 5) && (c->x86_model == 9))
731 #define TLB_INST_4K 0x01
732 #define TLB_INST_4M 0x02
733 #define TLB_INST_2M_4M 0x03
735 #define TLB_INST_ALL 0x05
736 #define TLB_INST_1G 0x06
738 #define TLB_DATA_4K 0x11
739 #define TLB_DATA_4M 0x12
740 #define TLB_DATA_2M_4M 0x13
741 #define TLB_DATA_4K_4M 0x14
743 #define TLB_DATA_1G 0x16
745 #define TLB_DATA0_4K 0x21
746 #define TLB_DATA0_4M 0x22
747 #define TLB_DATA0_2M_4M 0x23
750 #define STLB_4K_2M 0x42
752 static const struct _tlb_table intel_tlb_table[] = {
753 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
754 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
755 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
756 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
757 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
758 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
759 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
760 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
761 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
762 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
763 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
764 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
765 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
766 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
767 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
768 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
769 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
770 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
771 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
772 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
773 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
774 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
775 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
776 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
777 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
778 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
779 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
780 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
781 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
782 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
783 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
784 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
785 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
786 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
787 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
788 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
792 static void intel_tlb_lookup(const unsigned char desc)
798 /* look up this descriptor in the table */
799 for (k = 0; intel_tlb_table[k].descriptor != desc &&
800 intel_tlb_table[k].descriptor != 0; k++)
803 if (intel_tlb_table[k].tlb_type == 0)
806 switch (intel_tlb_table[k].tlb_type) {
808 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
809 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
810 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
811 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
814 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
815 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
816 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
817 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
818 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
819 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
820 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
821 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
822 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
823 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
824 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
825 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
828 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
829 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
830 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
831 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
832 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
833 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
836 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
837 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
840 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
841 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
844 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
845 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
846 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
847 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
851 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
852 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
856 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
857 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
860 case TLB_DATA0_2M_4M:
861 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
862 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
863 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
864 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
867 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
868 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
869 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
870 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
873 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
874 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
879 static void intel_detect_tlb(struct cpuinfo_x86 *c)
882 unsigned int regs[4];
883 unsigned char *desc = (unsigned char *)regs;
885 if (c->cpuid_level < 2)
888 /* Number of times to iterate */
889 n = cpuid_eax(2) & 0xFF;
891 for (i = 0 ; i < n ; i++) {
892 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
894 /* If bit 31 is set, this is an unknown format */
895 for (j = 0 ; j < 3 ; j++)
896 if (regs[j] & (1 << 31))
899 /* Byte 0 is level count, not a descriptor */
900 for (j = 1 ; j < 16 ; j++)
901 intel_tlb_lookup(desc[j]);
905 static const struct cpu_dev intel_cpu_dev = {
907 .c_ident = { "GenuineIntel" },
910 { .family = 4, .model_names =
912 [0] = "486 DX-25/33",
923 { .family = 5, .model_names =
925 [0] = "Pentium 60/66 A-step",
926 [1] = "Pentium 60/66",
927 [2] = "Pentium 75 - 200",
928 [3] = "OverDrive PODP5V83",
930 [7] = "Mobile Pentium 75 - 200",
931 [8] = "Mobile Pentium MMX",
932 [9] = "Quark SoC X1000",
935 { .family = 6, .model_names =
937 [0] = "Pentium Pro A-step",
939 [3] = "Pentium II (Klamath)",
940 [4] = "Pentium II (Deschutes)",
941 [5] = "Pentium II (Deschutes)",
942 [6] = "Mobile Pentium II",
943 [7] = "Pentium III (Katmai)",
944 [8] = "Pentium III (Coppermine)",
945 [10] = "Pentium III (Cascades)",
946 [11] = "Pentium III (Tualatin)",
949 { .family = 15, .model_names =
951 [0] = "Pentium 4 (Unknown)",
952 [1] = "Pentium 4 (Willamette)",
953 [2] = "Pentium 4 (Northwood)",
954 [4] = "Pentium 4 (Foster)",
955 [5] = "Pentium 4 (Foster)",
959 .legacy_cache_size = intel_size_cache,
961 .c_detect_tlb = intel_detect_tlb,
962 .c_early_init = early_init_intel,
963 .c_init = init_intel,
964 .c_x86_vendor = X86_VENDOR_INTEL,
967 cpu_dev_register(intel_cpu_dev);
970 #define pr_fmt(fmt) "x86/split lock detection: " fmt
972 static const struct {
974 enum split_lock_detect_state state;
975 } sld_options[] __initconst = {
977 { "warn", sld_warn },
978 { "fatal", sld_fatal },
981 static inline bool match_option(const char *arg, int arglen, const char *opt)
983 int len = strlen(opt);
985 return len == arglen && !strncmp(arg, opt, len);
988 static bool split_lock_verify_msr(bool on)
992 if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl))
995 ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
997 ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
998 if (wrmsrl_safe(MSR_TEST_CTRL, ctrl))
1000 rdmsrl(MSR_TEST_CTRL, tmp);
1004 static void __init split_lock_setup(void)
1006 enum split_lock_detect_state state = sld_warn;
1010 if (!split_lock_verify_msr(false)) {
1011 pr_info("MSR access failed: Disabled\n");
1015 ret = cmdline_find_option(boot_command_line, "split_lock_detect",
1018 for (i = 0; i < ARRAY_SIZE(sld_options); i++) {
1019 if (match_option(arg, ret, sld_options[i].option)) {
1020 state = sld_options[i].state;
1028 pr_info("disabled\n");
1031 pr_info("warning about user-space split_locks\n");
1034 pr_info("sending SIGBUS on user-space split_locks\n");
1038 rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1040 if (!split_lock_verify_msr(true)) {
1041 pr_info("MSR access failed: Disabled\n");
1046 setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
1050 * MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking
1051 * is not implemented as one thread could undo the setting of the other
1052 * thread immediately after dropping the lock anyway.
1054 static void sld_update_msr(bool on)
1056 u64 test_ctrl_val = msr_test_ctrl_cache;
1059 test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1061 wrmsrl(MSR_TEST_CTRL, test_ctrl_val);
1064 static void split_lock_init(void)
1066 split_lock_verify_msr(sld_state != sld_off);
1069 bool handle_user_split_lock(struct pt_regs *regs, long error_code)
1071 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)
1074 pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n",
1075 current->comm, current->pid, regs->ip);
1078 * Disable the split lock detection for this task so it can make
1079 * progress and set TIF_SLD so the detection is re-enabled via
1080 * switch_to_sld() when the task is scheduled out.
1082 sld_update_msr(false);
1083 set_tsk_thread_flag(current, TIF_SLD);
1088 * This function is called only when switching between tasks with
1089 * different split-lock detection modes. It sets the MSR for the
1090 * mode of the new task. This is right most of the time, but since
1091 * the MSR is shared by hyperthreads on a physical core there can
1092 * be glitches when the two threads need different modes.
1094 void switch_to_sld(unsigned long tifn)
1096 sld_update_msr(!(tifn & _TIF_SLD));
1099 #define SPLIT_LOCK_CPU(model) {X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY}
1102 * The following processors have the split lock detection feature. But
1103 * since they don't have the IA32_CORE_CAPABILITIES MSR, the feature cannot
1104 * be enumerated. Enable it by family and model matching on these
1107 static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
1108 SPLIT_LOCK_CPU(INTEL_FAM6_ICELAKE_X),
1109 SPLIT_LOCK_CPU(INTEL_FAM6_ICELAKE_L),
1113 void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c)
1115 u64 ia32_core_caps = 0;
1117 if (c->x86_vendor != X86_VENDOR_INTEL)
1119 if (cpu_has(c, X86_FEATURE_CORE_CAPABILITIES)) {
1120 /* Enumerate features reported in IA32_CORE_CAPABILITIES MSR. */
1121 rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);
1122 } else if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1123 /* Enumerate split lock detection by family and model. */
1124 if (x86_match_cpu(split_lock_cpu_ids))
1125 ia32_core_caps |= MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT;
1128 if (ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT)