1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/smp.h>
23 #include <linux/syscore_ops.h>
25 #include <asm/stackprotector.h>
26 #include <asm/perf_event.h>
27 #include <asm/mmu_context.h>
28 #include <asm/doublefault.h>
29 #include <asm/archrandom.h>
30 #include <asm/hypervisor.h>
31 #include <asm/processor.h>
32 #include <asm/tlbflush.h>
33 #include <asm/debugreg.h>
34 #include <asm/sections.h>
35 #include <asm/vsyscall.h>
36 #include <linux/topology.h>
37 #include <linux/cpumask.h>
38 #include <asm/pgtable.h>
39 #include <linux/atomic.h>
40 #include <asm/proto.h>
41 #include <asm/setup.h>
44 #include <asm/fpu/internal.h>
46 #include <asm/hwcap2.h>
47 #include <linux/numa.h>
53 #include <asm/memtype.h>
54 #include <asm/microcode.h>
55 #include <asm/microcode_intel.h>
56 #include <asm/intel-family.h>
57 #include <asm/cpu_device_id.h>
58 #include <asm/uv/uv.h>
62 u32 elf_hwcap2 __read_mostly;
64 /* all of these masks are initialized in setup_cpu_local_masks() */
65 cpumask_var_t cpu_initialized_mask;
66 cpumask_var_t cpu_callout_mask;
67 cpumask_var_t cpu_callin_mask;
69 /* representing cpus for which sibling maps can be computed */
70 cpumask_var_t cpu_sibling_setup_mask;
72 /* Number of siblings per CPU package */
73 int smp_num_siblings = 1;
74 EXPORT_SYMBOL(smp_num_siblings);
76 /* Last level cache ID of each logical CPU */
77 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
79 /* correctly size the local cpu masks */
80 void __init setup_cpu_local_masks(void)
82 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
83 alloc_bootmem_cpumask_var(&cpu_callin_mask);
84 alloc_bootmem_cpumask_var(&cpu_callout_mask);
85 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
88 static void default_init(struct cpuinfo_x86 *c)
91 cpu_detect_cache_sizes(c);
93 /* Not much we can do here... */
94 /* Check if at least it has cpuid */
95 if (c->cpuid_level == -1) {
96 /* No cpuid. It must be an ancient CPU */
98 strcpy(c->x86_model_id, "486");
100 strcpy(c->x86_model_id, "386");
105 static const struct cpu_dev default_cpu = {
106 .c_init = default_init,
107 .c_vendor = "Unknown",
108 .c_x86_vendor = X86_VENDOR_UNKNOWN,
111 static const struct cpu_dev *this_cpu = &default_cpu;
113 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
116 * We need valid kernel segments for data and code in long mode too
117 * IRET will check the segment types kkeil 2000/10/28
118 * Also sysret mandates a special GDT layout
120 * TLS descriptors are currently at a different place compared to i386.
121 * Hopefully nobody expects them at a fixed place (Wine?)
123 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
124 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
125 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
126 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
127 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
130 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
131 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
132 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
133 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
135 * Segments used for calling PnP BIOS have byte granularity.
136 * They code segments and data segments have fixed 64k limits,
137 * the transfer segment sizes are set at run time.
140 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
142 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
144 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
146 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
148 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
150 * The APM segments have byte granularity and their bases
151 * are set at run time. All have 64k limits.
154 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
156 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
158 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
160 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
161 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
162 GDT_STACK_CANARY_INIT
165 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
168 static int __init x86_nopcid_setup(char *s)
170 /* nopcid doesn't accept parameters */
174 /* do not emit a message if the feature is not present */
175 if (!boot_cpu_has(X86_FEATURE_PCID))
178 setup_clear_cpu_cap(X86_FEATURE_PCID);
179 pr_info("nopcid: PCID feature disabled\n");
182 early_param("nopcid", x86_nopcid_setup);
185 static int __init x86_noinvpcid_setup(char *s)
187 /* noinvpcid doesn't accept parameters */
191 /* do not emit a message if the feature is not present */
192 if (!boot_cpu_has(X86_FEATURE_INVPCID))
195 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
196 pr_info("noinvpcid: INVPCID feature disabled\n");
199 early_param("noinvpcid", x86_noinvpcid_setup);
202 static int cachesize_override = -1;
203 static int disable_x86_serial_nr = 1;
205 static int __init cachesize_setup(char *str)
207 get_option(&str, &cachesize_override);
210 __setup("cachesize=", cachesize_setup);
212 static int __init x86_sep_setup(char *s)
214 setup_clear_cpu_cap(X86_FEATURE_SEP);
217 __setup("nosep", x86_sep_setup);
219 /* Standard macro to see if a specific flag is changeable */
220 static inline int flag_is_changeable_p(u32 flag)
225 * Cyrix and IDT cpus allow disabling of CPUID
226 * so the code below may return different results
227 * when it is executed before and after enabling
228 * the CPUID. Add "volatile" to not allow gcc to
229 * optimize the subsequent calls to this function.
231 asm volatile ("pushfl \n\t"
242 : "=&r" (f1), "=&r" (f2)
245 return ((f1^f2) & flag) != 0;
248 /* Probe for the CPUID instruction */
249 int have_cpuid_p(void)
251 return flag_is_changeable_p(X86_EFLAGS_ID);
254 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
256 unsigned long lo, hi;
258 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
261 /* Disable processor serial number: */
263 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
265 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
267 pr_notice("CPU serial number disabled.\n");
268 clear_cpu_cap(c, X86_FEATURE_PN);
270 /* Disabling the serial number may affect the cpuid level */
271 c->cpuid_level = cpuid_eax(0);
274 static int __init x86_serial_nr_setup(char *s)
276 disable_x86_serial_nr = 0;
279 __setup("serialnumber", x86_serial_nr_setup);
281 static inline int flag_is_changeable_p(u32 flag)
285 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
290 static __init int setup_disable_smep(char *arg)
292 setup_clear_cpu_cap(X86_FEATURE_SMEP);
295 __setup("nosmep", setup_disable_smep);
297 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
299 if (cpu_has(c, X86_FEATURE_SMEP))
300 cr4_set_bits(X86_CR4_SMEP);
303 static __init int setup_disable_smap(char *arg)
305 setup_clear_cpu_cap(X86_FEATURE_SMAP);
308 __setup("nosmap", setup_disable_smap);
310 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
312 unsigned long eflags = native_save_fl();
314 /* This should have been cleared long ago */
315 BUG_ON(eflags & X86_EFLAGS_AC);
317 if (cpu_has(c, X86_FEATURE_SMAP)) {
318 #ifdef CONFIG_X86_SMAP
319 cr4_set_bits(X86_CR4_SMAP);
321 cr4_clear_bits(X86_CR4_SMAP);
326 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
328 /* Check the boot processor, plus build option for UMIP. */
329 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
332 /* Check the current processor's cpuid bits. */
333 if (!cpu_has(c, X86_FEATURE_UMIP))
336 cr4_set_bits(X86_CR4_UMIP);
338 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
344 * Make sure UMIP is disabled in case it was enabled in a
345 * previous boot (e.g., via kexec).
347 cr4_clear_bits(X86_CR4_UMIP);
350 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
351 static unsigned long cr4_pinned_bits __ro_after_init;
353 void native_write_cr0(unsigned long val)
355 unsigned long bits_missing = 0;
358 asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order));
360 if (static_branch_likely(&cr_pinning)) {
361 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
362 bits_missing = X86_CR0_WP;
366 /* Warn after we've set the missing bits. */
367 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
370 EXPORT_SYMBOL(native_write_cr0);
372 void native_write_cr4(unsigned long val)
374 unsigned long bits_missing = 0;
377 asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits));
379 if (static_branch_likely(&cr_pinning)) {
380 if (unlikely((val & cr4_pinned_bits) != cr4_pinned_bits)) {
381 bits_missing = ~val & cr4_pinned_bits;
385 /* Warn after we've set the missing bits. */
386 WARN_ONCE(bits_missing, "CR4 bits went missing: %lx!?\n",
390 EXPORT_SYMBOL(native_write_cr4);
394 unsigned long cr4 = __read_cr4();
396 if (boot_cpu_has(X86_FEATURE_PCID))
397 cr4 |= X86_CR4_PCIDE;
398 if (static_branch_likely(&cr_pinning))
399 cr4 |= cr4_pinned_bits;
403 /* Initialize cr4 shadow for this CPU. */
404 this_cpu_write(cpu_tlbstate.cr4, cr4);
408 * Once CPU feature detection is finished (and boot params have been
409 * parsed), record any of the sensitive CR bits that are set, and
412 static void __init setup_cr_pinning(void)
416 mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP);
417 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask;
418 static_key_enable(&cr_pinning.key);
422 * Protection Keys are not available in 32-bit mode.
424 static bool pku_disabled;
426 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
428 struct pkru_state *pk;
430 /* check the boot processor, plus compile options for PKU: */
431 if (!cpu_feature_enabled(X86_FEATURE_PKU))
433 /* checks the actual processor's cpuid bits: */
434 if (!cpu_has(c, X86_FEATURE_PKU))
439 cr4_set_bits(X86_CR4_PKE);
440 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU);
442 pk->pkru = init_pkru_value;
444 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
445 * cpuid bit to be set. We need to ensure that we
446 * update that bit in this CPU's "cpu_info".
448 set_cpu_cap(c, X86_FEATURE_OSPKE);
451 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
452 static __init int setup_disable_pku(char *arg)
455 * Do not clear the X86_FEATURE_PKU bit. All of the
456 * runtime checks are against OSPKE so clearing the
459 * This way, we will see "pku" in cpuinfo, but not
460 * "ospke", which is exactly what we want. It shows
461 * that the CPU has PKU, but the OS has not enabled it.
462 * This happens to be exactly how a system would look
463 * if we disabled the config option.
465 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
469 __setup("nopku", setup_disable_pku);
470 #endif /* CONFIG_X86_64 */
473 * Some CPU features depend on higher CPUID levels, which may not always
474 * be available due to CPUID level capping or broken virtualization
475 * software. Add those features to this table to auto-disable them.
477 struct cpuid_dependent_feature {
482 static const struct cpuid_dependent_feature
483 cpuid_dependent_features[] = {
484 { X86_FEATURE_MWAIT, 0x00000005 },
485 { X86_FEATURE_DCA, 0x00000009 },
486 { X86_FEATURE_XSAVE, 0x0000000d },
490 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
492 const struct cpuid_dependent_feature *df;
494 for (df = cpuid_dependent_features; df->feature; df++) {
496 if (!cpu_has(c, df->feature))
499 * Note: cpuid_level is set to -1 if unavailable, but
500 * extended_extended_level is set to 0 if unavailable
501 * and the legitimate extended levels are all negative
502 * when signed; hence the weird messing around with
505 if (!((s32)df->level < 0 ?
506 (u32)df->level > (u32)c->extended_cpuid_level :
507 (s32)df->level > (s32)c->cpuid_level))
510 clear_cpu_cap(c, df->feature);
514 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
515 x86_cap_flag(df->feature), df->level);
520 * Naming convention should be: <Name> [(<Codename>)]
521 * This table only is used unless init_<vendor>() below doesn't set it;
522 * in particular, if CPUID levels 0x80000002..4 are supported, this
526 /* Look up CPU names by table lookup. */
527 static const char *table_lookup_model(struct cpuinfo_x86 *c)
530 const struct legacy_cpu_model_info *info;
532 if (c->x86_model >= 16)
533 return NULL; /* Range check */
538 info = this_cpu->legacy_models;
540 while (info->family) {
541 if (info->family == c->x86)
542 return info->model_names[c->x86_model];
546 return NULL; /* Not found */
549 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
550 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
551 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
553 void load_percpu_segment(int cpu)
556 loadsegment(fs, __KERNEL_PERCPU);
558 __loadsegment_simple(gs, 0);
559 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
561 load_stack_canary_segment();
565 /* The 32-bit entry code needs to find cpu_entry_area. */
566 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
569 /* Load the original GDT from the per-cpu structure */
570 void load_direct_gdt(int cpu)
572 struct desc_ptr gdt_descr;
574 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
575 gdt_descr.size = GDT_SIZE - 1;
576 load_gdt(&gdt_descr);
578 EXPORT_SYMBOL_GPL(load_direct_gdt);
580 /* Load a fixmap remapping of the per-cpu GDT */
581 void load_fixmap_gdt(int cpu)
583 struct desc_ptr gdt_descr;
585 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
586 gdt_descr.size = GDT_SIZE - 1;
587 load_gdt(&gdt_descr);
589 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
592 * Current gdt points %fs at the "master" per-cpu area: after this,
593 * it's on the real one.
595 void switch_to_new_gdt(int cpu)
597 /* Load the original GDT */
598 load_direct_gdt(cpu);
599 /* Reload the per-cpu base */
600 load_percpu_segment(cpu);
603 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
605 static void get_model_name(struct cpuinfo_x86 *c)
610 if (c->extended_cpuid_level < 0x80000004)
613 v = (unsigned int *)c->x86_model_id;
614 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
615 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
616 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
617 c->x86_model_id[48] = 0;
619 /* Trim whitespace */
620 p = q = s = &c->x86_model_id[0];
626 /* Note the last non-whitespace index */
636 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
638 unsigned int eax, ebx, ecx, edx;
640 c->x86_max_cores = 1;
641 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
644 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
646 c->x86_max_cores = (eax >> 26) + 1;
649 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
651 unsigned int n, dummy, ebx, ecx, edx, l2size;
653 n = c->extended_cpuid_level;
655 if (n >= 0x80000005) {
656 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
657 c->x86_cache_size = (ecx>>24) + (edx>>24);
659 /* On K8 L1 TLB is inclusive, so don't count it */
664 if (n < 0x80000006) /* Some chips just has a large L1. */
667 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
671 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
673 /* do processor-specific cache resizing */
674 if (this_cpu->legacy_cache_size)
675 l2size = this_cpu->legacy_cache_size(c, l2size);
677 /* Allow user to override all this if necessary. */
678 if (cachesize_override != -1)
679 l2size = cachesize_override;
682 return; /* Again, no L2 cache is possible */
685 c->x86_cache_size = l2size;
688 u16 __read_mostly tlb_lli_4k[NR_INFO];
689 u16 __read_mostly tlb_lli_2m[NR_INFO];
690 u16 __read_mostly tlb_lli_4m[NR_INFO];
691 u16 __read_mostly tlb_lld_4k[NR_INFO];
692 u16 __read_mostly tlb_lld_2m[NR_INFO];
693 u16 __read_mostly tlb_lld_4m[NR_INFO];
694 u16 __read_mostly tlb_lld_1g[NR_INFO];
696 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
698 if (this_cpu->c_detect_tlb)
699 this_cpu->c_detect_tlb(c);
701 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
702 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
703 tlb_lli_4m[ENTRIES]);
705 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
706 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
707 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
710 int detect_ht_early(struct cpuinfo_x86 *c)
713 u32 eax, ebx, ecx, edx;
715 if (!cpu_has(c, X86_FEATURE_HT))
718 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
721 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
724 cpuid(1, &eax, &ebx, &ecx, &edx);
726 smp_num_siblings = (ebx & 0xff0000) >> 16;
727 if (smp_num_siblings == 1)
728 pr_info_once("CPU0: Hyper-Threading is disabled\n");
733 void detect_ht(struct cpuinfo_x86 *c)
736 int index_msb, core_bits;
738 if (detect_ht_early(c) < 0)
741 index_msb = get_count_order(smp_num_siblings);
742 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
744 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
746 index_msb = get_count_order(smp_num_siblings);
748 core_bits = get_count_order(c->x86_max_cores);
750 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
751 ((1 << core_bits) - 1);
755 static void get_cpu_vendor(struct cpuinfo_x86 *c)
757 char *v = c->x86_vendor_id;
760 for (i = 0; i < X86_VENDOR_NUM; i++) {
764 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
765 (cpu_devs[i]->c_ident[1] &&
766 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
768 this_cpu = cpu_devs[i];
769 c->x86_vendor = this_cpu->c_x86_vendor;
774 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
775 "CPU: Your system may be unstable.\n", v);
777 c->x86_vendor = X86_VENDOR_UNKNOWN;
778 this_cpu = &default_cpu;
781 void cpu_detect(struct cpuinfo_x86 *c)
783 /* Get vendor name */
784 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
785 (unsigned int *)&c->x86_vendor_id[0],
786 (unsigned int *)&c->x86_vendor_id[8],
787 (unsigned int *)&c->x86_vendor_id[4]);
790 /* Intel-defined flags: level 0x00000001 */
791 if (c->cpuid_level >= 0x00000001) {
792 u32 junk, tfms, cap0, misc;
794 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
795 c->x86 = x86_family(tfms);
796 c->x86_model = x86_model(tfms);
797 c->x86_stepping = x86_stepping(tfms);
799 if (cap0 & (1<<19)) {
800 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
801 c->x86_cache_alignment = c->x86_clflush_size;
806 static void apply_forced_caps(struct cpuinfo_x86 *c)
810 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
811 c->x86_capability[i] &= ~cpu_caps_cleared[i];
812 c->x86_capability[i] |= cpu_caps_set[i];
816 static void init_speculation_control(struct cpuinfo_x86 *c)
819 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
820 * and they also have a different bit for STIBP support. Also,
821 * a hypervisor might have set the individual AMD bits even on
822 * Intel CPUs, for finer-grained selection of what's available.
824 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
825 set_cpu_cap(c, X86_FEATURE_IBRS);
826 set_cpu_cap(c, X86_FEATURE_IBPB);
827 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
830 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
831 set_cpu_cap(c, X86_FEATURE_STIBP);
833 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
834 cpu_has(c, X86_FEATURE_VIRT_SSBD))
835 set_cpu_cap(c, X86_FEATURE_SSBD);
837 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
838 set_cpu_cap(c, X86_FEATURE_IBRS);
839 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
842 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
843 set_cpu_cap(c, X86_FEATURE_IBPB);
845 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
846 set_cpu_cap(c, X86_FEATURE_STIBP);
847 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
850 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
851 set_cpu_cap(c, X86_FEATURE_SSBD);
852 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
853 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
857 void get_cpu_cap(struct cpuinfo_x86 *c)
859 u32 eax, ebx, ecx, edx;
861 /* Intel-defined flags: level 0x00000001 */
862 if (c->cpuid_level >= 0x00000001) {
863 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
865 c->x86_capability[CPUID_1_ECX] = ecx;
866 c->x86_capability[CPUID_1_EDX] = edx;
869 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
870 if (c->cpuid_level >= 0x00000006)
871 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
873 /* Additional Intel-defined flags: level 0x00000007 */
874 if (c->cpuid_level >= 0x00000007) {
875 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
876 c->x86_capability[CPUID_7_0_EBX] = ebx;
877 c->x86_capability[CPUID_7_ECX] = ecx;
878 c->x86_capability[CPUID_7_EDX] = edx;
880 /* Check valid sub-leaf index before accessing it */
882 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
883 c->x86_capability[CPUID_7_1_EAX] = eax;
887 /* Extended state features: level 0x0000000d */
888 if (c->cpuid_level >= 0x0000000d) {
889 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
891 c->x86_capability[CPUID_D_1_EAX] = eax;
894 /* AMD-defined flags: level 0x80000001 */
895 eax = cpuid_eax(0x80000000);
896 c->extended_cpuid_level = eax;
898 if ((eax & 0xffff0000) == 0x80000000) {
899 if (eax >= 0x80000001) {
900 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
902 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
903 c->x86_capability[CPUID_8000_0001_EDX] = edx;
907 if (c->extended_cpuid_level >= 0x80000007) {
908 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
910 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
914 if (c->extended_cpuid_level >= 0x80000008) {
915 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
916 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
919 if (c->extended_cpuid_level >= 0x8000000a)
920 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
922 init_scattered_cpuid_features(c);
923 init_speculation_control(c);
926 * Clear/Set all flags overridden by options, after probe.
927 * This needs to happen each time we re-probe, which may happen
928 * several times during CPU initialization.
930 apply_forced_caps(c);
933 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
935 u32 eax, ebx, ecx, edx;
937 if (c->extended_cpuid_level >= 0x80000008) {
938 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
940 c->x86_virt_bits = (eax >> 8) & 0xff;
941 c->x86_phys_bits = eax & 0xff;
944 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
945 c->x86_phys_bits = 36;
947 c->x86_cache_bits = c->x86_phys_bits;
950 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
956 * First of all, decide if this is a 486 or higher
957 * It's a 486 if we can modify the AC flag
959 if (flag_is_changeable_p(X86_EFLAGS_AC))
964 for (i = 0; i < X86_VENDOR_NUM; i++)
965 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
966 c->x86_vendor_id[0] = 0;
967 cpu_devs[i]->c_identify(c);
968 if (c->x86_vendor_id[0]) {
976 #define NO_SPECULATION BIT(0)
977 #define NO_MELTDOWN BIT(1)
978 #define NO_SSB BIT(2)
979 #define NO_L1TF BIT(3)
980 #define NO_MDS BIT(4)
981 #define MSBDS_ONLY BIT(5)
982 #define NO_SWAPGS BIT(6)
983 #define NO_ITLB_MULTIHIT BIT(7)
984 #define NO_SPECTRE_V2 BIT(8)
986 #define VULNWL(vendor, family, model, whitelist) \
987 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
989 #define VULNWL_INTEL(model, whitelist) \
990 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
992 #define VULNWL_AMD(family, whitelist) \
993 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
995 #define VULNWL_HYGON(family, whitelist) \
996 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
998 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
999 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1000 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1001 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1002 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1004 /* Intel Family 6 */
1005 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1006 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1007 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1008 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1009 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1011 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1012 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1013 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1014 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1015 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1016 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1018 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1020 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1021 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1023 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1024 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1025 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1028 * Technically, swapgs isn't serializing on AMD (despite it previously
1029 * being documented as such in the APM). But according to AMD, %gs is
1030 * updated non-speculatively, and the issuing of %gs-relative memory
1031 * operands will be blocked until the %gs update completes, which is
1032 * good enough for our purposes.
1035 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT),
1037 /* AMD Family 0xf - 0x12 */
1038 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1039 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1040 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1041 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1043 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1044 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1045 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1047 /* Zhaoxin Family 7 */
1048 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1049 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1053 static bool __init cpu_matches(unsigned long which)
1055 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist);
1057 return m && !!(m->driver_data & which);
1060 u64 x86_read_arch_cap_msr(void)
1064 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1065 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1070 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1072 u64 ia32_cap = x86_read_arch_cap_msr();
1074 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1075 if (!cpu_matches(NO_ITLB_MULTIHIT) && !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1076 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1078 if (cpu_matches(NO_SPECULATION))
1081 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1083 if (!cpu_matches(NO_SPECTRE_V2))
1084 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1086 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) &&
1087 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1088 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1090 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1091 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1093 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) {
1094 setup_force_cpu_bug(X86_BUG_MDS);
1095 if (cpu_matches(MSBDS_ONLY))
1096 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1099 if (!cpu_matches(NO_SWAPGS))
1100 setup_force_cpu_bug(X86_BUG_SWAPGS);
1103 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1104 * - TSX is supported or
1105 * - TSX_CTRL is present
1107 * TSX_CTRL check is needed for cases when TSX could be disabled before
1108 * the kernel boot e.g. kexec.
1109 * TSX_CTRL check alone is not sufficient for cases when the microcode
1110 * update is not present or running as guest that don't get TSX_CTRL.
1112 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1113 (cpu_has(c, X86_FEATURE_RTM) ||
1114 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1115 setup_force_cpu_bug(X86_BUG_TAA);
1117 if (cpu_matches(NO_MELTDOWN))
1120 /* Rogue Data Cache Load? No! */
1121 if (ia32_cap & ARCH_CAP_RDCL_NO)
1124 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1126 if (cpu_matches(NO_L1TF))
1129 setup_force_cpu_bug(X86_BUG_L1TF);
1133 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1134 * unfortunately, that's not true in practice because of early VIA
1135 * chips and (more importantly) broken virtualizers that are not easy
1136 * to detect. In the latter case it doesn't even *fail* reliably, so
1137 * probing for it doesn't even work. Disable it completely on 32-bit
1138 * unless we can find a reliable way to detect all the broken cases.
1139 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1141 static void detect_nopl(void)
1143 #ifdef CONFIG_X86_32
1144 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1146 setup_force_cpu_cap(X86_FEATURE_NOPL);
1151 * Do minimum CPU detection early.
1152 * Fields really needed: vendor, cpuid_level, family, model, mask,
1154 * The others are not touched to avoid unwanted side effects.
1156 * WARNING: this function is only called on the boot CPU. Don't add code
1157 * here that is supposed to run on all CPUs.
1159 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1161 #ifdef CONFIG_X86_64
1162 c->x86_clflush_size = 64;
1163 c->x86_phys_bits = 36;
1164 c->x86_virt_bits = 48;
1166 c->x86_clflush_size = 32;
1167 c->x86_phys_bits = 32;
1168 c->x86_virt_bits = 32;
1170 c->x86_cache_alignment = c->x86_clflush_size;
1172 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1173 c->extended_cpuid_level = 0;
1175 if (!have_cpuid_p())
1176 identify_cpu_without_cpuid(c);
1178 /* cyrix could have cpuid enabled via c_identify()*/
1179 if (have_cpuid_p()) {
1183 get_cpu_address_sizes(c);
1184 setup_force_cpu_cap(X86_FEATURE_CPUID);
1186 if (this_cpu->c_early_init)
1187 this_cpu->c_early_init(c);
1190 filter_cpuid_features(c, false);
1192 if (this_cpu->c_bsp_init)
1193 this_cpu->c_bsp_init(c);
1195 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1198 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1200 cpu_set_bug_bits(c);
1202 cpu_set_core_cap_bits(c);
1204 fpu__init_system(c);
1206 #ifdef CONFIG_X86_32
1208 * Regardless of whether PCID is enumerated, the SDM says
1209 * that it can't be enabled in 32-bit mode.
1211 setup_clear_cpu_cap(X86_FEATURE_PCID);
1215 * Later in the boot process pgtable_l5_enabled() relies on
1216 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1217 * enabled by this point we need to clear the feature bit to avoid
1218 * false-positives at the later stage.
1220 * pgtable_l5_enabled() can be false here for several reasons:
1221 * - 5-level paging is disabled compile-time;
1222 * - it's 32-bit kernel;
1223 * - machine doesn't support 5-level paging;
1224 * - user specified 'no5lvl' in kernel command line.
1226 if (!pgtable_l5_enabled())
1227 setup_clear_cpu_cap(X86_FEATURE_LA57);
1232 void __init early_cpu_init(void)
1234 const struct cpu_dev *const *cdev;
1237 #ifdef CONFIG_PROCESSOR_SELECT
1238 pr_info("KERNEL supported cpus:\n");
1241 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1242 const struct cpu_dev *cpudev = *cdev;
1244 if (count >= X86_VENDOR_NUM)
1246 cpu_devs[count] = cpudev;
1249 #ifdef CONFIG_PROCESSOR_SELECT
1253 for (j = 0; j < 2; j++) {
1254 if (!cpudev->c_ident[j])
1256 pr_info(" %s %s\n", cpudev->c_vendor,
1257 cpudev->c_ident[j]);
1262 early_identify_cpu(&boot_cpu_data);
1265 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1267 #ifdef CONFIG_X86_64
1269 * Empirically, writing zero to a segment selector on AMD does
1270 * not clear the base, whereas writing zero to a segment
1271 * selector on Intel does clear the base. Intel's behavior
1272 * allows slightly faster context switches in the common case
1273 * where GS is unused by the prev and next threads.
1275 * Since neither vendor documents this anywhere that I can see,
1276 * detect it directly instead of hardcoding the choice by
1279 * I've designated AMD's behavior as the "bug" because it's
1280 * counterintuitive and less friendly.
1283 unsigned long old_base, tmp;
1284 rdmsrl(MSR_FS_BASE, old_base);
1285 wrmsrl(MSR_FS_BASE, 1);
1287 rdmsrl(MSR_FS_BASE, tmp);
1289 set_cpu_bug(c, X86_BUG_NULL_SEG);
1290 wrmsrl(MSR_FS_BASE, old_base);
1294 static void generic_identify(struct cpuinfo_x86 *c)
1296 c->extended_cpuid_level = 0;
1298 if (!have_cpuid_p())
1299 identify_cpu_without_cpuid(c);
1301 /* cyrix could have cpuid enabled via c_identify()*/
1302 if (!have_cpuid_p())
1311 get_cpu_address_sizes(c);
1313 if (c->cpuid_level >= 0x00000001) {
1314 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1315 #ifdef CONFIG_X86_32
1317 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1319 c->apicid = c->initial_apicid;
1322 c->phys_proc_id = c->initial_apicid;
1325 get_model_name(c); /* Default name */
1327 detect_null_seg_behavior(c);
1330 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1331 * systems that run Linux at CPL > 0 may or may not have the
1332 * issue, but, even if they have the issue, there's absolutely
1333 * nothing we can do about it because we can't use the real IRET
1336 * NB: For the time being, only 32-bit kernels support
1337 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1338 * whether to apply espfix using paravirt hooks. If any
1339 * non-paravirt system ever shows up that does *not* have the
1340 * ESPFIX issue, we can change this.
1342 #ifdef CONFIG_X86_32
1343 # ifdef CONFIG_PARAVIRT_XXL
1345 extern void native_iret(void);
1346 if (pv_ops.cpu.iret == native_iret)
1347 set_cpu_bug(c, X86_BUG_ESPFIX);
1350 set_cpu_bug(c, X86_BUG_ESPFIX);
1356 * Validate that ACPI/mptables have the same information about the
1357 * effective APIC id and update the package map.
1359 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1362 unsigned int apicid, cpu = smp_processor_id();
1364 apicid = apic->cpu_present_to_apicid(cpu);
1366 if (apicid != c->apicid) {
1367 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1368 cpu, apicid, c->initial_apicid);
1370 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1371 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu));
1373 c->logical_proc_id = 0;
1378 * This does the hard work of actually picking apart the CPU stuff...
1380 static void identify_cpu(struct cpuinfo_x86 *c)
1384 c->loops_per_jiffy = loops_per_jiffy;
1385 c->x86_cache_size = 0;
1386 c->x86_vendor = X86_VENDOR_UNKNOWN;
1387 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1388 c->x86_vendor_id[0] = '\0'; /* Unset */
1389 c->x86_model_id[0] = '\0'; /* Unset */
1390 c->x86_max_cores = 1;
1391 c->x86_coreid_bits = 0;
1393 #ifdef CONFIG_X86_64
1394 c->x86_clflush_size = 64;
1395 c->x86_phys_bits = 36;
1396 c->x86_virt_bits = 48;
1398 c->cpuid_level = -1; /* CPUID not detected */
1399 c->x86_clflush_size = 32;
1400 c->x86_phys_bits = 32;
1401 c->x86_virt_bits = 32;
1403 c->x86_cache_alignment = c->x86_clflush_size;
1404 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1405 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1406 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1409 generic_identify(c);
1411 if (this_cpu->c_identify)
1412 this_cpu->c_identify(c);
1414 /* Clear/Set all flags overridden by options, after probe */
1415 apply_forced_caps(c);
1417 #ifdef CONFIG_X86_64
1418 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1422 * Vendor-specific initialization. In this section we
1423 * canonicalize the feature flags, meaning if there are
1424 * features a certain CPU supports which CPUID doesn't
1425 * tell us, CPUID claiming incorrect flags, or other bugs,
1426 * we handle them here.
1428 * At the end of this section, c->x86_capability better
1429 * indicate the features this CPU genuinely supports!
1431 if (this_cpu->c_init)
1432 this_cpu->c_init(c);
1434 /* Disable the PN if appropriate */
1435 squash_the_stupid_serial_number(c);
1437 /* Set up SMEP/SMAP/UMIP */
1443 * The vendor-specific functions might have changed features.
1444 * Now we do "generic changes."
1447 /* Filter out anything that depends on CPUID levels we don't have */
1448 filter_cpuid_features(c, true);
1450 /* If the model name is still unset, do table lookup. */
1451 if (!c->x86_model_id[0]) {
1453 p = table_lookup_model(c);
1455 strcpy(c->x86_model_id, p);
1457 /* Last resort... */
1458 sprintf(c->x86_model_id, "%02x/%02x",
1459 c->x86, c->x86_model);
1462 #ifdef CONFIG_X86_64
1470 * Clear/Set all flags overridden by options, need do it
1471 * before following smp all cpus cap AND.
1473 apply_forced_caps(c);
1476 * On SMP, boot_cpu_data holds the common feature set between
1477 * all CPUs; so make sure that we indicate which features are
1478 * common between the CPUs. The first time this routine gets
1479 * executed, c == &boot_cpu_data.
1481 if (c != &boot_cpu_data) {
1482 /* AND the already accumulated flags with these */
1483 for (i = 0; i < NCAPINTS; i++)
1484 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1486 /* OR, i.e. replicate the bug flags */
1487 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1488 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1491 /* Init Machine Check Exception if available. */
1494 select_idle_routine(c);
1497 numa_add_cpu(smp_processor_id());
1502 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1503 * on 32-bit kernels:
1505 #ifdef CONFIG_X86_32
1506 void enable_sep_cpu(void)
1508 struct tss_struct *tss;
1511 if (!boot_cpu_has(X86_FEATURE_SEP))
1515 tss = &per_cpu(cpu_tss_rw, cpu);
1518 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1519 * see the big comment in struct x86_hw_tss's definition.
1522 tss->x86_tss.ss1 = __KERNEL_CS;
1523 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1524 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1525 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1531 void __init identify_boot_cpu(void)
1533 identify_cpu(&boot_cpu_data);
1534 #ifdef CONFIG_X86_32
1538 cpu_detect_tlb(&boot_cpu_data);
1544 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1546 BUG_ON(c == &boot_cpu_data);
1548 #ifdef CONFIG_X86_32
1552 validate_apic_and_package_id(c);
1553 x86_spec_ctrl_setup_ap();
1556 static __init int setup_noclflush(char *arg)
1558 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1559 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1562 __setup("noclflush", setup_noclflush);
1564 void print_cpu_info(struct cpuinfo_x86 *c)
1566 const char *vendor = NULL;
1568 if (c->x86_vendor < X86_VENDOR_NUM) {
1569 vendor = this_cpu->c_vendor;
1571 if (c->cpuid_level >= 0)
1572 vendor = c->x86_vendor_id;
1575 if (vendor && !strstr(c->x86_model_id, vendor))
1576 pr_cont("%s ", vendor);
1578 if (c->x86_model_id[0])
1579 pr_cont("%s", c->x86_model_id);
1581 pr_cont("%d86", c->x86);
1583 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1585 if (c->x86_stepping || c->cpuid_level >= 0)
1586 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1592 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1593 * But we need to keep a dummy __setup around otherwise it would
1594 * show up as an environment variable for init.
1596 static __init int setup_clearcpuid(char *arg)
1600 __setup("clearcpuid=", setup_clearcpuid);
1602 #ifdef CONFIG_X86_64
1603 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
1604 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
1605 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
1608 * The following percpu variables are hot. Align current_task to
1609 * cacheline size such that they fall in the same cacheline.
1611 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1613 EXPORT_PER_CPU_SYMBOL(current_task);
1615 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
1616 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1618 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1619 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1621 /* May not be marked __init: used by software suspend */
1622 void syscall_init(void)
1624 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1625 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1627 #ifdef CONFIG_IA32_EMULATION
1628 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1630 * This only works on Intel CPUs.
1631 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1632 * This does not cause SYSENTER to jump to the wrong location, because
1633 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1635 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1636 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1637 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1638 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1640 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1641 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1642 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1643 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1646 /* Flags to clear on syscall */
1647 wrmsrl(MSR_SYSCALL_MASK,
1648 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1649 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1652 DEFINE_PER_CPU(int, debug_stack_usage);
1653 DEFINE_PER_CPU(u32, debug_idt_ctr);
1655 void debug_stack_set_zero(void)
1657 this_cpu_inc(debug_idt_ctr);
1660 NOKPROBE_SYMBOL(debug_stack_set_zero);
1662 void debug_stack_reset(void)
1664 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1666 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1669 NOKPROBE_SYMBOL(debug_stack_reset);
1671 #else /* CONFIG_X86_64 */
1673 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1674 EXPORT_PER_CPU_SYMBOL(current_task);
1675 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1676 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1679 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1680 * the top of the kernel stack. Use an extra percpu variable to track the
1681 * top of the kernel stack directly.
1683 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1684 (unsigned long)&init_thread_union + THREAD_SIZE;
1685 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1687 #ifdef CONFIG_STACKPROTECTOR
1688 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1691 #endif /* CONFIG_X86_64 */
1694 * Clear all 6 debug registers:
1696 static void clear_all_debug_regs(void)
1700 for (i = 0; i < 8; i++) {
1701 /* Ignore db4, db5 */
1702 if ((i == 4) || (i == 5))
1711 * Restore debug regs if using kgdbwait and you have a kernel debugger
1712 * connection established.
1714 static void dbg_restore_debug_regs(void)
1716 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1717 arch_kgdb_ops.correct_hw_break();
1719 #else /* ! CONFIG_KGDB */
1720 #define dbg_restore_debug_regs()
1721 #endif /* ! CONFIG_KGDB */
1723 static void wait_for_master_cpu(int cpu)
1727 * wait for ACK from master CPU before continuing
1728 * with AP initialization
1730 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1731 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1736 #ifdef CONFIG_X86_64
1737 static inline void setup_getcpu(int cpu)
1739 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
1740 struct desc_struct d = { };
1742 if (boot_cpu_has(X86_FEATURE_RDTSCP))
1743 write_rdtscp_aux(cpudata);
1745 /* Store CPU and node number in limit. */
1747 d.limit1 = cpudata >> 16;
1749 d.type = 5; /* RO data, expand down, accessed */
1750 d.dpl = 3; /* Visible to user code */
1751 d.s = 1; /* Not a system segment */
1752 d.p = 1; /* Present */
1753 d.d = 1; /* 32-bit */
1755 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
1758 static inline void ucode_cpu_init(int cpu)
1764 static inline void tss_setup_ist(struct tss_struct *tss)
1766 /* Set up the per-CPU TSS IST stacks */
1767 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
1768 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
1769 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
1770 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
1773 #else /* CONFIG_X86_64 */
1775 static inline void setup_getcpu(int cpu) { }
1777 static inline void ucode_cpu_init(int cpu)
1779 show_ucode_info_early();
1782 static inline void tss_setup_ist(struct tss_struct *tss) { }
1784 #endif /* !CONFIG_X86_64 */
1786 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
1788 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
1790 #ifdef CONFIG_X86_IOPL_IOPERM
1791 tss->io_bitmap.prev_max = 0;
1792 tss->io_bitmap.prev_sequence = 0;
1793 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
1795 * Invalidate the extra array entry past the end of the all
1796 * permission bitmap as required by the hardware.
1798 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
1803 * cpu_init() initializes state that is per-CPU. Some data is already
1804 * initialized (naturally) in the bootstrap process, such as the GDT
1805 * and IDT. We reload them nevertheless, this function acts as a
1806 * 'CPU state barrier', nothing should get across.
1810 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
1811 struct task_struct *cur = current;
1812 int cpu = raw_smp_processor_id();
1814 wait_for_master_cpu(cpu);
1816 ucode_cpu_init(cpu);
1819 if (this_cpu_read(numa_node) == 0 &&
1820 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1821 set_numa_node(early_cpu_to_node(cpu));
1825 pr_debug("Initializing CPU#%d\n", cpu);
1827 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
1828 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
1829 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1832 * Initialize the per-CPU GDT with the boot GDT,
1833 * and set up the GDT descriptor:
1835 switch_to_new_gdt(cpu);
1838 if (IS_ENABLED(CONFIG_X86_64)) {
1840 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1843 wrmsrl(MSR_FS_BASE, 0);
1844 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1851 cur->active_mm = &init_mm;
1853 initialize_tlbstate_and_flush();
1854 enter_lazy_tlb(&init_mm, cur);
1856 /* Initialize the TSS. */
1858 tss_setup_io_bitmap(tss);
1859 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1863 * sp0 points to the entry trampoline stack regardless of what task
1866 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1868 load_mm_ldt(&init_mm);
1870 clear_all_debug_regs();
1871 dbg_restore_debug_regs();
1873 doublefault_init_cpu_tss();
1880 load_fixmap_gdt(cpu);
1884 * The microcode loader calls this upon late microcode load to recheck features,
1885 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1888 void microcode_check(void)
1890 struct cpuinfo_x86 info;
1892 perf_check_microcode();
1894 /* Reload CPUID max function as it might've changed. */
1895 info.cpuid_level = cpuid_eax(0);
1898 * Copy all capability leafs to pick up the synthetic ones so that
1899 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1900 * get overwritten in get_cpu_cap().
1902 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
1906 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
1909 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1910 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
1914 * Invoked from core CPU hotplug code after hotplug operations
1916 void arch_smt_update(void)
1918 /* Handle the speculative execution misfeatures */
1919 cpu_bugs_smt_update();
1920 /* Check whether IPI broadcasting can be enabled */