1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
15 #include <asm/stackprotector.h>
16 #include <asm/perf_event.h>
17 #include <asm/mmu_context.h>
18 #include <asm/archrandom.h>
19 #include <asm/hypervisor.h>
20 #include <asm/processor.h>
21 #include <asm/debugreg.h>
22 #include <asm/sections.h>
23 #include <linux/topology.h>
24 #include <linux/cpumask.h>
25 #include <asm/pgtable.h>
26 #include <linux/atomic.h>
27 #include <asm/proto.h>
28 #include <asm/setup.h>
32 #include <asm/fpu-internal.h>
34 #include <linux/numa.h>
40 #include <asm/microcode.h>
41 #include <asm/microcode_intel.h>
43 #ifdef CONFIG_X86_LOCAL_APIC
44 #include <asm/uv/uv.h>
49 /* all of these masks are initialized in setup_cpu_local_masks() */
50 cpumask_var_t cpu_initialized_mask;
51 cpumask_var_t cpu_callout_mask;
52 cpumask_var_t cpu_callin_mask;
54 /* representing cpus for which sibling maps can be computed */
55 cpumask_var_t cpu_sibling_setup_mask;
57 /* correctly size the local cpu masks */
58 void __init setup_cpu_local_masks(void)
60 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
61 alloc_bootmem_cpumask_var(&cpu_callin_mask);
62 alloc_bootmem_cpumask_var(&cpu_callout_mask);
63 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
66 static void default_init(struct cpuinfo_x86 *c)
69 cpu_detect_cache_sizes(c);
71 /* Not much we can do here... */
72 /* Check if at least it has cpuid */
73 if (c->cpuid_level == -1) {
74 /* No cpuid. It must be an ancient CPU */
76 strcpy(c->x86_model_id, "486");
78 strcpy(c->x86_model_id, "386");
83 static const struct cpu_dev default_cpu = {
84 .c_init = default_init,
85 .c_vendor = "Unknown",
86 .c_x86_vendor = X86_VENDOR_UNKNOWN,
89 static const struct cpu_dev *this_cpu = &default_cpu;
91 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
94 * We need valid kernel segments for data and code in long mode too
95 * IRET will check the segment types kkeil 2000/10/28
96 * Also sysret mandates a special GDT layout
98 * TLS descriptors are currently at a different place compared to i386.
99 * Hopefully nobody expects them at a fixed place (Wine?)
101 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
102 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
103 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
104 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
105 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
106 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
108 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
109 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
111 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
113 * Segments used for calling PnP BIOS have byte granularity.
114 * They code segments and data segments have fixed 64k limits,
115 * the transfer segment sizes are set at run time.
118 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
120 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
122 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
124 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
126 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
128 * The APM segments have byte granularity and their bases
129 * are set at run time. All have 64k limits.
132 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
134 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
136 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
138 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
139 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
140 GDT_STACK_CANARY_INIT
143 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
145 static int __init x86_xsave_setup(char *s)
147 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
148 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
149 setup_clear_cpu_cap(X86_FEATURE_AVX);
150 setup_clear_cpu_cap(X86_FEATURE_AVX2);
153 __setup("noxsave", x86_xsave_setup);
155 static int __init x86_xsaveopt_setup(char *s)
157 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
160 __setup("noxsaveopt", x86_xsaveopt_setup);
163 static int cachesize_override = -1;
164 static int disable_x86_serial_nr = 1;
166 static int __init cachesize_setup(char *str)
168 get_option(&str, &cachesize_override);
171 __setup("cachesize=", cachesize_setup);
173 static int __init x86_fxsr_setup(char *s)
175 setup_clear_cpu_cap(X86_FEATURE_FXSR);
176 setup_clear_cpu_cap(X86_FEATURE_XMM);
179 __setup("nofxsr", x86_fxsr_setup);
181 static int __init x86_sep_setup(char *s)
183 setup_clear_cpu_cap(X86_FEATURE_SEP);
186 __setup("nosep", x86_sep_setup);
188 /* Standard macro to see if a specific flag is changeable */
189 static inline int flag_is_changeable_p(u32 flag)
194 * Cyrix and IDT cpus allow disabling of CPUID
195 * so the code below may return different results
196 * when it is executed before and after enabling
197 * the CPUID. Add "volatile" to not allow gcc to
198 * optimize the subsequent calls to this function.
200 asm volatile ("pushfl \n\t"
211 : "=&r" (f1), "=&r" (f2)
214 return ((f1^f2) & flag) != 0;
217 /* Probe for the CPUID instruction */
218 int have_cpuid_p(void)
220 return flag_is_changeable_p(X86_EFLAGS_ID);
223 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
225 unsigned long lo, hi;
227 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
230 /* Disable processor serial number: */
232 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
234 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
236 printk(KERN_NOTICE "CPU serial number disabled.\n");
237 clear_cpu_cap(c, X86_FEATURE_PN);
239 /* Disabling the serial number may affect the cpuid level */
240 c->cpuid_level = cpuid_eax(0);
243 static int __init x86_serial_nr_setup(char *s)
245 disable_x86_serial_nr = 0;
248 __setup("serialnumber", x86_serial_nr_setup);
250 static inline int flag_is_changeable_p(u32 flag)
254 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
259 static __init int setup_disable_smep(char *arg)
261 setup_clear_cpu_cap(X86_FEATURE_SMEP);
264 __setup("nosmep", setup_disable_smep);
266 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
268 if (cpu_has(c, X86_FEATURE_SMEP))
269 set_in_cr4(X86_CR4_SMEP);
272 static __init int setup_disable_smap(char *arg)
274 setup_clear_cpu_cap(X86_FEATURE_SMAP);
277 __setup("nosmap", setup_disable_smap);
279 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
281 unsigned long eflags;
283 /* This should have been cleared long ago */
284 raw_local_save_flags(eflags);
285 BUG_ON(eflags & X86_EFLAGS_AC);
287 if (cpu_has(c, X86_FEATURE_SMAP))
288 set_in_cr4(X86_CR4_SMAP);
292 * Some CPU features depend on higher CPUID levels, which may not always
293 * be available due to CPUID level capping or broken virtualization
294 * software. Add those features to this table to auto-disable them.
296 struct cpuid_dependent_feature {
301 static const struct cpuid_dependent_feature
302 cpuid_dependent_features[] = {
303 { X86_FEATURE_MWAIT, 0x00000005 },
304 { X86_FEATURE_DCA, 0x00000009 },
305 { X86_FEATURE_XSAVE, 0x0000000d },
309 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
311 const struct cpuid_dependent_feature *df;
313 for (df = cpuid_dependent_features; df->feature; df++) {
315 if (!cpu_has(c, df->feature))
318 * Note: cpuid_level is set to -1 if unavailable, but
319 * extended_extended_level is set to 0 if unavailable
320 * and the legitimate extended levels are all negative
321 * when signed; hence the weird messing around with
324 if (!((s32)df->level < 0 ?
325 (u32)df->level > (u32)c->extended_cpuid_level :
326 (s32)df->level > (s32)c->cpuid_level))
329 clear_cpu_cap(c, df->feature);
334 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
335 x86_cap_flags[df->feature], df->level);
340 * Naming convention should be: <Name> [(<Codename>)]
341 * This table only is used unless init_<vendor>() below doesn't set it;
342 * in particular, if CPUID levels 0x80000002..4 are supported, this
346 /* Look up CPU names by table lookup. */
347 static const char *table_lookup_model(struct cpuinfo_x86 *c)
350 const struct legacy_cpu_model_info *info;
352 if (c->x86_model >= 16)
353 return NULL; /* Range check */
358 info = this_cpu->legacy_models;
360 while (info->family) {
361 if (info->family == c->x86)
362 return info->model_names[c->x86_model];
366 return NULL; /* Not found */
369 __u32 cpu_caps_cleared[NCAPINTS];
370 __u32 cpu_caps_set[NCAPINTS];
372 void load_percpu_segment(int cpu)
375 loadsegment(fs, __KERNEL_PERCPU);
378 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
380 load_stack_canary_segment();
384 * Current gdt points %fs at the "master" per-cpu area: after this,
385 * it's on the real one.
387 void switch_to_new_gdt(int cpu)
389 struct desc_ptr gdt_descr;
391 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
392 gdt_descr.size = GDT_SIZE - 1;
393 load_gdt(&gdt_descr);
394 /* Reload the per-cpu base */
396 load_percpu_segment(cpu);
399 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
401 static void get_model_name(struct cpuinfo_x86 *c)
406 if (c->extended_cpuid_level < 0x80000004)
409 v = (unsigned int *)c->x86_model_id;
410 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
411 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
412 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
413 c->x86_model_id[48] = 0;
416 * Intel chips right-justify this string for some dumb reason;
417 * undo that brain damage:
419 p = q = &c->x86_model_id[0];
425 while (q <= &c->x86_model_id[48])
426 *q++ = '\0'; /* Zero-pad the rest */
430 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
432 unsigned int n, dummy, ebx, ecx, edx, l2size;
434 n = c->extended_cpuid_level;
436 if (n >= 0x80000005) {
437 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
438 c->x86_cache_size = (ecx>>24) + (edx>>24);
440 /* On K8 L1 TLB is inclusive, so don't count it */
445 if (n < 0x80000006) /* Some chips just has a large L1. */
448 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
452 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
454 /* do processor-specific cache resizing */
455 if (this_cpu->legacy_cache_size)
456 l2size = this_cpu->legacy_cache_size(c, l2size);
458 /* Allow user to override all this if necessary. */
459 if (cachesize_override != -1)
460 l2size = cachesize_override;
463 return; /* Again, no L2 cache is possible */
466 c->x86_cache_size = l2size;
469 u16 __read_mostly tlb_lli_4k[NR_INFO];
470 u16 __read_mostly tlb_lli_2m[NR_INFO];
471 u16 __read_mostly tlb_lli_4m[NR_INFO];
472 u16 __read_mostly tlb_lld_4k[NR_INFO];
473 u16 __read_mostly tlb_lld_2m[NR_INFO];
474 u16 __read_mostly tlb_lld_4m[NR_INFO];
475 u16 __read_mostly tlb_lld_1g[NR_INFO];
478 * tlb_flushall_shift shows the balance point in replacing cr3 write
479 * with multiple 'invlpg'. It will do this replacement when
480 * flush_tlb_lines <= active_lines/2^tlb_flushall_shift.
481 * If tlb_flushall_shift is -1, means the replacement will be disabled.
483 s8 __read_mostly tlb_flushall_shift = -1;
485 void cpu_detect_tlb(struct cpuinfo_x86 *c)
487 if (this_cpu->c_detect_tlb)
488 this_cpu->c_detect_tlb(c);
490 printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"
491 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n"
492 "tlb_flushall_shift: %d\n",
493 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
494 tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
495 tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
496 tlb_lld_1g[ENTRIES], tlb_flushall_shift);
499 void detect_ht(struct cpuinfo_x86 *c)
502 u32 eax, ebx, ecx, edx;
503 int index_msb, core_bits;
506 if (!cpu_has(c, X86_FEATURE_HT))
509 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
512 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
515 cpuid(1, &eax, &ebx, &ecx, &edx);
517 smp_num_siblings = (ebx & 0xff0000) >> 16;
519 if (smp_num_siblings == 1) {
520 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
524 if (smp_num_siblings <= 1)
527 index_msb = get_count_order(smp_num_siblings);
528 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
530 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
532 index_msb = get_count_order(smp_num_siblings);
534 core_bits = get_count_order(c->x86_max_cores);
536 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
537 ((1 << core_bits) - 1);
540 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
541 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
543 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
550 static void get_cpu_vendor(struct cpuinfo_x86 *c)
552 char *v = c->x86_vendor_id;
555 for (i = 0; i < X86_VENDOR_NUM; i++) {
559 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
560 (cpu_devs[i]->c_ident[1] &&
561 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
563 this_cpu = cpu_devs[i];
564 c->x86_vendor = this_cpu->c_x86_vendor;
570 "CPU: vendor_id '%s' unknown, using generic init.\n" \
571 "CPU: Your system may be unstable.\n", v);
573 c->x86_vendor = X86_VENDOR_UNKNOWN;
574 this_cpu = &default_cpu;
577 void cpu_detect(struct cpuinfo_x86 *c)
579 /* Get vendor name */
580 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
581 (unsigned int *)&c->x86_vendor_id[0],
582 (unsigned int *)&c->x86_vendor_id[8],
583 (unsigned int *)&c->x86_vendor_id[4]);
586 /* Intel-defined flags: level 0x00000001 */
587 if (c->cpuid_level >= 0x00000001) {
588 u32 junk, tfms, cap0, misc;
590 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
591 c->x86 = (tfms >> 8) & 0xf;
592 c->x86_model = (tfms >> 4) & 0xf;
593 c->x86_mask = tfms & 0xf;
596 c->x86 += (tfms >> 20) & 0xff;
598 c->x86_model += ((tfms >> 16) & 0xf) << 4;
600 if (cap0 & (1<<19)) {
601 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
602 c->x86_cache_alignment = c->x86_clflush_size;
607 void get_cpu_cap(struct cpuinfo_x86 *c)
612 /* Intel-defined flags: level 0x00000001 */
613 if (c->cpuid_level >= 0x00000001) {
614 u32 capability, excap;
616 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
617 c->x86_capability[0] = capability;
618 c->x86_capability[4] = excap;
621 /* Additional Intel-defined flags: level 0x00000007 */
622 if (c->cpuid_level >= 0x00000007) {
623 u32 eax, ebx, ecx, edx;
625 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
627 c->x86_capability[9] = ebx;
630 /* AMD-defined flags: level 0x80000001 */
631 xlvl = cpuid_eax(0x80000000);
632 c->extended_cpuid_level = xlvl;
634 if ((xlvl & 0xffff0000) == 0x80000000) {
635 if (xlvl >= 0x80000001) {
636 c->x86_capability[1] = cpuid_edx(0x80000001);
637 c->x86_capability[6] = cpuid_ecx(0x80000001);
641 if (c->extended_cpuid_level >= 0x80000008) {
642 u32 eax = cpuid_eax(0x80000008);
644 c->x86_virt_bits = (eax >> 8) & 0xff;
645 c->x86_phys_bits = eax & 0xff;
648 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
649 c->x86_phys_bits = 36;
652 if (c->extended_cpuid_level >= 0x80000007)
653 c->x86_power = cpuid_edx(0x80000007);
655 init_scattered_cpuid_features(c);
658 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
664 * First of all, decide if this is a 486 or higher
665 * It's a 486 if we can modify the AC flag
667 if (flag_is_changeable_p(X86_EFLAGS_AC))
672 for (i = 0; i < X86_VENDOR_NUM; i++)
673 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
674 c->x86_vendor_id[0] = 0;
675 cpu_devs[i]->c_identify(c);
676 if (c->x86_vendor_id[0]) {
685 * Do minimum CPU detection early.
686 * Fields really needed: vendor, cpuid_level, family, model, mask,
688 * The others are not touched to avoid unwanted side effects.
690 * WARNING: this function is only called on the BP. Don't add code here
691 * that is supposed to run on all CPUs.
693 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
696 c->x86_clflush_size = 64;
697 c->x86_phys_bits = 36;
698 c->x86_virt_bits = 48;
700 c->x86_clflush_size = 32;
701 c->x86_phys_bits = 32;
702 c->x86_virt_bits = 32;
704 c->x86_cache_alignment = c->x86_clflush_size;
706 memset(&c->x86_capability, 0, sizeof c->x86_capability);
707 c->extended_cpuid_level = 0;
710 identify_cpu_without_cpuid(c);
712 /* cyrix could have cpuid enabled via c_identify()*/
721 if (this_cpu->c_early_init)
722 this_cpu->c_early_init(c);
725 filter_cpuid_features(c, false);
727 if (this_cpu->c_bsp_init)
728 this_cpu->c_bsp_init(c);
730 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
733 void __init early_cpu_init(void)
735 const struct cpu_dev *const *cdev;
738 #ifdef CONFIG_PROCESSOR_SELECT
739 printk(KERN_INFO "KERNEL supported cpus:\n");
742 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
743 const struct cpu_dev *cpudev = *cdev;
745 if (count >= X86_VENDOR_NUM)
747 cpu_devs[count] = cpudev;
750 #ifdef CONFIG_PROCESSOR_SELECT
754 for (j = 0; j < 2; j++) {
755 if (!cpudev->c_ident[j])
757 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
763 early_identify_cpu(&boot_cpu_data);
767 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
768 * unfortunately, that's not true in practice because of early VIA
769 * chips and (more importantly) broken virtualizers that are not easy
770 * to detect. In the latter case it doesn't even *fail* reliably, so
771 * probing for it doesn't even work. Disable it completely on 32-bit
772 * unless we can find a reliable way to detect all the broken cases.
773 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
775 static void detect_nopl(struct cpuinfo_x86 *c)
778 clear_cpu_cap(c, X86_FEATURE_NOPL);
780 set_cpu_cap(c, X86_FEATURE_NOPL);
784 static void generic_identify(struct cpuinfo_x86 *c)
786 c->extended_cpuid_level = 0;
789 identify_cpu_without_cpuid(c);
791 /* cyrix could have cpuid enabled via c_identify()*/
801 if (c->cpuid_level >= 0x00000001) {
802 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
804 # ifdef CONFIG_X86_HT
805 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
807 c->apicid = c->initial_apicid;
810 c->phys_proc_id = c->initial_apicid;
813 get_model_name(c); /* Default name */
819 * This does the hard work of actually picking apart the CPU stuff...
821 static void identify_cpu(struct cpuinfo_x86 *c)
825 c->loops_per_jiffy = loops_per_jiffy;
826 c->x86_cache_size = -1;
827 c->x86_vendor = X86_VENDOR_UNKNOWN;
828 c->x86_model = c->x86_mask = 0; /* So far unknown... */
829 c->x86_vendor_id[0] = '\0'; /* Unset */
830 c->x86_model_id[0] = '\0'; /* Unset */
831 c->x86_max_cores = 1;
832 c->x86_coreid_bits = 0;
834 c->x86_clflush_size = 64;
835 c->x86_phys_bits = 36;
836 c->x86_virt_bits = 48;
838 c->cpuid_level = -1; /* CPUID not detected */
839 c->x86_clflush_size = 32;
840 c->x86_phys_bits = 32;
841 c->x86_virt_bits = 32;
843 c->x86_cache_alignment = c->x86_clflush_size;
844 memset(&c->x86_capability, 0, sizeof c->x86_capability);
848 if (this_cpu->c_identify)
849 this_cpu->c_identify(c);
851 /* Clear/Set all flags overriden by options, after probe */
852 for (i = 0; i < NCAPINTS; i++) {
853 c->x86_capability[i] &= ~cpu_caps_cleared[i];
854 c->x86_capability[i] |= cpu_caps_set[i];
858 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
862 * Vendor-specific initialization. In this section we
863 * canonicalize the feature flags, meaning if there are
864 * features a certain CPU supports which CPUID doesn't
865 * tell us, CPUID claiming incorrect flags, or other bugs,
866 * we handle them here.
868 * At the end of this section, c->x86_capability better
869 * indicate the features this CPU genuinely supports!
871 if (this_cpu->c_init)
874 /* Disable the PN if appropriate */
875 squash_the_stupid_serial_number(c);
877 /* Set up SMEP/SMAP */
882 * The vendor-specific functions might have changed features.
883 * Now we do "generic changes."
886 /* Filter out anything that depends on CPUID levels we don't have */
887 filter_cpuid_features(c, true);
889 /* If the model name is still unset, do table lookup. */
890 if (!c->x86_model_id[0]) {
892 p = table_lookup_model(c);
894 strcpy(c->x86_model_id, p);
897 sprintf(c->x86_model_id, "%02x/%02x",
898 c->x86, c->x86_model);
909 * Clear/Set all flags overriden by options, need do it
910 * before following smp all cpus cap AND.
912 for (i = 0; i < NCAPINTS; i++) {
913 c->x86_capability[i] &= ~cpu_caps_cleared[i];
914 c->x86_capability[i] |= cpu_caps_set[i];
918 * On SMP, boot_cpu_data holds the common feature set between
919 * all CPUs; so make sure that we indicate which features are
920 * common between the CPUs. The first time this routine gets
921 * executed, c == &boot_cpu_data.
923 if (c != &boot_cpu_data) {
924 /* AND the already accumulated flags with these */
925 for (i = 0; i < NCAPINTS; i++)
926 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
928 /* OR, i.e. replicate the bug flags */
929 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
930 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
933 /* Init Machine Check Exception if available. */
936 select_idle_routine(c);
939 numa_add_cpu(smp_processor_id());
944 static void vgetcpu_set_mode(void)
946 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
947 vgetcpu_mode = VGETCPU_RDTSCP;
949 vgetcpu_mode = VGETCPU_LSL;
953 void __init identify_boot_cpu(void)
955 identify_cpu(&boot_cpu_data);
956 init_amd_e400_c1e_mask();
963 cpu_detect_tlb(&boot_cpu_data);
966 void identify_secondary_cpu(struct cpuinfo_x86 *c)
968 BUG_ON(c == &boot_cpu_data);
981 static const struct msr_range msr_range_array[] = {
982 { 0x00000000, 0x00000418},
983 { 0xc0000000, 0xc000040b},
984 { 0xc0010000, 0xc0010142},
985 { 0xc0011000, 0xc001103b},
988 static void __print_cpu_msr(void)
990 unsigned index_min, index_max;
995 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
996 index_min = msr_range_array[i].min;
997 index_max = msr_range_array[i].max;
999 for (index = index_min; index < index_max; index++) {
1000 if (rdmsrl_safe(index, &val))
1002 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1007 static int show_msr;
1009 static __init int setup_show_msr(char *arg)
1013 get_option(&arg, &num);
1019 __setup("show_msr=", setup_show_msr);
1021 static __init int setup_noclflush(char *arg)
1023 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1026 __setup("noclflush", setup_noclflush);
1028 void print_cpu_info(struct cpuinfo_x86 *c)
1030 const char *vendor = NULL;
1032 if (c->x86_vendor < X86_VENDOR_NUM) {
1033 vendor = this_cpu->c_vendor;
1035 if (c->cpuid_level >= 0)
1036 vendor = c->x86_vendor_id;
1039 if (vendor && !strstr(c->x86_model_id, vendor))
1040 printk(KERN_CONT "%s ", vendor);
1042 if (c->x86_model_id[0])
1043 printk(KERN_CONT "%s", strim(c->x86_model_id));
1045 printk(KERN_CONT "%d86", c->x86);
1047 printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model);
1049 if (c->x86_mask || c->cpuid_level >= 0)
1050 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask);
1052 printk(KERN_CONT ")\n");
1057 void print_cpu_msr(struct cpuinfo_x86 *c)
1059 if (c->cpu_index < show_msr)
1063 static __init int setup_disablecpuid(char *arg)
1067 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1068 setup_clear_cpu_cap(bit);
1074 __setup("clearcpuid=", setup_disablecpuid);
1076 #ifdef CONFIG_X86_64
1077 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1078 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1079 (unsigned long) debug_idt_table };
1081 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1082 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1085 * The following four percpu variables are hot. Align current_task to
1086 * cacheline size such that all four fall in the same cacheline.
1088 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1090 EXPORT_PER_CPU_SYMBOL(current_task);
1092 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1093 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1094 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1096 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1097 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1099 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1101 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1102 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1104 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1107 * Special IST stacks which the CPU switches to when it calls
1108 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1109 * limit), all of them are 4K, except the debug stack which
1112 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1113 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1114 [DEBUG_STACK - 1] = DEBUG_STKSZ
1117 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1118 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1120 /* May not be marked __init: used by software suspend */
1121 void syscall_init(void)
1124 * LSTAR and STAR live in a bit strange symbiosis.
1125 * They both write to the same internal register. STAR allows to
1126 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1128 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1129 wrmsrl(MSR_LSTAR, system_call);
1130 wrmsrl(MSR_CSTAR, ignore_sysret);
1132 #ifdef CONFIG_IA32_EMULATION
1133 syscall32_cpu_init();
1136 /* Flags to clear on syscall */
1137 wrmsrl(MSR_SYSCALL_MASK,
1138 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1139 X86_EFLAGS_IOPL|X86_EFLAGS_AC);
1143 * Copies of the original ist values from the tss are only accessed during
1144 * debugging, no special alignment required.
1146 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1148 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1149 DEFINE_PER_CPU(int, debug_stack_usage);
1151 int is_debug_stack(unsigned long addr)
1153 return __get_cpu_var(debug_stack_usage) ||
1154 (addr <= __get_cpu_var(debug_stack_addr) &&
1155 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ));
1158 DEFINE_PER_CPU(u32, debug_idt_ctr);
1160 void debug_stack_set_zero(void)
1162 this_cpu_inc(debug_idt_ctr);
1166 void debug_stack_reset(void)
1168 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1170 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1174 #else /* CONFIG_X86_64 */
1176 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1177 EXPORT_PER_CPU_SYMBOL(current_task);
1178 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1179 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1180 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1182 #ifdef CONFIG_CC_STACKPROTECTOR
1183 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1186 #endif /* CONFIG_X86_64 */
1189 * Clear all 6 debug registers:
1191 static void clear_all_debug_regs(void)
1195 for (i = 0; i < 8; i++) {
1196 /* Ignore db4, db5 */
1197 if ((i == 4) || (i == 5))
1206 * Restore debug regs if using kgdbwait and you have a kernel debugger
1207 * connection established.
1209 static void dbg_restore_debug_regs(void)
1211 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1212 arch_kgdb_ops.correct_hw_break();
1214 #else /* ! CONFIG_KGDB */
1215 #define dbg_restore_debug_regs()
1216 #endif /* ! CONFIG_KGDB */
1219 * cpu_init() initializes state that is per-CPU. Some data is already
1220 * initialized (naturally) in the bootstrap process, such as the GDT
1221 * and IDT. We reload them nevertheless, this function acts as a
1222 * 'CPU state barrier', nothing should get across.
1223 * A lot of state is already set up in PDA init for 64 bit
1225 #ifdef CONFIG_X86_64
1229 struct orig_ist *oist;
1230 struct task_struct *me;
1231 struct tss_struct *t;
1237 * Load microcode on this cpu if a valid microcode is available.
1238 * This is early microcode loading procedure.
1242 cpu = stack_smp_processor_id();
1243 t = &per_cpu(init_tss, cpu);
1244 oist = &per_cpu(orig_ist, cpu);
1247 if (this_cpu_read(numa_node) == 0 &&
1248 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1249 set_numa_node(early_cpu_to_node(cpu));
1254 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1255 panic("CPU#%d already initialized!\n", cpu);
1257 pr_debug("Initializing CPU#%d\n", cpu);
1259 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1262 * Initialize the per-CPU GDT with the boot GDT,
1263 * and set up the GDT descriptor:
1266 switch_to_new_gdt(cpu);
1271 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1274 wrmsrl(MSR_FS_BASE, 0);
1275 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1282 * set up and load the per-CPU TSS
1284 if (!oist->ist[0]) {
1285 char *estacks = per_cpu(exception_stacks, cpu);
1287 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1288 estacks += exception_stack_sizes[v];
1289 oist->ist[v] = t->x86_tss.ist[v] =
1290 (unsigned long)estacks;
1291 if (v == DEBUG_STACK-1)
1292 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1296 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1299 * <= is required because the CPU will access up to
1300 * 8 bits beyond the end of the IO permission bitmap.
1302 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1303 t->io_bitmap[i] = ~0UL;
1305 atomic_inc(&init_mm.mm_count);
1306 me->active_mm = &init_mm;
1308 enter_lazy_tlb(&init_mm, me);
1310 load_sp0(t, ¤t->thread);
1311 set_tss_desc(cpu, t);
1313 load_LDT(&init_mm.context);
1315 clear_all_debug_regs();
1316 dbg_restore_debug_regs();
1328 int cpu = smp_processor_id();
1329 struct task_struct *curr = current;
1330 struct tss_struct *t = &per_cpu(init_tss, cpu);
1331 struct thread_struct *thread = &curr->thread;
1333 show_ucode_info_early();
1335 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1336 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1341 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1343 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1344 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1347 switch_to_new_gdt(cpu);
1350 * Set up and load the per-CPU TSS and LDT
1352 atomic_inc(&init_mm.mm_count);
1353 curr->active_mm = &init_mm;
1355 enter_lazy_tlb(&init_mm, curr);
1357 load_sp0(t, thread);
1358 set_tss_desc(cpu, t);
1360 load_LDT(&init_mm.context);
1362 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1364 #ifdef CONFIG_DOUBLEFAULT
1365 /* Set up doublefault TSS pointer in the GDT */
1366 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1369 clear_all_debug_regs();
1370 dbg_restore_debug_regs();
1376 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
1377 void warn_pre_alternatives(void)
1379 WARN(1, "You're using static_cpu_has before alternatives have run!\n");
1381 EXPORT_SYMBOL_GPL(warn_pre_alternatives);
1384 inline bool __static_cpu_has_safe(u16 bit)
1386 return boot_cpu_has(bit);
1388 EXPORT_SYMBOL_GPL(__static_cpu_has_safe);