1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/mem_encrypt.h>
22 #include <linux/smp.h>
23 #include <linux/cpu.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/pgtable.h>
27 #include <linux/stackprotector.h>
28 #include <linux/utsname.h>
30 #include <asm/alternative.h>
31 #include <asm/cmdline.h>
32 #include <asm/perf_event.h>
33 #include <asm/mmu_context.h>
34 #include <asm/doublefault.h>
35 #include <asm/archrandom.h>
36 #include <asm/hypervisor.h>
37 #include <asm/processor.h>
38 #include <asm/tlbflush.h>
39 #include <asm/debugreg.h>
40 #include <asm/sections.h>
41 #include <asm/vsyscall.h>
42 #include <linux/topology.h>
43 #include <linux/cpumask.h>
44 #include <linux/atomic.h>
45 #include <asm/proto.h>
46 #include <asm/setup.h>
49 #include <asm/fpu/api.h>
51 #include <asm/hwcap2.h>
52 #include <linux/numa.h>
59 #include <asm/cacheinfo.h>
60 #include <asm/memtype.h>
61 #include <asm/microcode.h>
62 #include <asm/intel-family.h>
63 #include <asm/cpu_device_id.h>
64 #include <asm/uv/uv.h>
65 #include <asm/set_memory.h>
66 #include <asm/traps.h>
71 u32 elf_hwcap2 __read_mostly;
73 /* Number of siblings per CPU package */
74 int smp_num_siblings = 1;
75 EXPORT_SYMBOL(smp_num_siblings);
77 static struct ppin_info {
82 [X86_VENDOR_INTEL] = {
83 .feature = X86_FEATURE_INTEL_PPIN,
84 .msr_ppin_ctl = MSR_PPIN_CTL,
88 .feature = X86_FEATURE_AMD_PPIN,
89 .msr_ppin_ctl = MSR_AMD_PPIN_CTL,
90 .msr_ppin = MSR_AMD_PPIN
94 static const struct x86_cpu_id ppin_cpuids[] = {
95 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]),
96 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]),
98 /* Legacy models without CPUID enumeration */
99 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]),
100 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]),
101 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]),
102 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]),
103 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]),
104 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]),
105 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]),
106 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
107 X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
108 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]),
109 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]),
114 static void ppin_init(struct cpuinfo_x86 *c)
116 const struct x86_cpu_id *id;
117 unsigned long long val;
118 struct ppin_info *info;
120 id = x86_match_cpu(ppin_cpuids);
125 * Testing the presence of the MSR is not enough. Need to check
126 * that the PPIN_CTL allows reading of the PPIN.
128 info = (struct ppin_info *)id->driver_data;
130 if (rdmsrl_safe(info->msr_ppin_ctl, &val))
133 if ((val & 3UL) == 1UL) {
134 /* PPIN locked in disabled mode */
138 /* If PPIN is disabled, try to enable */
140 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL);
141 rdmsrl_safe(info->msr_ppin_ctl, &val);
144 /* Is the enable bit set? */
146 c->ppin = __rdmsr(info->msr_ppin);
147 set_cpu_cap(c, info->feature);
152 clear_cpu_cap(c, info->feature);
155 static void default_init(struct cpuinfo_x86 *c)
158 cpu_detect_cache_sizes(c);
160 /* Not much we can do here... */
161 /* Check if at least it has cpuid */
162 if (c->cpuid_level == -1) {
163 /* No cpuid. It must be an ancient CPU */
165 strcpy(c->x86_model_id, "486");
166 else if (c->x86 == 3)
167 strcpy(c->x86_model_id, "386");
172 static const struct cpu_dev default_cpu = {
173 .c_init = default_init,
174 .c_vendor = "Unknown",
175 .c_x86_vendor = X86_VENDOR_UNKNOWN,
178 static const struct cpu_dev *this_cpu = &default_cpu;
180 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
183 * We need valid kernel segments for data and code in long mode too
184 * IRET will check the segment types kkeil 2000/10/28
185 * Also sysret mandates a special GDT layout
187 * TLS descriptors are currently at a different place compared to i386.
188 * Hopefully nobody expects them at a fixed place (Wine?)
190 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
191 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
192 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
193 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
194 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
195 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
197 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
198 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
199 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
200 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
202 * Segments used for calling PnP BIOS have byte granularity.
203 * They code segments and data segments have fixed 64k limits,
204 * the transfer segment sizes are set at run time.
207 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
209 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
211 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
213 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
215 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
217 * The APM segments have byte granularity and their bases
218 * are set at run time. All have 64k limits.
221 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
223 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
225 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
227 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
228 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
231 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
234 static int __init x86_nopcid_setup(char *s)
236 /* nopcid doesn't accept parameters */
240 /* do not emit a message if the feature is not present */
241 if (!boot_cpu_has(X86_FEATURE_PCID))
244 setup_clear_cpu_cap(X86_FEATURE_PCID);
245 pr_info("nopcid: PCID feature disabled\n");
248 early_param("nopcid", x86_nopcid_setup);
251 static int __init x86_noinvpcid_setup(char *s)
253 /* noinvpcid doesn't accept parameters */
257 /* do not emit a message if the feature is not present */
258 if (!boot_cpu_has(X86_FEATURE_INVPCID))
261 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
262 pr_info("noinvpcid: INVPCID feature disabled\n");
265 early_param("noinvpcid", x86_noinvpcid_setup);
268 static int cachesize_override = -1;
269 static int disable_x86_serial_nr = 1;
271 static int __init cachesize_setup(char *str)
273 get_option(&str, &cachesize_override);
276 __setup("cachesize=", cachesize_setup);
278 /* Standard macro to see if a specific flag is changeable */
279 static inline int flag_is_changeable_p(u32 flag)
284 * Cyrix and IDT cpus allow disabling of CPUID
285 * so the code below may return different results
286 * when it is executed before and after enabling
287 * the CPUID. Add "volatile" to not allow gcc to
288 * optimize the subsequent calls to this function.
290 asm volatile ("pushfl \n\t"
301 : "=&r" (f1), "=&r" (f2)
304 return ((f1^f2) & flag) != 0;
307 /* Probe for the CPUID instruction */
308 int have_cpuid_p(void)
310 return flag_is_changeable_p(X86_EFLAGS_ID);
313 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
315 unsigned long lo, hi;
317 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
320 /* Disable processor serial number: */
322 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
324 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
326 pr_notice("CPU serial number disabled.\n");
327 clear_cpu_cap(c, X86_FEATURE_PN);
329 /* Disabling the serial number may affect the cpuid level */
330 c->cpuid_level = cpuid_eax(0);
333 static int __init x86_serial_nr_setup(char *s)
335 disable_x86_serial_nr = 0;
338 __setup("serialnumber", x86_serial_nr_setup);
340 static inline int flag_is_changeable_p(u32 flag)
344 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
349 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
351 if (cpu_has(c, X86_FEATURE_SMEP))
352 cr4_set_bits(X86_CR4_SMEP);
355 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
357 unsigned long eflags = native_save_fl();
359 /* This should have been cleared long ago */
360 BUG_ON(eflags & X86_EFLAGS_AC);
362 if (cpu_has(c, X86_FEATURE_SMAP))
363 cr4_set_bits(X86_CR4_SMAP);
366 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
368 /* Check the boot processor, plus build option for UMIP. */
369 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
372 /* Check the current processor's cpuid bits. */
373 if (!cpu_has(c, X86_FEATURE_UMIP))
376 cr4_set_bits(X86_CR4_UMIP);
378 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
384 * Make sure UMIP is disabled in case it was enabled in a
385 * previous boot (e.g., via kexec).
387 cr4_clear_bits(X86_CR4_UMIP);
390 /* These bits should not change their value after CPU init is finished. */
391 static const unsigned long cr4_pinned_mask =
392 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
393 X86_CR4_FSGSBASE | X86_CR4_CET;
394 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
395 static unsigned long cr4_pinned_bits __ro_after_init;
397 void native_write_cr0(unsigned long val)
399 unsigned long bits_missing = 0;
402 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
404 if (static_branch_likely(&cr_pinning)) {
405 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
406 bits_missing = X86_CR0_WP;
410 /* Warn after we've set the missing bits. */
411 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
414 EXPORT_SYMBOL(native_write_cr0);
416 void __no_profile native_write_cr4(unsigned long val)
418 unsigned long bits_changed = 0;
421 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
423 if (static_branch_likely(&cr_pinning)) {
424 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
425 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
426 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
429 /* Warn after we've corrected the changed bits. */
430 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
434 #if IS_MODULE(CONFIG_LKDTM)
435 EXPORT_SYMBOL_GPL(native_write_cr4);
438 void cr4_update_irqsoff(unsigned long set, unsigned long clear)
440 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
442 lockdep_assert_irqs_disabled();
444 newval = (cr4 & ~clear) | set;
446 this_cpu_write(cpu_tlbstate.cr4, newval);
450 EXPORT_SYMBOL(cr4_update_irqsoff);
452 /* Read the CR4 shadow. */
453 unsigned long cr4_read_shadow(void)
455 return this_cpu_read(cpu_tlbstate.cr4);
457 EXPORT_SYMBOL_GPL(cr4_read_shadow);
461 unsigned long cr4 = __read_cr4();
463 if (boot_cpu_has(X86_FEATURE_PCID))
464 cr4 |= X86_CR4_PCIDE;
465 if (static_branch_likely(&cr_pinning))
466 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
470 /* Initialize cr4 shadow for this CPU. */
471 this_cpu_write(cpu_tlbstate.cr4, cr4);
475 * Once CPU feature detection is finished (and boot params have been
476 * parsed), record any of the sensitive CR bits that are set, and
479 static void __init setup_cr_pinning(void)
481 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
482 static_key_enable(&cr_pinning.key);
485 static __init int x86_nofsgsbase_setup(char *arg)
487 /* Require an exact match without trailing characters. */
491 /* Do not emit a message if the feature is not present. */
492 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
495 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
496 pr_info("FSGSBASE disabled via kernel command line\n");
499 __setup("nofsgsbase", x86_nofsgsbase_setup);
502 * Protection Keys are not available in 32-bit mode.
504 static bool pku_disabled;
506 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
508 if (c == &boot_cpu_data) {
509 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU))
512 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
513 * bit to be set. Enforce it.
515 setup_force_cpu_cap(X86_FEATURE_OSPKE);
517 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) {
521 cr4_set_bits(X86_CR4_PKE);
522 /* Load the default PKRU value */
523 pkru_write_default();
526 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
527 static __init int setup_disable_pku(char *arg)
530 * Do not clear the X86_FEATURE_PKU bit. All of the
531 * runtime checks are against OSPKE so clearing the
534 * This way, we will see "pku" in cpuinfo, but not
535 * "ospke", which is exactly what we want. It shows
536 * that the CPU has PKU, but the OS has not enabled it.
537 * This happens to be exactly how a system would look
538 * if we disabled the config option.
540 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
544 __setup("nopku", setup_disable_pku);
547 #ifdef CONFIG_X86_KERNEL_IBT
549 __noendbr u64 ibt_save(bool disable)
553 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
554 rdmsrl(MSR_IA32_S_CET, msr);
556 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN);
562 __noendbr void ibt_restore(u64 save)
566 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
567 rdmsrl(MSR_IA32_S_CET, msr);
568 msr &= ~CET_ENDBR_EN;
569 msr |= (save & CET_ENDBR_EN);
570 wrmsrl(MSR_IA32_S_CET, msr);
576 static __always_inline void setup_cet(struct cpuinfo_x86 *c)
578 bool user_shstk, kernel_ibt;
580 if (!IS_ENABLED(CONFIG_X86_CET))
583 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT);
584 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) &&
585 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK);
587 if (!kernel_ibt && !user_shstk)
591 set_cpu_cap(c, X86_FEATURE_USER_SHSTK);
594 wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN);
596 wrmsrl(MSR_IA32_S_CET, 0);
598 cr4_set_bits(X86_CR4_CET);
600 if (kernel_ibt && ibt_selftest()) {
601 pr_err("IBT selftest: Failed!\n");
602 wrmsrl(MSR_IA32_S_CET, 0);
603 setup_clear_cpu_cap(X86_FEATURE_IBT);
607 __noendbr void cet_disable(void)
609 if (!(cpu_feature_enabled(X86_FEATURE_IBT) ||
610 cpu_feature_enabled(X86_FEATURE_SHSTK)))
613 wrmsrl(MSR_IA32_S_CET, 0);
614 wrmsrl(MSR_IA32_U_CET, 0);
618 * Some CPU features depend on higher CPUID levels, which may not always
619 * be available due to CPUID level capping or broken virtualization
620 * software. Add those features to this table to auto-disable them.
622 struct cpuid_dependent_feature {
627 static const struct cpuid_dependent_feature
628 cpuid_dependent_features[] = {
629 { X86_FEATURE_MWAIT, 0x00000005 },
630 { X86_FEATURE_DCA, 0x00000009 },
631 { X86_FEATURE_XSAVE, 0x0000000d },
635 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
637 const struct cpuid_dependent_feature *df;
639 for (df = cpuid_dependent_features; df->feature; df++) {
641 if (!cpu_has(c, df->feature))
644 * Note: cpuid_level is set to -1 if unavailable, but
645 * extended_extended_level is set to 0 if unavailable
646 * and the legitimate extended levels are all negative
647 * when signed; hence the weird messing around with
650 if (!((s32)df->level < 0 ?
651 (u32)df->level > (u32)c->extended_cpuid_level :
652 (s32)df->level > (s32)c->cpuid_level))
655 clear_cpu_cap(c, df->feature);
659 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
660 x86_cap_flag(df->feature), df->level);
665 * Naming convention should be: <Name> [(<Codename>)]
666 * This table only is used unless init_<vendor>() below doesn't set it;
667 * in particular, if CPUID levels 0x80000002..4 are supported, this
671 /* Look up CPU names by table lookup. */
672 static const char *table_lookup_model(struct cpuinfo_x86 *c)
675 const struct legacy_cpu_model_info *info;
677 if (c->x86_model >= 16)
678 return NULL; /* Range check */
683 info = this_cpu->legacy_models;
685 while (info->family) {
686 if (info->family == c->x86)
687 return info->model_names[c->x86_model];
691 return NULL; /* Not found */
694 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
695 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
696 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
699 /* The 32-bit entry code needs to find cpu_entry_area. */
700 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
703 /* Load the original GDT from the per-cpu structure */
704 void load_direct_gdt(int cpu)
706 struct desc_ptr gdt_descr;
708 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
709 gdt_descr.size = GDT_SIZE - 1;
710 load_gdt(&gdt_descr);
712 EXPORT_SYMBOL_GPL(load_direct_gdt);
714 /* Load a fixmap remapping of the per-cpu GDT */
715 void load_fixmap_gdt(int cpu)
717 struct desc_ptr gdt_descr;
719 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
720 gdt_descr.size = GDT_SIZE - 1;
721 load_gdt(&gdt_descr);
723 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
726 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base
727 * @cpu: The CPU number for which this is invoked
729 * Invoked during early boot to switch from early GDT and early per CPU to
730 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base
731 * switch is implicit by loading the direct GDT. On 64bit this requires
734 void __init switch_gdt_and_percpu_base(int cpu)
736 load_direct_gdt(cpu);
740 * No need to load %gs. It is already correct.
742 * Writing %gs on 64bit would zero GSBASE which would make any per
743 * CPU operation up to the point of the wrmsrl() fault.
745 * Set GSBASE to the new offset. Until the wrmsrl() happens the
746 * early mapping is still valid. That means the GSBASE update will
747 * lose any prior per CPU data which was not copied over in
748 * setup_per_cpu_areas().
750 * This works even with stackprotector enabled because the
751 * per CPU stack canary is 0 in both per CPU areas.
753 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
756 * %fs is already set to __KERNEL_PERCPU, but after switching GDT
757 * it is required to load FS again so that the 'hidden' part is
758 * updated from the new GDT. Up to this point the early per CPU
759 * translation is active. Any content of the early per CPU data
760 * which was not copied over in setup_per_cpu_areas() is lost.
762 loadsegment(fs, __KERNEL_PERCPU);
766 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
768 static void get_model_name(struct cpuinfo_x86 *c)
773 if (c->extended_cpuid_level < 0x80000004)
776 v = (unsigned int *)c->x86_model_id;
777 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
778 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
779 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
780 c->x86_model_id[48] = 0;
782 /* Trim whitespace */
783 p = q = s = &c->x86_model_id[0];
789 /* Note the last non-whitespace index */
799 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
801 unsigned int eax, ebx, ecx, edx;
803 c->x86_max_cores = 1;
804 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
807 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
809 c->x86_max_cores = (eax >> 26) + 1;
812 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
814 unsigned int n, dummy, ebx, ecx, edx, l2size;
816 n = c->extended_cpuid_level;
818 if (n >= 0x80000005) {
819 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
820 c->x86_cache_size = (ecx>>24) + (edx>>24);
822 /* On K8 L1 TLB is inclusive, so don't count it */
827 if (n < 0x80000006) /* Some chips just has a large L1. */
830 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
834 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
836 /* do processor-specific cache resizing */
837 if (this_cpu->legacy_cache_size)
838 l2size = this_cpu->legacy_cache_size(c, l2size);
840 /* Allow user to override all this if necessary. */
841 if (cachesize_override != -1)
842 l2size = cachesize_override;
845 return; /* Again, no L2 cache is possible */
848 c->x86_cache_size = l2size;
851 u16 __read_mostly tlb_lli_4k[NR_INFO];
852 u16 __read_mostly tlb_lli_2m[NR_INFO];
853 u16 __read_mostly tlb_lli_4m[NR_INFO];
854 u16 __read_mostly tlb_lld_4k[NR_INFO];
855 u16 __read_mostly tlb_lld_2m[NR_INFO];
856 u16 __read_mostly tlb_lld_4m[NR_INFO];
857 u16 __read_mostly tlb_lld_1g[NR_INFO];
859 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
861 if (this_cpu->c_detect_tlb)
862 this_cpu->c_detect_tlb(c);
864 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
865 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
866 tlb_lli_4m[ENTRIES]);
868 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
869 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
870 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
873 int detect_ht_early(struct cpuinfo_x86 *c)
876 u32 eax, ebx, ecx, edx;
878 if (!cpu_has(c, X86_FEATURE_HT))
881 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
884 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
887 cpuid(1, &eax, &ebx, &ecx, &edx);
889 smp_num_siblings = (ebx & 0xff0000) >> 16;
890 if (smp_num_siblings == 1)
891 pr_info_once("CPU0: Hyper-Threading is disabled\n");
896 void detect_ht(struct cpuinfo_x86 *c)
899 int index_msb, core_bits;
901 if (detect_ht_early(c) < 0)
904 index_msb = get_count_order(smp_num_siblings);
905 c->topo.pkg_id = apic->phys_pkg_id(c->topo.initial_apicid, index_msb);
907 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
909 index_msb = get_count_order(smp_num_siblings);
911 core_bits = get_count_order(c->x86_max_cores);
913 c->topo.core_id = apic->phys_pkg_id(c->topo.initial_apicid, index_msb) &
914 ((1 << core_bits) - 1);
918 static void get_cpu_vendor(struct cpuinfo_x86 *c)
920 char *v = c->x86_vendor_id;
923 for (i = 0; i < X86_VENDOR_NUM; i++) {
927 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
928 (cpu_devs[i]->c_ident[1] &&
929 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
931 this_cpu = cpu_devs[i];
932 c->x86_vendor = this_cpu->c_x86_vendor;
937 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
938 "CPU: Your system may be unstable.\n", v);
940 c->x86_vendor = X86_VENDOR_UNKNOWN;
941 this_cpu = &default_cpu;
944 void cpu_detect(struct cpuinfo_x86 *c)
946 /* Get vendor name */
947 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
948 (unsigned int *)&c->x86_vendor_id[0],
949 (unsigned int *)&c->x86_vendor_id[8],
950 (unsigned int *)&c->x86_vendor_id[4]);
953 /* Intel-defined flags: level 0x00000001 */
954 if (c->cpuid_level >= 0x00000001) {
955 u32 junk, tfms, cap0, misc;
957 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
958 c->x86 = x86_family(tfms);
959 c->x86_model = x86_model(tfms);
960 c->x86_stepping = x86_stepping(tfms);
962 if (cap0 & (1<<19)) {
963 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
964 c->x86_cache_alignment = c->x86_clflush_size;
969 static void apply_forced_caps(struct cpuinfo_x86 *c)
973 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
974 c->x86_capability[i] &= ~cpu_caps_cleared[i];
975 c->x86_capability[i] |= cpu_caps_set[i];
979 static void init_speculation_control(struct cpuinfo_x86 *c)
982 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
983 * and they also have a different bit for STIBP support. Also,
984 * a hypervisor might have set the individual AMD bits even on
985 * Intel CPUs, for finer-grained selection of what's available.
987 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
988 set_cpu_cap(c, X86_FEATURE_IBRS);
989 set_cpu_cap(c, X86_FEATURE_IBPB);
990 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
993 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
994 set_cpu_cap(c, X86_FEATURE_STIBP);
996 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
997 cpu_has(c, X86_FEATURE_VIRT_SSBD))
998 set_cpu_cap(c, X86_FEATURE_SSBD);
1000 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
1001 set_cpu_cap(c, X86_FEATURE_IBRS);
1002 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1005 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
1006 set_cpu_cap(c, X86_FEATURE_IBPB);
1008 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
1009 set_cpu_cap(c, X86_FEATURE_STIBP);
1010 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1013 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
1014 set_cpu_cap(c, X86_FEATURE_SSBD);
1015 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1016 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
1020 void get_cpu_cap(struct cpuinfo_x86 *c)
1022 u32 eax, ebx, ecx, edx;
1024 /* Intel-defined flags: level 0x00000001 */
1025 if (c->cpuid_level >= 0x00000001) {
1026 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
1028 c->x86_capability[CPUID_1_ECX] = ecx;
1029 c->x86_capability[CPUID_1_EDX] = edx;
1032 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
1033 if (c->cpuid_level >= 0x00000006)
1034 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
1036 /* Additional Intel-defined flags: level 0x00000007 */
1037 if (c->cpuid_level >= 0x00000007) {
1038 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
1039 c->x86_capability[CPUID_7_0_EBX] = ebx;
1040 c->x86_capability[CPUID_7_ECX] = ecx;
1041 c->x86_capability[CPUID_7_EDX] = edx;
1043 /* Check valid sub-leaf index before accessing it */
1045 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
1046 c->x86_capability[CPUID_7_1_EAX] = eax;
1050 /* Extended state features: level 0x0000000d */
1051 if (c->cpuid_level >= 0x0000000d) {
1052 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
1054 c->x86_capability[CPUID_D_1_EAX] = eax;
1057 /* AMD-defined flags: level 0x80000001 */
1058 eax = cpuid_eax(0x80000000);
1059 c->extended_cpuid_level = eax;
1061 if ((eax & 0xffff0000) == 0x80000000) {
1062 if (eax >= 0x80000001) {
1063 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
1065 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
1066 c->x86_capability[CPUID_8000_0001_EDX] = edx;
1070 if (c->extended_cpuid_level >= 0x80000007) {
1071 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
1073 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
1077 if (c->extended_cpuid_level >= 0x80000008) {
1078 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1079 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
1082 if (c->extended_cpuid_level >= 0x8000000a)
1083 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
1085 if (c->extended_cpuid_level >= 0x8000001f)
1086 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
1088 if (c->extended_cpuid_level >= 0x80000021)
1089 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021);
1091 init_scattered_cpuid_features(c);
1092 init_speculation_control(c);
1095 * Clear/Set all flags overridden by options, after probe.
1096 * This needs to happen each time we re-probe, which may happen
1097 * several times during CPU initialization.
1099 apply_forced_caps(c);
1102 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
1104 u32 eax, ebx, ecx, edx;
1106 if (c->extended_cpuid_level >= 0x80000008) {
1107 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1109 c->x86_virt_bits = (eax >> 8) & 0xff;
1110 c->x86_phys_bits = eax & 0xff;
1112 #ifdef CONFIG_X86_32
1113 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
1114 c->x86_phys_bits = 36;
1116 c->x86_cache_bits = c->x86_phys_bits;
1119 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
1121 #ifdef CONFIG_X86_32
1125 * First of all, decide if this is a 486 or higher
1126 * It's a 486 if we can modify the AC flag
1128 if (flag_is_changeable_p(X86_EFLAGS_AC))
1133 for (i = 0; i < X86_VENDOR_NUM; i++)
1134 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1135 c->x86_vendor_id[0] = 0;
1136 cpu_devs[i]->c_identify(c);
1137 if (c->x86_vendor_id[0]) {
1145 #define NO_SPECULATION BIT(0)
1146 #define NO_MELTDOWN BIT(1)
1147 #define NO_SSB BIT(2)
1148 #define NO_L1TF BIT(3)
1149 #define NO_MDS BIT(4)
1150 #define MSBDS_ONLY BIT(5)
1151 #define NO_SWAPGS BIT(6)
1152 #define NO_ITLB_MULTIHIT BIT(7)
1153 #define NO_SPECTRE_V2 BIT(8)
1154 #define NO_MMIO BIT(9)
1155 #define NO_EIBRS_PBRSB BIT(10)
1157 #define VULNWL(vendor, family, model, whitelist) \
1158 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1160 #define VULNWL_INTEL(model, whitelist) \
1161 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1163 #define VULNWL_AMD(family, whitelist) \
1164 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1166 #define VULNWL_HYGON(family, whitelist) \
1167 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1169 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1170 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1171 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1172 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1173 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1174 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION),
1175 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION),
1177 /* Intel Family 6 */
1178 VULNWL_INTEL(TIGERLAKE, NO_MMIO),
1179 VULNWL_INTEL(TIGERLAKE_L, NO_MMIO),
1180 VULNWL_INTEL(ALDERLAKE, NO_MMIO),
1181 VULNWL_INTEL(ALDERLAKE_L, NO_MMIO),
1183 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1184 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1185 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1186 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1187 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1189 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1190 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1191 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1192 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1193 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1194 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1196 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1198 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1199 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1201 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1202 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1203 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1206 * Technically, swapgs isn't serializing on AMD (despite it previously
1207 * being documented as such in the APM). But according to AMD, %gs is
1208 * updated non-speculatively, and the issuing of %gs-relative memory
1209 * operands will be blocked until the %gs update completes, which is
1210 * good enough for our purposes.
1213 VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB),
1214 VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB),
1215 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
1217 /* AMD Family 0xf - 0x12 */
1218 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1219 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1220 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1221 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1223 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1224 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1225 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1227 /* Zhaoxin Family 7 */
1228 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO),
1229 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO),
1233 #define VULNBL(vendor, family, model, blacklist) \
1234 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist)
1236 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1237 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1238 INTEL_FAM6_##model, steppings, \
1239 X86_FEATURE_ANY, issues)
1241 #define VULNBL_AMD(family, blacklist) \
1242 VULNBL(AMD, family, X86_MODEL_ANY, blacklist)
1244 #define VULNBL_HYGON(family, blacklist) \
1245 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist)
1247 #define SRBDS BIT(0)
1248 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */
1250 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
1251 #define MMIO_SBDS BIT(2)
1252 /* CPU is affected by RETbleed, speculating where you would not expect it */
1253 #define RETBLEED BIT(3)
1254 /* CPU is affected by SMT (cross-thread) return predictions */
1255 #define SMT_RSB BIT(4)
1256 /* CPU is affected by SRSO */
1258 /* CPU is affected by GDS */
1261 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1262 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1263 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS),
1264 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS),
1265 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS),
1266 VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO),
1267 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO),
1268 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1269 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO),
1270 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS),
1271 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1272 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1273 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1274 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1275 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1276 VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED),
1277 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1278 VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS),
1279 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS),
1280 VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1281 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED),
1282 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1283 VULNBL_INTEL_STEPPINGS(TIGERLAKE_L, X86_STEPPING_ANY, GDS),
1284 VULNBL_INTEL_STEPPINGS(TIGERLAKE, X86_STEPPING_ANY, GDS),
1285 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED),
1286 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1287 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS),
1288 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO),
1289 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS),
1291 VULNBL_AMD(0x15, RETBLEED),
1292 VULNBL_AMD(0x16, RETBLEED),
1293 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO),
1294 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB),
1295 VULNBL_AMD(0x19, SRSO),
1299 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1301 const struct x86_cpu_id *m = x86_match_cpu(table);
1303 return m && !!(m->driver_data & which);
1306 u64 x86_read_arch_cap_msr(void)
1310 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1311 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1316 static bool arch_cap_mmio_immune(u64 ia32_cap)
1318 return (ia32_cap & ARCH_CAP_FBSDP_NO &&
1319 ia32_cap & ARCH_CAP_PSDP_NO &&
1320 ia32_cap & ARCH_CAP_SBDR_SSDP_NO);
1323 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1325 u64 ia32_cap = x86_read_arch_cap_msr();
1327 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1328 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1329 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1330 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1332 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1335 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1337 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1338 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1340 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1341 !(ia32_cap & ARCH_CAP_SSB_NO) &&
1342 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1343 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1346 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature
1347 * flag and protect from vendor-specific bugs via the whitelist.
1349 if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) {
1350 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1351 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) &&
1352 !(ia32_cap & ARCH_CAP_PBRSB_NO))
1353 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB);
1356 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1357 !(ia32_cap & ARCH_CAP_MDS_NO)) {
1358 setup_force_cpu_bug(X86_BUG_MDS);
1359 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1360 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1363 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1364 setup_force_cpu_bug(X86_BUG_SWAPGS);
1367 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1368 * - TSX is supported or
1369 * - TSX_CTRL is present
1371 * TSX_CTRL check is needed for cases when TSX could be disabled before
1372 * the kernel boot e.g. kexec.
1373 * TSX_CTRL check alone is not sufficient for cases when the microcode
1374 * update is not present or running as guest that don't get TSX_CTRL.
1376 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1377 (cpu_has(c, X86_FEATURE_RTM) ||
1378 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1379 setup_force_cpu_bug(X86_BUG_TAA);
1382 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1383 * in the vulnerability blacklist.
1385 * Some of the implications and mitigation of Shared Buffers Data
1386 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
1389 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1390 cpu_has(c, X86_FEATURE_RDSEED)) &&
1391 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS))
1392 setup_force_cpu_bug(X86_BUG_SRBDS);
1395 * Processor MMIO Stale Data bug enumeration
1397 * Affected CPU list is generally enough to enumerate the vulnerability,
1398 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
1399 * not want the guest to enumerate the bug.
1401 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist,
1402 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits.
1404 if (!arch_cap_mmio_immune(ia32_cap)) {
1405 if (cpu_matches(cpu_vuln_blacklist, MMIO))
1406 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1407 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO))
1408 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN);
1411 if (!cpu_has(c, X86_FEATURE_BTC_NO)) {
1412 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA))
1413 setup_force_cpu_bug(X86_BUG_RETBLEED);
1416 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB))
1417 setup_force_cpu_bug(X86_BUG_SMT_RSB);
1419 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) {
1420 if (cpu_matches(cpu_vuln_blacklist, SRSO))
1421 setup_force_cpu_bug(X86_BUG_SRSO);
1425 * Check if CPU is vulnerable to GDS. If running in a virtual machine on
1426 * an affected processor, the VMM may have disabled the use of GATHER by
1427 * disabling AVX2. The only way to do this in HW is to clear XCR0[2],
1428 * which means that AVX will be disabled.
1430 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(ia32_cap & ARCH_CAP_GDS_NO) &&
1431 boot_cpu_has(X86_FEATURE_AVX))
1432 setup_force_cpu_bug(X86_BUG_GDS);
1434 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1437 /* Rogue Data Cache Load? No! */
1438 if (ia32_cap & ARCH_CAP_RDCL_NO)
1441 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1443 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1446 setup_force_cpu_bug(X86_BUG_L1TF);
1450 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1451 * unfortunately, that's not true in practice because of early VIA
1452 * chips and (more importantly) broken virtualizers that are not easy
1453 * to detect. In the latter case it doesn't even *fail* reliably, so
1454 * probing for it doesn't even work. Disable it completely on 32-bit
1455 * unless we can find a reliable way to detect all the broken cases.
1456 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1458 static void detect_nopl(void)
1460 #ifdef CONFIG_X86_32
1461 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1463 setup_force_cpu_cap(X86_FEATURE_NOPL);
1468 * We parse cpu parameters early because fpu__init_system() is executed
1469 * before parse_early_param().
1471 static void __init cpu_parse_early_param(void)
1474 char *argptr = arg, *opt;
1475 int arglen, taint = 0;
1477 #ifdef CONFIG_X86_32
1478 if (cmdline_find_option_bool(boot_command_line, "no387"))
1479 #ifdef CONFIG_MATH_EMULATION
1480 setup_clear_cpu_cap(X86_FEATURE_FPU);
1482 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1485 if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1486 setup_clear_cpu_cap(X86_FEATURE_FXSR);
1489 if (cmdline_find_option_bool(boot_command_line, "noxsave"))
1490 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1492 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
1493 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1495 if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
1496 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1498 if (cmdline_find_option_bool(boot_command_line, "nousershstk"))
1499 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK);
1501 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg));
1505 pr_info("Clearing CPUID bits:");
1508 bool found __maybe_unused = false;
1511 opt = strsep(&argptr, ",");
1514 * Handle naked numbers first for feature flags which don't
1517 if (!kstrtouint(opt, 10, &bit)) {
1518 if (bit < NCAPINTS * 32) {
1520 /* empty-string, i.e., ""-defined feature flags */
1521 if (!x86_cap_flags[bit])
1522 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit));
1524 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit));
1526 setup_clear_cpu_cap(bit);
1530 * The assumption is that there are no feature names with only
1531 * numbers in the name thus go to the next argument.
1536 for (bit = 0; bit < 32 * NCAPINTS; bit++) {
1537 if (!x86_cap_flag(bit))
1540 if (strcmp(x86_cap_flag(bit), opt))
1543 pr_cont(" %s", opt);
1544 setup_clear_cpu_cap(bit);
1551 pr_cont(" (unknown: %s)", opt);
1556 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1560 * Do minimum CPU detection early.
1561 * Fields really needed: vendor, cpuid_level, family, model, mask,
1563 * The others are not touched to avoid unwanted side effects.
1565 * WARNING: this function is only called on the boot CPU. Don't add code
1566 * here that is supposed to run on all CPUs.
1568 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1570 #ifdef CONFIG_X86_64
1571 c->x86_clflush_size = 64;
1572 c->x86_phys_bits = 36;
1573 c->x86_virt_bits = 48;
1575 c->x86_clflush_size = 32;
1576 c->x86_phys_bits = 32;
1577 c->x86_virt_bits = 32;
1579 c->x86_cache_alignment = c->x86_clflush_size;
1581 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1582 c->extended_cpuid_level = 0;
1584 if (!have_cpuid_p())
1585 identify_cpu_without_cpuid(c);
1587 /* cyrix could have cpuid enabled via c_identify()*/
1588 if (have_cpuid_p()) {
1592 get_cpu_address_sizes(c);
1593 setup_force_cpu_cap(X86_FEATURE_CPUID);
1594 cpu_parse_early_param();
1596 if (this_cpu->c_early_init)
1597 this_cpu->c_early_init(c);
1600 filter_cpuid_features(c, false);
1602 if (this_cpu->c_bsp_init)
1603 this_cpu->c_bsp_init(c);
1605 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1608 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1610 cpu_set_bug_bits(c);
1614 #ifdef CONFIG_X86_32
1616 * Regardless of whether PCID is enumerated, the SDM says
1617 * that it can't be enabled in 32-bit mode.
1619 setup_clear_cpu_cap(X86_FEATURE_PCID);
1623 * Later in the boot process pgtable_l5_enabled() relies on
1624 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1625 * enabled by this point we need to clear the feature bit to avoid
1626 * false-positives at the later stage.
1628 * pgtable_l5_enabled() can be false here for several reasons:
1629 * - 5-level paging is disabled compile-time;
1630 * - it's 32-bit kernel;
1631 * - machine doesn't support 5-level paging;
1632 * - user specified 'no5lvl' in kernel command line.
1634 if (!pgtable_l5_enabled())
1635 setup_clear_cpu_cap(X86_FEATURE_LA57);
1640 void __init early_cpu_init(void)
1642 const struct cpu_dev *const *cdev;
1645 #ifdef CONFIG_PROCESSOR_SELECT
1646 pr_info("KERNEL supported cpus:\n");
1649 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1650 const struct cpu_dev *cpudev = *cdev;
1652 if (count >= X86_VENDOR_NUM)
1654 cpu_devs[count] = cpudev;
1657 #ifdef CONFIG_PROCESSOR_SELECT
1661 for (j = 0; j < 2; j++) {
1662 if (!cpudev->c_ident[j])
1664 pr_info(" %s %s\n", cpudev->c_vendor,
1665 cpudev->c_ident[j]);
1670 early_identify_cpu(&boot_cpu_data);
1673 static bool detect_null_seg_behavior(void)
1676 * Empirically, writing zero to a segment selector on AMD does
1677 * not clear the base, whereas writing zero to a segment
1678 * selector on Intel does clear the base. Intel's behavior
1679 * allows slightly faster context switches in the common case
1680 * where GS is unused by the prev and next threads.
1682 * Since neither vendor documents this anywhere that I can see,
1683 * detect it directly instead of hard-coding the choice by
1686 * I've designated AMD's behavior as the "bug" because it's
1687 * counterintuitive and less friendly.
1690 unsigned long old_base, tmp;
1691 rdmsrl(MSR_FS_BASE, old_base);
1692 wrmsrl(MSR_FS_BASE, 1);
1694 rdmsrl(MSR_FS_BASE, tmp);
1695 wrmsrl(MSR_FS_BASE, old_base);
1699 void check_null_seg_clears_base(struct cpuinfo_x86 *c)
1701 /* BUG_NULL_SEG is only relevant with 64bit userspace */
1702 if (!IS_ENABLED(CONFIG_X86_64))
1705 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE))
1709 * CPUID bit above wasn't set. If this kernel is still running
1710 * as a HV guest, then the HV has decided not to advertize
1711 * that CPUID bit for whatever reason. For example, one
1712 * member of the migration pool might be vulnerable. Which
1713 * means, the bug is present: set the BUG flag and return.
1715 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1716 set_cpu_bug(c, X86_BUG_NULL_SEG);
1721 * Zen2 CPUs also have this behaviour, but no CPUID bit.
1722 * 0x18 is the respective family for Hygon.
1724 if ((c->x86 == 0x17 || c->x86 == 0x18) &&
1725 detect_null_seg_behavior())
1728 /* All the remaining ones are affected */
1729 set_cpu_bug(c, X86_BUG_NULL_SEG);
1732 static void generic_identify(struct cpuinfo_x86 *c)
1734 c->extended_cpuid_level = 0;
1736 if (!have_cpuid_p())
1737 identify_cpu_without_cpuid(c);
1739 /* cyrix could have cpuid enabled via c_identify()*/
1740 if (!have_cpuid_p())
1749 get_cpu_address_sizes(c);
1751 if (c->cpuid_level >= 0x00000001) {
1752 c->topo.initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1753 #ifdef CONFIG_X86_32
1755 c->topo.apicid = apic->phys_pkg_id(c->topo.initial_apicid, 0);
1757 c->topo.apicid = c->topo.initial_apicid;
1760 c->topo.pkg_id = c->topo.initial_apicid;
1763 get_model_name(c); /* Default name */
1766 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1767 * systems that run Linux at CPL > 0 may or may not have the
1768 * issue, but, even if they have the issue, there's absolutely
1769 * nothing we can do about it because we can't use the real IRET
1772 * NB: For the time being, only 32-bit kernels support
1773 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1774 * whether to apply espfix using paravirt hooks. If any
1775 * non-paravirt system ever shows up that does *not* have the
1776 * ESPFIX issue, we can change this.
1778 #ifdef CONFIG_X86_32
1779 set_cpu_bug(c, X86_BUG_ESPFIX);
1784 * Validate that ACPI/mptables have the same information about the
1785 * effective APIC id and update the package map.
1787 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1790 unsigned int apicid, cpu = smp_processor_id();
1792 apicid = apic->cpu_present_to_apicid(cpu);
1794 if (apicid != c->topo.apicid) {
1795 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1796 cpu, apicid, c->topo.initial_apicid);
1798 BUG_ON(topology_update_package_map(c->topo.pkg_id, cpu));
1799 BUG_ON(topology_update_die_map(c->topo.die_id, cpu));
1801 c->topo.logical_pkg_id = 0;
1806 * This does the hard work of actually picking apart the CPU stuff...
1808 static void identify_cpu(struct cpuinfo_x86 *c)
1812 c->loops_per_jiffy = loops_per_jiffy;
1813 c->x86_cache_size = 0;
1814 c->x86_vendor = X86_VENDOR_UNKNOWN;
1815 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1816 c->x86_vendor_id[0] = '\0'; /* Unset */
1817 c->x86_model_id[0] = '\0'; /* Unset */
1818 c->x86_max_cores = 1;
1819 c->x86_coreid_bits = 0;
1820 c->topo.cu_id = 0xff;
1821 c->topo.llc_id = BAD_APICID;
1822 c->topo.l2c_id = BAD_APICID;
1823 #ifdef CONFIG_X86_64
1824 c->x86_clflush_size = 64;
1825 c->x86_phys_bits = 36;
1826 c->x86_virt_bits = 48;
1828 c->cpuid_level = -1; /* CPUID not detected */
1829 c->x86_clflush_size = 32;
1830 c->x86_phys_bits = 32;
1831 c->x86_virt_bits = 32;
1833 c->x86_cache_alignment = c->x86_clflush_size;
1834 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1835 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1836 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1839 generic_identify(c);
1841 if (this_cpu->c_identify)
1842 this_cpu->c_identify(c);
1844 /* Clear/Set all flags overridden by options, after probe */
1845 apply_forced_caps(c);
1847 #ifdef CONFIG_X86_64
1848 c->topo.apicid = apic->phys_pkg_id(c->topo.initial_apicid, 0);
1852 * Vendor-specific initialization. In this section we
1853 * canonicalize the feature flags, meaning if there are
1854 * features a certain CPU supports which CPUID doesn't
1855 * tell us, CPUID claiming incorrect flags, or other bugs,
1856 * we handle them here.
1858 * At the end of this section, c->x86_capability better
1859 * indicate the features this CPU genuinely supports!
1861 if (this_cpu->c_init)
1862 this_cpu->c_init(c);
1864 /* Disable the PN if appropriate */
1865 squash_the_stupid_serial_number(c);
1867 /* Set up SMEP/SMAP/UMIP */
1872 /* Enable FSGSBASE instructions if available. */
1873 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1874 cr4_set_bits(X86_CR4_FSGSBASE);
1875 elf_hwcap2 |= HWCAP2_FSGSBASE;
1879 * The vendor-specific functions might have changed features.
1880 * Now we do "generic changes."
1883 /* Filter out anything that depends on CPUID levels we don't have */
1884 filter_cpuid_features(c, true);
1886 /* If the model name is still unset, do table lookup. */
1887 if (!c->x86_model_id[0]) {
1889 p = table_lookup_model(c);
1891 strcpy(c->x86_model_id, p);
1893 /* Last resort... */
1894 sprintf(c->x86_model_id, "%02x/%02x",
1895 c->x86, c->x86_model);
1898 #ifdef CONFIG_X86_64
1907 * Clear/Set all flags overridden by options, need do it
1908 * before following smp all cpus cap AND.
1910 apply_forced_caps(c);
1913 * On SMP, boot_cpu_data holds the common feature set between
1914 * all CPUs; so make sure that we indicate which features are
1915 * common between the CPUs. The first time this routine gets
1916 * executed, c == &boot_cpu_data.
1918 if (c != &boot_cpu_data) {
1919 /* AND the already accumulated flags with these */
1920 for (i = 0; i < NCAPINTS; i++)
1921 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1923 /* OR, i.e. replicate the bug flags */
1924 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1925 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1930 /* Init Machine Check Exception if available. */
1933 select_idle_routine(c);
1936 numa_add_cpu(smp_processor_id());
1941 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1942 * on 32-bit kernels:
1944 #ifdef CONFIG_X86_32
1945 void enable_sep_cpu(void)
1947 struct tss_struct *tss;
1950 if (!boot_cpu_has(X86_FEATURE_SEP))
1954 tss = &per_cpu(cpu_tss_rw, cpu);
1957 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1958 * see the big comment in struct x86_hw_tss's definition.
1961 tss->x86_tss.ss1 = __KERNEL_CS;
1962 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1963 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1964 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1970 static __init void identify_boot_cpu(void)
1972 identify_cpu(&boot_cpu_data);
1973 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT))
1974 pr_info("CET detected: Indirect Branch Tracking enabled\n");
1975 #ifdef CONFIG_X86_32
1978 cpu_detect_tlb(&boot_cpu_data);
1985 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1987 BUG_ON(c == &boot_cpu_data);
1989 #ifdef CONFIG_X86_32
1992 validate_apic_and_package_id(c);
1993 x86_spec_ctrl_setup_ap();
1995 if (boot_cpu_has_bug(X86_BUG_GDS))
2001 void print_cpu_info(struct cpuinfo_x86 *c)
2003 const char *vendor = NULL;
2005 if (c->x86_vendor < X86_VENDOR_NUM) {
2006 vendor = this_cpu->c_vendor;
2008 if (c->cpuid_level >= 0)
2009 vendor = c->x86_vendor_id;
2012 if (vendor && !strstr(c->x86_model_id, vendor))
2013 pr_cont("%s ", vendor);
2015 if (c->x86_model_id[0])
2016 pr_cont("%s", c->x86_model_id);
2018 pr_cont("%d86", c->x86);
2020 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
2022 if (c->x86_stepping || c->cpuid_level >= 0)
2023 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
2029 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy
2030 * function prevents it from becoming an environment variable for init.
2032 static __init int setup_clearcpuid(char *arg)
2036 __setup("clearcpuid=", setup_clearcpuid);
2038 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = {
2039 .current_task = &init_task,
2040 .preempt_count = INIT_PREEMPT_COUNT,
2041 .top_of_stack = TOP_OF_INIT_STACK,
2043 EXPORT_PER_CPU_SYMBOL(pcpu_hot);
2045 #ifdef CONFIG_X86_64
2046 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
2047 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
2048 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
2050 static void wrmsrl_cstar(unsigned long val)
2053 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
2054 * is so far ignored by the CPU, but raises a #VE trap in a TDX
2055 * guest. Avoid the pointless write on all Intel CPUs.
2057 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2058 wrmsrl(MSR_CSTAR, val);
2061 /* May not be marked __init: used by software suspend */
2062 void syscall_init(void)
2064 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
2065 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
2067 #ifdef CONFIG_IA32_EMULATION
2068 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat);
2070 * This only works on Intel CPUs.
2071 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
2072 * This does not cause SYSENTER to jump to the wrong location, because
2073 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
2075 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
2076 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
2077 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
2078 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
2080 wrmsrl_cstar((unsigned long)ignore_sysret);
2081 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
2082 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
2083 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
2087 * Flags to clear on syscall; clear as much as possible
2088 * to minimize user space-kernel interference.
2090 wrmsrl(MSR_SYSCALL_MASK,
2091 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF|
2092 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF|
2093 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF|
2094 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF|
2095 X86_EFLAGS_AC|X86_EFLAGS_ID);
2098 #else /* CONFIG_X86_64 */
2100 #ifdef CONFIG_STACKPROTECTOR
2101 DEFINE_PER_CPU(unsigned long, __stack_chk_guard);
2102 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard);
2105 #endif /* CONFIG_X86_64 */
2108 * Clear all 6 debug registers:
2110 static void clear_all_debug_regs(void)
2114 for (i = 0; i < 8; i++) {
2115 /* Ignore db4, db5 */
2116 if ((i == 4) || (i == 5))
2125 * Restore debug regs if using kgdbwait and you have a kernel debugger
2126 * connection established.
2128 static void dbg_restore_debug_regs(void)
2130 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
2131 arch_kgdb_ops.correct_hw_break();
2133 #else /* ! CONFIG_KGDB */
2134 #define dbg_restore_debug_regs()
2135 #endif /* ! CONFIG_KGDB */
2137 static inline void setup_getcpu(int cpu)
2139 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
2140 struct desc_struct d = { };
2142 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
2143 wrmsr(MSR_TSC_AUX, cpudata, 0);
2145 /* Store CPU and node number in limit. */
2147 d.limit1 = cpudata >> 16;
2149 d.type = 5; /* RO data, expand down, accessed */
2150 d.dpl = 3; /* Visible to user code */
2151 d.s = 1; /* Not a system segment */
2152 d.p = 1; /* Present */
2153 d.d = 1; /* 32-bit */
2155 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
2158 #ifdef CONFIG_X86_64
2159 static inline void ucode_cpu_init(int cpu) { }
2161 static inline void tss_setup_ist(struct tss_struct *tss)
2163 /* Set up the per-CPU TSS IST stacks */
2164 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
2165 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
2166 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
2167 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
2168 /* Only mapped when SEV-ES is active */
2169 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
2172 #else /* CONFIG_X86_64 */
2174 static inline void ucode_cpu_init(int cpu)
2176 show_ucode_info_early();
2179 static inline void tss_setup_ist(struct tss_struct *tss) { }
2181 #endif /* !CONFIG_X86_64 */
2183 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
2185 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
2187 #ifdef CONFIG_X86_IOPL_IOPERM
2188 tss->io_bitmap.prev_max = 0;
2189 tss->io_bitmap.prev_sequence = 0;
2190 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
2192 * Invalidate the extra array entry past the end of the all
2193 * permission bitmap as required by the hardware.
2195 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
2200 * Setup everything needed to handle exceptions from the IDT, including the IST
2201 * exceptions which use paranoid_entry().
2203 void cpu_init_exception_handling(void)
2205 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
2206 int cpu = raw_smp_processor_id();
2208 /* paranoid_entry() gets the CPU number from the GDT */
2211 /* IST vectors need TSS to be set up. */
2213 tss_setup_io_bitmap(tss);
2214 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
2218 /* GHCB needs to be setup to handle #VC. */
2221 /* Finally load the IDT */
2226 * cpu_init() initializes state that is per-CPU. Some data is already
2227 * initialized (naturally) in the bootstrap process, such as the GDT. We
2228 * reload it nevertheless, this function acts as a 'CPU state barrier',
2229 * nothing should get across.
2233 struct task_struct *cur = current;
2234 int cpu = raw_smp_processor_id();
2236 ucode_cpu_init(cpu);
2239 if (this_cpu_read(numa_node) == 0 &&
2240 early_cpu_to_node(cpu) != NUMA_NO_NODE)
2241 set_numa_node(early_cpu_to_node(cpu));
2243 pr_debug("Initializing CPU#%d\n", cpu);
2245 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
2246 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
2247 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
2249 if (IS_ENABLED(CONFIG_X86_64)) {
2251 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
2254 wrmsrl(MSR_FS_BASE, 0);
2255 wrmsrl(MSR_KERNEL_GS_BASE, 0);
2262 cur->active_mm = &init_mm;
2264 initialize_tlbstate_and_flush();
2265 enter_lazy_tlb(&init_mm, cur);
2268 * sp0 points to the entry trampoline stack regardless of what task
2271 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
2273 load_mm_ldt(&init_mm);
2275 clear_all_debug_regs();
2276 dbg_restore_debug_regs();
2278 doublefault_init_cpu_tss();
2283 load_fixmap_gdt(cpu);
2286 #ifdef CONFIG_MICROCODE_LATE_LOADING
2288 * store_cpu_caps() - Store a snapshot of CPU capabilities
2289 * @curr_info: Pointer where to store it
2293 void store_cpu_caps(struct cpuinfo_x86 *curr_info)
2295 /* Reload CPUID max function as it might've changed. */
2296 curr_info->cpuid_level = cpuid_eax(0);
2298 /* Copy all capability leafs and pick up the synthetic ones. */
2299 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability,
2300 sizeof(curr_info->x86_capability));
2302 /* Get the hardware CPUID leafs */
2303 get_cpu_cap(curr_info);
2307 * microcode_check() - Check if any CPU capabilities changed after an update.
2308 * @prev_info: CPU capabilities stored before an update.
2310 * The microcode loader calls this upon late microcode load to recheck features,
2311 * only when microcode has been updated. Caller holds and CPU hotplug lock.
2315 void microcode_check(struct cpuinfo_x86 *prev_info)
2317 struct cpuinfo_x86 curr_info;
2319 perf_check_microcode();
2321 amd_check_microcode();
2323 store_cpu_caps(&curr_info);
2325 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
2326 sizeof(prev_info->x86_capability)))
2329 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2330 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2335 * Invoked from core CPU hotplug code after hotplug operations
2337 void arch_smt_update(void)
2339 /* Handle the speculative execution misfeatures */
2340 cpu_bugs_smt_update();
2341 /* Check whether IPI broadcasting can be enabled */
2345 void __init arch_cpu_finalize_init(void)
2347 identify_boot_cpu();
2350 * identify_boot_cpu() initialized SMT support information, let the
2353 cpu_smt_set_num_threads(smp_num_siblings, smp_num_siblings);
2355 if (!IS_ENABLED(CONFIG_SMP)) {
2357 print_cpu_info(&boot_cpu_data);
2360 cpu_select_mitigations();
2364 if (IS_ENABLED(CONFIG_X86_32)) {
2366 * Check whether this is a real i386 which is not longer
2367 * supported and fixup the utsname.
2369 if (boot_cpu_data.x86 < 4)
2370 panic("Kernel requires i486+ for 'invlpg' and other features");
2372 init_utsname()->machine[1] =
2373 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
2377 * Must be before alternatives because it might set or clear
2383 alternative_instructions();
2385 if (IS_ENABLED(CONFIG_X86_64)) {
2387 * Make sure the first 2MB area is not mapped by huge pages
2388 * There are typically fixed size MTRRs in there and overlapping
2389 * MTRRs into large pages causes slow downs.
2391 * Right now we don't do that with gbpages because there seems
2392 * very little benefit for that case.
2394 if (!direct_gbpages)
2395 set_memory_4k((unsigned long)__va(0), 1);
2397 fpu__init_check_bugs();
2401 * This needs to be called before any devices perform DMA
2402 * operations that might use the SWIOTLB bounce buffers. It will
2403 * mark the bounce buffers as decrypted so that their usage will
2404 * not cause "plain-text" data to be decrypted when accessed. It
2405 * must be called after late_time_init() so that Hyper-V x86/x64
2406 * hypercalls work when the SWIOTLB bounce buffers are decrypted.