1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/smp.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/pgtable.h>
26 #include <asm/cmdline.h>
27 #include <asm/stackprotector.h>
28 #include <asm/perf_event.h>
29 #include <asm/mmu_context.h>
30 #include <asm/doublefault.h>
31 #include <asm/archrandom.h>
32 #include <asm/hypervisor.h>
33 #include <asm/processor.h>
34 #include <asm/tlbflush.h>
35 #include <asm/debugreg.h>
36 #include <asm/sections.h>
37 #include <asm/vsyscall.h>
38 #include <linux/topology.h>
39 #include <linux/cpumask.h>
40 #include <linux/atomic.h>
41 #include <asm/proto.h>
42 #include <asm/setup.h>
45 #include <asm/fpu/internal.h>
47 #include <asm/hwcap2.h>
48 #include <linux/numa.h>
55 #include <asm/memtype.h>
56 #include <asm/microcode.h>
57 #include <asm/microcode_intel.h>
58 #include <asm/intel-family.h>
59 #include <asm/cpu_device_id.h>
60 #include <asm/uv/uv.h>
64 u32 elf_hwcap2 __read_mostly;
66 /* all of these masks are initialized in setup_cpu_local_masks() */
67 cpumask_var_t cpu_initialized_mask;
68 cpumask_var_t cpu_callout_mask;
69 cpumask_var_t cpu_callin_mask;
71 /* representing cpus for which sibling maps can be computed */
72 cpumask_var_t cpu_sibling_setup_mask;
74 /* Number of siblings per CPU package */
75 int smp_num_siblings = 1;
76 EXPORT_SYMBOL(smp_num_siblings);
78 /* Last level cache ID of each logical CPU */
79 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
81 /* correctly size the local cpu masks */
82 void __init setup_cpu_local_masks(void)
84 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
85 alloc_bootmem_cpumask_var(&cpu_callin_mask);
86 alloc_bootmem_cpumask_var(&cpu_callout_mask);
87 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
90 static void default_init(struct cpuinfo_x86 *c)
93 cpu_detect_cache_sizes(c);
95 /* Not much we can do here... */
96 /* Check if at least it has cpuid */
97 if (c->cpuid_level == -1) {
98 /* No cpuid. It must be an ancient CPU */
100 strcpy(c->x86_model_id, "486");
101 else if (c->x86 == 3)
102 strcpy(c->x86_model_id, "386");
107 static const struct cpu_dev default_cpu = {
108 .c_init = default_init,
109 .c_vendor = "Unknown",
110 .c_x86_vendor = X86_VENDOR_UNKNOWN,
113 static const struct cpu_dev *this_cpu = &default_cpu;
115 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
118 * We need valid kernel segments for data and code in long mode too
119 * IRET will check the segment types kkeil 2000/10/28
120 * Also sysret mandates a special GDT layout
122 * TLS descriptors are currently at a different place compared to i386.
123 * Hopefully nobody expects them at a fixed place (Wine?)
125 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
126 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
127 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
129 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
130 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
132 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
133 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
134 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
135 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
137 * Segments used for calling PnP BIOS have byte granularity.
138 * They code segments and data segments have fixed 64k limits,
139 * the transfer segment sizes are set at run time.
142 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
144 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
146 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
148 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
150 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
152 * The APM segments have byte granularity and their bases
153 * are set at run time. All have 64k limits.
156 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
158 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
160 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
162 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
163 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
164 GDT_STACK_CANARY_INIT
167 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
170 static int __init x86_nopcid_setup(char *s)
172 /* nopcid doesn't accept parameters */
176 /* do not emit a message if the feature is not present */
177 if (!boot_cpu_has(X86_FEATURE_PCID))
180 setup_clear_cpu_cap(X86_FEATURE_PCID);
181 pr_info("nopcid: PCID feature disabled\n");
184 early_param("nopcid", x86_nopcid_setup);
187 static int __init x86_noinvpcid_setup(char *s)
189 /* noinvpcid doesn't accept parameters */
193 /* do not emit a message if the feature is not present */
194 if (!boot_cpu_has(X86_FEATURE_INVPCID))
197 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
198 pr_info("noinvpcid: INVPCID feature disabled\n");
201 early_param("noinvpcid", x86_noinvpcid_setup);
204 static int cachesize_override = -1;
205 static int disable_x86_serial_nr = 1;
207 static int __init cachesize_setup(char *str)
209 get_option(&str, &cachesize_override);
212 __setup("cachesize=", cachesize_setup);
214 static int __init x86_sep_setup(char *s)
216 setup_clear_cpu_cap(X86_FEATURE_SEP);
219 __setup("nosep", x86_sep_setup);
221 /* Standard macro to see if a specific flag is changeable */
222 static inline int flag_is_changeable_p(u32 flag)
227 * Cyrix and IDT cpus allow disabling of CPUID
228 * so the code below may return different results
229 * when it is executed before and after enabling
230 * the CPUID. Add "volatile" to not allow gcc to
231 * optimize the subsequent calls to this function.
233 asm volatile ("pushfl \n\t"
244 : "=&r" (f1), "=&r" (f2)
247 return ((f1^f2) & flag) != 0;
250 /* Probe for the CPUID instruction */
251 int have_cpuid_p(void)
253 return flag_is_changeable_p(X86_EFLAGS_ID);
256 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
258 unsigned long lo, hi;
260 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
263 /* Disable processor serial number: */
265 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
267 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
269 pr_notice("CPU serial number disabled.\n");
270 clear_cpu_cap(c, X86_FEATURE_PN);
272 /* Disabling the serial number may affect the cpuid level */
273 c->cpuid_level = cpuid_eax(0);
276 static int __init x86_serial_nr_setup(char *s)
278 disable_x86_serial_nr = 0;
281 __setup("serialnumber", x86_serial_nr_setup);
283 static inline int flag_is_changeable_p(u32 flag)
287 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
292 static __init int setup_disable_smep(char *arg)
294 setup_clear_cpu_cap(X86_FEATURE_SMEP);
297 __setup("nosmep", setup_disable_smep);
299 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
301 if (cpu_has(c, X86_FEATURE_SMEP))
302 cr4_set_bits(X86_CR4_SMEP);
305 static __init int setup_disable_smap(char *arg)
307 setup_clear_cpu_cap(X86_FEATURE_SMAP);
310 __setup("nosmap", setup_disable_smap);
312 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
314 unsigned long eflags = native_save_fl();
316 /* This should have been cleared long ago */
317 BUG_ON(eflags & X86_EFLAGS_AC);
319 if (cpu_has(c, X86_FEATURE_SMAP)) {
320 #ifdef CONFIG_X86_SMAP
321 cr4_set_bits(X86_CR4_SMAP);
323 cr4_clear_bits(X86_CR4_SMAP);
328 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
330 /* Check the boot processor, plus build option for UMIP. */
331 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
334 /* Check the current processor's cpuid bits. */
335 if (!cpu_has(c, X86_FEATURE_UMIP))
338 cr4_set_bits(X86_CR4_UMIP);
340 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
346 * Make sure UMIP is disabled in case it was enabled in a
347 * previous boot (e.g., via kexec).
349 cr4_clear_bits(X86_CR4_UMIP);
352 /* These bits should not change their value after CPU init is finished. */
353 static const unsigned long cr4_pinned_mask =
354 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | X86_CR4_FSGSBASE;
355 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
356 static unsigned long cr4_pinned_bits __ro_after_init;
358 void native_write_cr0(unsigned long val)
360 unsigned long bits_missing = 0;
363 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
365 if (static_branch_likely(&cr_pinning)) {
366 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
367 bits_missing = X86_CR0_WP;
371 /* Warn after we've set the missing bits. */
372 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
375 EXPORT_SYMBOL(native_write_cr0);
377 void native_write_cr4(unsigned long val)
379 unsigned long bits_changed = 0;
382 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
384 if (static_branch_likely(&cr_pinning)) {
385 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
386 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
387 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
390 /* Warn after we've corrected the changed bits. */
391 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
395 #if IS_MODULE(CONFIG_LKDTM)
396 EXPORT_SYMBOL_GPL(native_write_cr4);
399 void cr4_update_irqsoff(unsigned long set, unsigned long clear)
401 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
403 lockdep_assert_irqs_disabled();
405 newval = (cr4 & ~clear) | set;
407 this_cpu_write(cpu_tlbstate.cr4, newval);
411 EXPORT_SYMBOL(cr4_update_irqsoff);
413 /* Read the CR4 shadow. */
414 unsigned long cr4_read_shadow(void)
416 return this_cpu_read(cpu_tlbstate.cr4);
418 EXPORT_SYMBOL_GPL(cr4_read_shadow);
422 unsigned long cr4 = __read_cr4();
424 if (boot_cpu_has(X86_FEATURE_PCID))
425 cr4 |= X86_CR4_PCIDE;
426 if (static_branch_likely(&cr_pinning))
427 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
431 /* Initialize cr4 shadow for this CPU. */
432 this_cpu_write(cpu_tlbstate.cr4, cr4);
436 * Once CPU feature detection is finished (and boot params have been
437 * parsed), record any of the sensitive CR bits that are set, and
440 static void __init setup_cr_pinning(void)
442 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
443 static_key_enable(&cr_pinning.key);
446 static __init int x86_nofsgsbase_setup(char *arg)
448 /* Require an exact match without trailing characters. */
452 /* Do not emit a message if the feature is not present. */
453 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
456 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
457 pr_info("FSGSBASE disabled via kernel command line\n");
460 __setup("nofsgsbase", x86_nofsgsbase_setup);
463 * Protection Keys are not available in 32-bit mode.
465 static bool pku_disabled;
467 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
469 struct pkru_state *pk;
471 /* check the boot processor, plus compile options for PKU: */
472 if (!cpu_feature_enabled(X86_FEATURE_PKU))
474 /* checks the actual processor's cpuid bits: */
475 if (!cpu_has(c, X86_FEATURE_PKU))
480 cr4_set_bits(X86_CR4_PKE);
481 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU);
483 pk->pkru = init_pkru_value;
485 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
486 * cpuid bit to be set. We need to ensure that we
487 * update that bit in this CPU's "cpu_info".
489 set_cpu_cap(c, X86_FEATURE_OSPKE);
492 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
493 static __init int setup_disable_pku(char *arg)
496 * Do not clear the X86_FEATURE_PKU bit. All of the
497 * runtime checks are against OSPKE so clearing the
500 * This way, we will see "pku" in cpuinfo, but not
501 * "ospke", which is exactly what we want. It shows
502 * that the CPU has PKU, but the OS has not enabled it.
503 * This happens to be exactly how a system would look
504 * if we disabled the config option.
506 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
510 __setup("nopku", setup_disable_pku);
511 #endif /* CONFIG_X86_64 */
514 * Some CPU features depend on higher CPUID levels, which may not always
515 * be available due to CPUID level capping or broken virtualization
516 * software. Add those features to this table to auto-disable them.
518 struct cpuid_dependent_feature {
523 static const struct cpuid_dependent_feature
524 cpuid_dependent_features[] = {
525 { X86_FEATURE_MWAIT, 0x00000005 },
526 { X86_FEATURE_DCA, 0x00000009 },
527 { X86_FEATURE_XSAVE, 0x0000000d },
531 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
533 const struct cpuid_dependent_feature *df;
535 for (df = cpuid_dependent_features; df->feature; df++) {
537 if (!cpu_has(c, df->feature))
540 * Note: cpuid_level is set to -1 if unavailable, but
541 * extended_extended_level is set to 0 if unavailable
542 * and the legitimate extended levels are all negative
543 * when signed; hence the weird messing around with
546 if (!((s32)df->level < 0 ?
547 (u32)df->level > (u32)c->extended_cpuid_level :
548 (s32)df->level > (s32)c->cpuid_level))
551 clear_cpu_cap(c, df->feature);
555 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
556 x86_cap_flag(df->feature), df->level);
561 * Naming convention should be: <Name> [(<Codename>)]
562 * This table only is used unless init_<vendor>() below doesn't set it;
563 * in particular, if CPUID levels 0x80000002..4 are supported, this
567 /* Look up CPU names by table lookup. */
568 static const char *table_lookup_model(struct cpuinfo_x86 *c)
571 const struct legacy_cpu_model_info *info;
573 if (c->x86_model >= 16)
574 return NULL; /* Range check */
579 info = this_cpu->legacy_models;
581 while (info->family) {
582 if (info->family == c->x86)
583 return info->model_names[c->x86_model];
587 return NULL; /* Not found */
590 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
591 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
592 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
594 void load_percpu_segment(int cpu)
597 loadsegment(fs, __KERNEL_PERCPU);
599 __loadsegment_simple(gs, 0);
600 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
602 load_stack_canary_segment();
606 /* The 32-bit entry code needs to find cpu_entry_area. */
607 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
610 /* Load the original GDT from the per-cpu structure */
611 void load_direct_gdt(int cpu)
613 struct desc_ptr gdt_descr;
615 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
616 gdt_descr.size = GDT_SIZE - 1;
617 load_gdt(&gdt_descr);
619 EXPORT_SYMBOL_GPL(load_direct_gdt);
621 /* Load a fixmap remapping of the per-cpu GDT */
622 void load_fixmap_gdt(int cpu)
624 struct desc_ptr gdt_descr;
626 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
627 gdt_descr.size = GDT_SIZE - 1;
628 load_gdt(&gdt_descr);
630 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
633 * Current gdt points %fs at the "master" per-cpu area: after this,
634 * it's on the real one.
636 void switch_to_new_gdt(int cpu)
638 /* Load the original GDT */
639 load_direct_gdt(cpu);
640 /* Reload the per-cpu base */
641 load_percpu_segment(cpu);
644 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
646 static void get_model_name(struct cpuinfo_x86 *c)
651 if (c->extended_cpuid_level < 0x80000004)
654 v = (unsigned int *)c->x86_model_id;
655 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
656 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
657 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
658 c->x86_model_id[48] = 0;
660 /* Trim whitespace */
661 p = q = s = &c->x86_model_id[0];
667 /* Note the last non-whitespace index */
677 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
679 unsigned int eax, ebx, ecx, edx;
681 c->x86_max_cores = 1;
682 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
685 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
687 c->x86_max_cores = (eax >> 26) + 1;
690 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
692 unsigned int n, dummy, ebx, ecx, edx, l2size;
694 n = c->extended_cpuid_level;
696 if (n >= 0x80000005) {
697 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
698 c->x86_cache_size = (ecx>>24) + (edx>>24);
700 /* On K8 L1 TLB is inclusive, so don't count it */
705 if (n < 0x80000006) /* Some chips just has a large L1. */
708 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
712 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
714 /* do processor-specific cache resizing */
715 if (this_cpu->legacy_cache_size)
716 l2size = this_cpu->legacy_cache_size(c, l2size);
718 /* Allow user to override all this if necessary. */
719 if (cachesize_override != -1)
720 l2size = cachesize_override;
723 return; /* Again, no L2 cache is possible */
726 c->x86_cache_size = l2size;
729 u16 __read_mostly tlb_lli_4k[NR_INFO];
730 u16 __read_mostly tlb_lli_2m[NR_INFO];
731 u16 __read_mostly tlb_lli_4m[NR_INFO];
732 u16 __read_mostly tlb_lld_4k[NR_INFO];
733 u16 __read_mostly tlb_lld_2m[NR_INFO];
734 u16 __read_mostly tlb_lld_4m[NR_INFO];
735 u16 __read_mostly tlb_lld_1g[NR_INFO];
737 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
739 if (this_cpu->c_detect_tlb)
740 this_cpu->c_detect_tlb(c);
742 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
743 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
744 tlb_lli_4m[ENTRIES]);
746 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
747 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
748 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
751 int detect_ht_early(struct cpuinfo_x86 *c)
754 u32 eax, ebx, ecx, edx;
756 if (!cpu_has(c, X86_FEATURE_HT))
759 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
762 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
765 cpuid(1, &eax, &ebx, &ecx, &edx);
767 smp_num_siblings = (ebx & 0xff0000) >> 16;
768 if (smp_num_siblings == 1)
769 pr_info_once("CPU0: Hyper-Threading is disabled\n");
774 void detect_ht(struct cpuinfo_x86 *c)
777 int index_msb, core_bits;
779 if (detect_ht_early(c) < 0)
782 index_msb = get_count_order(smp_num_siblings);
783 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
785 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
787 index_msb = get_count_order(smp_num_siblings);
789 core_bits = get_count_order(c->x86_max_cores);
791 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
792 ((1 << core_bits) - 1);
796 static void get_cpu_vendor(struct cpuinfo_x86 *c)
798 char *v = c->x86_vendor_id;
801 for (i = 0; i < X86_VENDOR_NUM; i++) {
805 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
806 (cpu_devs[i]->c_ident[1] &&
807 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
809 this_cpu = cpu_devs[i];
810 c->x86_vendor = this_cpu->c_x86_vendor;
815 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
816 "CPU: Your system may be unstable.\n", v);
818 c->x86_vendor = X86_VENDOR_UNKNOWN;
819 this_cpu = &default_cpu;
822 void cpu_detect(struct cpuinfo_x86 *c)
824 /* Get vendor name */
825 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
826 (unsigned int *)&c->x86_vendor_id[0],
827 (unsigned int *)&c->x86_vendor_id[8],
828 (unsigned int *)&c->x86_vendor_id[4]);
831 /* Intel-defined flags: level 0x00000001 */
832 if (c->cpuid_level >= 0x00000001) {
833 u32 junk, tfms, cap0, misc;
835 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
836 c->x86 = x86_family(tfms);
837 c->x86_model = x86_model(tfms);
838 c->x86_stepping = x86_stepping(tfms);
840 if (cap0 & (1<<19)) {
841 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
842 c->x86_cache_alignment = c->x86_clflush_size;
847 static void apply_forced_caps(struct cpuinfo_x86 *c)
851 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
852 c->x86_capability[i] &= ~cpu_caps_cleared[i];
853 c->x86_capability[i] |= cpu_caps_set[i];
857 static void init_speculation_control(struct cpuinfo_x86 *c)
860 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
861 * and they also have a different bit for STIBP support. Also,
862 * a hypervisor might have set the individual AMD bits even on
863 * Intel CPUs, for finer-grained selection of what's available.
865 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
866 set_cpu_cap(c, X86_FEATURE_IBRS);
867 set_cpu_cap(c, X86_FEATURE_IBPB);
868 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
871 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
872 set_cpu_cap(c, X86_FEATURE_STIBP);
874 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
875 cpu_has(c, X86_FEATURE_VIRT_SSBD))
876 set_cpu_cap(c, X86_FEATURE_SSBD);
878 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
879 set_cpu_cap(c, X86_FEATURE_IBRS);
880 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
883 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
884 set_cpu_cap(c, X86_FEATURE_IBPB);
886 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
887 set_cpu_cap(c, X86_FEATURE_STIBP);
888 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
891 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
892 set_cpu_cap(c, X86_FEATURE_SSBD);
893 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
894 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
898 void get_cpu_cap(struct cpuinfo_x86 *c)
900 u32 eax, ebx, ecx, edx;
902 /* Intel-defined flags: level 0x00000001 */
903 if (c->cpuid_level >= 0x00000001) {
904 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
906 c->x86_capability[CPUID_1_ECX] = ecx;
907 c->x86_capability[CPUID_1_EDX] = edx;
910 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
911 if (c->cpuid_level >= 0x00000006)
912 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
914 /* Additional Intel-defined flags: level 0x00000007 */
915 if (c->cpuid_level >= 0x00000007) {
916 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
917 c->x86_capability[CPUID_7_0_EBX] = ebx;
918 c->x86_capability[CPUID_7_ECX] = ecx;
919 c->x86_capability[CPUID_7_EDX] = edx;
921 /* Check valid sub-leaf index before accessing it */
923 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
924 c->x86_capability[CPUID_7_1_EAX] = eax;
928 /* Extended state features: level 0x0000000d */
929 if (c->cpuid_level >= 0x0000000d) {
930 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
932 c->x86_capability[CPUID_D_1_EAX] = eax;
935 /* AMD-defined flags: level 0x80000001 */
936 eax = cpuid_eax(0x80000000);
937 c->extended_cpuid_level = eax;
939 if ((eax & 0xffff0000) == 0x80000000) {
940 if (eax >= 0x80000001) {
941 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
943 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
944 c->x86_capability[CPUID_8000_0001_EDX] = edx;
948 if (c->extended_cpuid_level >= 0x80000007) {
949 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
951 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
955 if (c->extended_cpuid_level >= 0x80000008) {
956 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
957 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
960 if (c->extended_cpuid_level >= 0x8000000a)
961 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
963 init_scattered_cpuid_features(c);
964 init_speculation_control(c);
967 * Clear/Set all flags overridden by options, after probe.
968 * This needs to happen each time we re-probe, which may happen
969 * several times during CPU initialization.
971 apply_forced_caps(c);
974 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
976 u32 eax, ebx, ecx, edx;
978 if (c->extended_cpuid_level >= 0x80000008) {
979 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
981 c->x86_virt_bits = (eax >> 8) & 0xff;
982 c->x86_phys_bits = eax & 0xff;
985 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
986 c->x86_phys_bits = 36;
988 c->x86_cache_bits = c->x86_phys_bits;
991 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
997 * First of all, decide if this is a 486 or higher
998 * It's a 486 if we can modify the AC flag
1000 if (flag_is_changeable_p(X86_EFLAGS_AC))
1005 for (i = 0; i < X86_VENDOR_NUM; i++)
1006 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1007 c->x86_vendor_id[0] = 0;
1008 cpu_devs[i]->c_identify(c);
1009 if (c->x86_vendor_id[0]) {
1017 #define NO_SPECULATION BIT(0)
1018 #define NO_MELTDOWN BIT(1)
1019 #define NO_SSB BIT(2)
1020 #define NO_L1TF BIT(3)
1021 #define NO_MDS BIT(4)
1022 #define MSBDS_ONLY BIT(5)
1023 #define NO_SWAPGS BIT(6)
1024 #define NO_ITLB_MULTIHIT BIT(7)
1025 #define NO_SPECTRE_V2 BIT(8)
1027 #define VULNWL(vendor, family, model, whitelist) \
1028 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1030 #define VULNWL_INTEL(model, whitelist) \
1031 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1033 #define VULNWL_AMD(family, whitelist) \
1034 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1036 #define VULNWL_HYGON(family, whitelist) \
1037 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1039 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1040 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1041 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1042 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1043 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1045 /* Intel Family 6 */
1046 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1047 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1048 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1049 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1050 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1052 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1053 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1054 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1055 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1056 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1057 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1059 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1061 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1062 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1064 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1065 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1066 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1069 * Technically, swapgs isn't serializing on AMD (despite it previously
1070 * being documented as such in the APM). But according to AMD, %gs is
1071 * updated non-speculatively, and the issuing of %gs-relative memory
1072 * operands will be blocked until the %gs update completes, which is
1073 * good enough for our purposes.
1076 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT),
1078 /* AMD Family 0xf - 0x12 */
1079 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1080 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1081 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1082 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1084 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1085 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1086 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1088 /* Zhaoxin Family 7 */
1089 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1090 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1094 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1095 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1096 INTEL_FAM6_##model, steppings, \
1097 X86_FEATURE_ANY, issues)
1099 #define SRBDS BIT(0)
1101 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1102 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1103 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS),
1104 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS),
1105 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS),
1106 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1107 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS),
1108 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS),
1109 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS),
1110 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS),
1111 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS),
1115 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1117 const struct x86_cpu_id *m = x86_match_cpu(table);
1119 return m && !!(m->driver_data & which);
1122 u64 x86_read_arch_cap_msr(void)
1126 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1127 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1132 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1134 u64 ia32_cap = x86_read_arch_cap_msr();
1136 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1137 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1138 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1139 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1141 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1144 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1146 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1147 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1149 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1150 !(ia32_cap & ARCH_CAP_SSB_NO) &&
1151 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1152 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1154 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1155 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1157 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1158 !(ia32_cap & ARCH_CAP_MDS_NO)) {
1159 setup_force_cpu_bug(X86_BUG_MDS);
1160 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1161 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1164 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1165 setup_force_cpu_bug(X86_BUG_SWAPGS);
1168 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1169 * - TSX is supported or
1170 * - TSX_CTRL is present
1172 * TSX_CTRL check is needed for cases when TSX could be disabled before
1173 * the kernel boot e.g. kexec.
1174 * TSX_CTRL check alone is not sufficient for cases when the microcode
1175 * update is not present or running as guest that don't get TSX_CTRL.
1177 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1178 (cpu_has(c, X86_FEATURE_RTM) ||
1179 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1180 setup_force_cpu_bug(X86_BUG_TAA);
1183 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1184 * in the vulnerability blacklist.
1186 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1187 cpu_has(c, X86_FEATURE_RDSEED)) &&
1188 cpu_matches(cpu_vuln_blacklist, SRBDS))
1189 setup_force_cpu_bug(X86_BUG_SRBDS);
1191 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1194 /* Rogue Data Cache Load? No! */
1195 if (ia32_cap & ARCH_CAP_RDCL_NO)
1198 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1200 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1203 setup_force_cpu_bug(X86_BUG_L1TF);
1207 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1208 * unfortunately, that's not true in practice because of early VIA
1209 * chips and (more importantly) broken virtualizers that are not easy
1210 * to detect. In the latter case it doesn't even *fail* reliably, so
1211 * probing for it doesn't even work. Disable it completely on 32-bit
1212 * unless we can find a reliable way to detect all the broken cases.
1213 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1215 static void detect_nopl(void)
1217 #ifdef CONFIG_X86_32
1218 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1220 setup_force_cpu_cap(X86_FEATURE_NOPL);
1225 * We parse cpu parameters early because fpu__init_system() is executed
1226 * before parse_early_param().
1228 static void __init cpu_parse_early_param(void)
1232 int arglen, res, bit;
1234 #ifdef CONFIG_X86_32
1235 if (cmdline_find_option_bool(boot_command_line, "no387"))
1236 #ifdef CONFIG_MATH_EMULATION
1237 setup_clear_cpu_cap(X86_FEATURE_FPU);
1239 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1242 if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1243 setup_clear_cpu_cap(X86_FEATURE_FXSR);
1246 if (cmdline_find_option_bool(boot_command_line, "noxsave"))
1247 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1249 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
1250 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1252 if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
1253 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1255 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg));
1259 pr_info("Clearing CPUID bits:");
1261 res = get_option(&argptr, &bit);
1262 if (res == 0 || res == 3)
1265 /* If the argument was too long, the last bit may be cut off */
1266 if (res == 1 && arglen >= sizeof(arg))
1269 if (bit >= 0 && bit < NCAPINTS * 32) {
1270 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit));
1271 setup_clear_cpu_cap(bit);
1278 * Do minimum CPU detection early.
1279 * Fields really needed: vendor, cpuid_level, family, model, mask,
1281 * The others are not touched to avoid unwanted side effects.
1283 * WARNING: this function is only called on the boot CPU. Don't add code
1284 * here that is supposed to run on all CPUs.
1286 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1288 #ifdef CONFIG_X86_64
1289 c->x86_clflush_size = 64;
1290 c->x86_phys_bits = 36;
1291 c->x86_virt_bits = 48;
1293 c->x86_clflush_size = 32;
1294 c->x86_phys_bits = 32;
1295 c->x86_virt_bits = 32;
1297 c->x86_cache_alignment = c->x86_clflush_size;
1299 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1300 c->extended_cpuid_level = 0;
1302 if (!have_cpuid_p())
1303 identify_cpu_without_cpuid(c);
1305 /* cyrix could have cpuid enabled via c_identify()*/
1306 if (have_cpuid_p()) {
1310 get_cpu_address_sizes(c);
1311 setup_force_cpu_cap(X86_FEATURE_CPUID);
1312 cpu_parse_early_param();
1314 if (this_cpu->c_early_init)
1315 this_cpu->c_early_init(c);
1318 filter_cpuid_features(c, false);
1320 if (this_cpu->c_bsp_init)
1321 this_cpu->c_bsp_init(c);
1323 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1326 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1328 cpu_set_bug_bits(c);
1330 cpu_set_core_cap_bits(c);
1332 fpu__init_system(c);
1334 #ifdef CONFIG_X86_32
1336 * Regardless of whether PCID is enumerated, the SDM says
1337 * that it can't be enabled in 32-bit mode.
1339 setup_clear_cpu_cap(X86_FEATURE_PCID);
1343 * Later in the boot process pgtable_l5_enabled() relies on
1344 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1345 * enabled by this point we need to clear the feature bit to avoid
1346 * false-positives at the later stage.
1348 * pgtable_l5_enabled() can be false here for several reasons:
1349 * - 5-level paging is disabled compile-time;
1350 * - it's 32-bit kernel;
1351 * - machine doesn't support 5-level paging;
1352 * - user specified 'no5lvl' in kernel command line.
1354 if (!pgtable_l5_enabled())
1355 setup_clear_cpu_cap(X86_FEATURE_LA57);
1360 void __init early_cpu_init(void)
1362 const struct cpu_dev *const *cdev;
1365 #ifdef CONFIG_PROCESSOR_SELECT
1366 pr_info("KERNEL supported cpus:\n");
1369 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1370 const struct cpu_dev *cpudev = *cdev;
1372 if (count >= X86_VENDOR_NUM)
1374 cpu_devs[count] = cpudev;
1377 #ifdef CONFIG_PROCESSOR_SELECT
1381 for (j = 0; j < 2; j++) {
1382 if (!cpudev->c_ident[j])
1384 pr_info(" %s %s\n", cpudev->c_vendor,
1385 cpudev->c_ident[j]);
1390 early_identify_cpu(&boot_cpu_data);
1393 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1395 #ifdef CONFIG_X86_64
1397 * Empirically, writing zero to a segment selector on AMD does
1398 * not clear the base, whereas writing zero to a segment
1399 * selector on Intel does clear the base. Intel's behavior
1400 * allows slightly faster context switches in the common case
1401 * where GS is unused by the prev and next threads.
1403 * Since neither vendor documents this anywhere that I can see,
1404 * detect it directly instead of hardcoding the choice by
1407 * I've designated AMD's behavior as the "bug" because it's
1408 * counterintuitive and less friendly.
1411 unsigned long old_base, tmp;
1412 rdmsrl(MSR_FS_BASE, old_base);
1413 wrmsrl(MSR_FS_BASE, 1);
1415 rdmsrl(MSR_FS_BASE, tmp);
1417 set_cpu_bug(c, X86_BUG_NULL_SEG);
1418 wrmsrl(MSR_FS_BASE, old_base);
1422 static void generic_identify(struct cpuinfo_x86 *c)
1424 c->extended_cpuid_level = 0;
1426 if (!have_cpuid_p())
1427 identify_cpu_without_cpuid(c);
1429 /* cyrix could have cpuid enabled via c_identify()*/
1430 if (!have_cpuid_p())
1439 get_cpu_address_sizes(c);
1441 if (c->cpuid_level >= 0x00000001) {
1442 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1443 #ifdef CONFIG_X86_32
1445 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1447 c->apicid = c->initial_apicid;
1450 c->phys_proc_id = c->initial_apicid;
1453 get_model_name(c); /* Default name */
1455 detect_null_seg_behavior(c);
1458 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1459 * systems that run Linux at CPL > 0 may or may not have the
1460 * issue, but, even if they have the issue, there's absolutely
1461 * nothing we can do about it because we can't use the real IRET
1464 * NB: For the time being, only 32-bit kernels support
1465 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1466 * whether to apply espfix using paravirt hooks. If any
1467 * non-paravirt system ever shows up that does *not* have the
1468 * ESPFIX issue, we can change this.
1470 #ifdef CONFIG_X86_32
1471 set_cpu_bug(c, X86_BUG_ESPFIX);
1476 * Validate that ACPI/mptables have the same information about the
1477 * effective APIC id and update the package map.
1479 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1482 unsigned int apicid, cpu = smp_processor_id();
1484 apicid = apic->cpu_present_to_apicid(cpu);
1486 if (apicid != c->apicid) {
1487 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1488 cpu, apicid, c->initial_apicid);
1490 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1491 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu));
1493 c->logical_proc_id = 0;
1498 * This does the hard work of actually picking apart the CPU stuff...
1500 static void identify_cpu(struct cpuinfo_x86 *c)
1504 c->loops_per_jiffy = loops_per_jiffy;
1505 c->x86_cache_size = 0;
1506 c->x86_vendor = X86_VENDOR_UNKNOWN;
1507 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1508 c->x86_vendor_id[0] = '\0'; /* Unset */
1509 c->x86_model_id[0] = '\0'; /* Unset */
1510 c->x86_max_cores = 1;
1511 c->x86_coreid_bits = 0;
1513 #ifdef CONFIG_X86_64
1514 c->x86_clflush_size = 64;
1515 c->x86_phys_bits = 36;
1516 c->x86_virt_bits = 48;
1518 c->cpuid_level = -1; /* CPUID not detected */
1519 c->x86_clflush_size = 32;
1520 c->x86_phys_bits = 32;
1521 c->x86_virt_bits = 32;
1523 c->x86_cache_alignment = c->x86_clflush_size;
1524 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1525 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1526 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1529 generic_identify(c);
1531 if (this_cpu->c_identify)
1532 this_cpu->c_identify(c);
1534 /* Clear/Set all flags overridden by options, after probe */
1535 apply_forced_caps(c);
1537 #ifdef CONFIG_X86_64
1538 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1542 * Vendor-specific initialization. In this section we
1543 * canonicalize the feature flags, meaning if there are
1544 * features a certain CPU supports which CPUID doesn't
1545 * tell us, CPUID claiming incorrect flags, or other bugs,
1546 * we handle them here.
1548 * At the end of this section, c->x86_capability better
1549 * indicate the features this CPU genuinely supports!
1551 if (this_cpu->c_init)
1552 this_cpu->c_init(c);
1554 /* Disable the PN if appropriate */
1555 squash_the_stupid_serial_number(c);
1557 /* Set up SMEP/SMAP/UMIP */
1562 /* Enable FSGSBASE instructions if available. */
1563 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1564 cr4_set_bits(X86_CR4_FSGSBASE);
1565 elf_hwcap2 |= HWCAP2_FSGSBASE;
1569 * The vendor-specific functions might have changed features.
1570 * Now we do "generic changes."
1573 /* Filter out anything that depends on CPUID levels we don't have */
1574 filter_cpuid_features(c, true);
1576 /* If the model name is still unset, do table lookup. */
1577 if (!c->x86_model_id[0]) {
1579 p = table_lookup_model(c);
1581 strcpy(c->x86_model_id, p);
1583 /* Last resort... */
1584 sprintf(c->x86_model_id, "%02x/%02x",
1585 c->x86, c->x86_model);
1588 #ifdef CONFIG_X86_64
1596 * Clear/Set all flags overridden by options, need do it
1597 * before following smp all cpus cap AND.
1599 apply_forced_caps(c);
1602 * On SMP, boot_cpu_data holds the common feature set between
1603 * all CPUs; so make sure that we indicate which features are
1604 * common between the CPUs. The first time this routine gets
1605 * executed, c == &boot_cpu_data.
1607 if (c != &boot_cpu_data) {
1608 /* AND the already accumulated flags with these */
1609 for (i = 0; i < NCAPINTS; i++)
1610 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1612 /* OR, i.e. replicate the bug flags */
1613 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1614 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1617 /* Init Machine Check Exception if available. */
1620 select_idle_routine(c);
1623 numa_add_cpu(smp_processor_id());
1628 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1629 * on 32-bit kernels:
1631 #ifdef CONFIG_X86_32
1632 void enable_sep_cpu(void)
1634 struct tss_struct *tss;
1637 if (!boot_cpu_has(X86_FEATURE_SEP))
1641 tss = &per_cpu(cpu_tss_rw, cpu);
1644 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1645 * see the big comment in struct x86_hw_tss's definition.
1648 tss->x86_tss.ss1 = __KERNEL_CS;
1649 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1650 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1651 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1657 void __init identify_boot_cpu(void)
1659 identify_cpu(&boot_cpu_data);
1660 #ifdef CONFIG_X86_32
1664 cpu_detect_tlb(&boot_cpu_data);
1670 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1672 BUG_ON(c == &boot_cpu_data);
1674 #ifdef CONFIG_X86_32
1678 validate_apic_and_package_id(c);
1679 x86_spec_ctrl_setup_ap();
1683 static __init int setup_noclflush(char *arg)
1685 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1686 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1689 __setup("noclflush", setup_noclflush);
1691 void print_cpu_info(struct cpuinfo_x86 *c)
1693 const char *vendor = NULL;
1695 if (c->x86_vendor < X86_VENDOR_NUM) {
1696 vendor = this_cpu->c_vendor;
1698 if (c->cpuid_level >= 0)
1699 vendor = c->x86_vendor_id;
1702 if (vendor && !strstr(c->x86_model_id, vendor))
1703 pr_cont("%s ", vendor);
1705 if (c->x86_model_id[0])
1706 pr_cont("%s", c->x86_model_id);
1708 pr_cont("%d86", c->x86);
1710 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1712 if (c->x86_stepping || c->cpuid_level >= 0)
1713 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1719 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1720 * But we need to keep a dummy __setup around otherwise it would
1721 * show up as an environment variable for init.
1723 static __init int setup_clearcpuid(char *arg)
1727 __setup("clearcpuid=", setup_clearcpuid);
1729 #ifdef CONFIG_X86_64
1730 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
1731 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
1732 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
1735 * The following percpu variables are hot. Align current_task to
1736 * cacheline size such that they fall in the same cacheline.
1738 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1740 EXPORT_PER_CPU_SYMBOL(current_task);
1742 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
1743 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1745 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1746 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1748 /* May not be marked __init: used by software suspend */
1749 void syscall_init(void)
1751 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1752 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1754 #ifdef CONFIG_IA32_EMULATION
1755 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1757 * This only works on Intel CPUs.
1758 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1759 * This does not cause SYSENTER to jump to the wrong location, because
1760 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1762 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1763 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1764 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1765 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1767 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1768 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1769 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1770 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1773 /* Flags to clear on syscall */
1774 wrmsrl(MSR_SYSCALL_MASK,
1775 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1776 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1779 #else /* CONFIG_X86_64 */
1781 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1782 EXPORT_PER_CPU_SYMBOL(current_task);
1783 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1784 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1787 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1788 * the top of the kernel stack. Use an extra percpu variable to track the
1789 * top of the kernel stack directly.
1791 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1792 (unsigned long)&init_thread_union + THREAD_SIZE;
1793 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1795 #ifdef CONFIG_STACKPROTECTOR
1796 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1799 #endif /* CONFIG_X86_64 */
1802 * Clear all 6 debug registers:
1804 static void clear_all_debug_regs(void)
1808 for (i = 0; i < 8; i++) {
1809 /* Ignore db4, db5 */
1810 if ((i == 4) || (i == 5))
1819 * Restore debug regs if using kgdbwait and you have a kernel debugger
1820 * connection established.
1822 static void dbg_restore_debug_regs(void)
1824 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1825 arch_kgdb_ops.correct_hw_break();
1827 #else /* ! CONFIG_KGDB */
1828 #define dbg_restore_debug_regs()
1829 #endif /* ! CONFIG_KGDB */
1831 static void wait_for_master_cpu(int cpu)
1835 * wait for ACK from master CPU before continuing
1836 * with AP initialization
1838 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1839 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1844 #ifdef CONFIG_X86_64
1845 static inline void setup_getcpu(int cpu)
1847 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
1848 struct desc_struct d = { };
1850 if (boot_cpu_has(X86_FEATURE_RDTSCP))
1851 write_rdtscp_aux(cpudata);
1853 /* Store CPU and node number in limit. */
1855 d.limit1 = cpudata >> 16;
1857 d.type = 5; /* RO data, expand down, accessed */
1858 d.dpl = 3; /* Visible to user code */
1859 d.s = 1; /* Not a system segment */
1860 d.p = 1; /* Present */
1861 d.d = 1; /* 32-bit */
1863 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
1866 static inline void ucode_cpu_init(int cpu)
1872 static inline void tss_setup_ist(struct tss_struct *tss)
1874 /* Set up the per-CPU TSS IST stacks */
1875 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
1876 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
1877 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
1878 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
1879 /* Only mapped when SEV-ES is active */
1880 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
1883 #else /* CONFIG_X86_64 */
1885 static inline void setup_getcpu(int cpu) { }
1887 static inline void ucode_cpu_init(int cpu)
1889 show_ucode_info_early();
1892 static inline void tss_setup_ist(struct tss_struct *tss) { }
1894 #endif /* !CONFIG_X86_64 */
1896 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
1898 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
1900 #ifdef CONFIG_X86_IOPL_IOPERM
1901 tss->io_bitmap.prev_max = 0;
1902 tss->io_bitmap.prev_sequence = 0;
1903 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
1905 * Invalidate the extra array entry past the end of the all
1906 * permission bitmap as required by the hardware.
1908 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
1913 * Setup everything needed to handle exceptions from the IDT, including the IST
1914 * exceptions which use paranoid_entry().
1916 void cpu_init_exception_handling(void)
1918 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
1919 int cpu = raw_smp_processor_id();
1921 /* paranoid_entry() gets the CPU number from the GDT */
1924 /* IST vectors need TSS to be set up. */
1926 tss_setup_io_bitmap(tss);
1927 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1931 /* Finally load the IDT */
1936 * cpu_init() initializes state that is per-CPU. Some data is already
1937 * initialized (naturally) in the bootstrap process, such as the GDT
1938 * and IDT. We reload them nevertheless, this function acts as a
1939 * 'CPU state barrier', nothing should get across.
1943 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
1944 struct task_struct *cur = current;
1945 int cpu = raw_smp_processor_id();
1947 wait_for_master_cpu(cpu);
1949 ucode_cpu_init(cpu);
1952 if (this_cpu_read(numa_node) == 0 &&
1953 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1954 set_numa_node(early_cpu_to_node(cpu));
1958 pr_debug("Initializing CPU#%d\n", cpu);
1960 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
1961 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
1962 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1965 * Initialize the per-CPU GDT with the boot GDT,
1966 * and set up the GDT descriptor:
1968 switch_to_new_gdt(cpu);
1971 if (IS_ENABLED(CONFIG_X86_64)) {
1973 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1976 wrmsrl(MSR_FS_BASE, 0);
1977 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1984 cur->active_mm = &init_mm;
1986 initialize_tlbstate_and_flush();
1987 enter_lazy_tlb(&init_mm, cur);
1989 /* Initialize the TSS. */
1991 tss_setup_io_bitmap(tss);
1992 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1996 * sp0 points to the entry trampoline stack regardless of what task
1999 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
2001 load_mm_ldt(&init_mm);
2003 clear_all_debug_regs();
2004 dbg_restore_debug_regs();
2006 doublefault_init_cpu_tss();
2013 load_fixmap_gdt(cpu);
2017 * The microcode loader calls this upon late microcode load to recheck features,
2018 * only when microcode has been updated. Caller holds microcode_mutex and CPU
2021 void microcode_check(void)
2023 struct cpuinfo_x86 info;
2025 perf_check_microcode();
2027 /* Reload CPUID max function as it might've changed. */
2028 info.cpuid_level = cpuid_eax(0);
2031 * Copy all capability leafs to pick up the synthetic ones so that
2032 * memcmp() below doesn't fail on that. The ones coming from CPUID will
2033 * get overwritten in get_cpu_cap().
2035 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
2039 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
2042 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2043 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2047 * Invoked from core CPU hotplug code after hotplug operations
2049 void arch_smt_update(void)
2051 /* Handle the speculative execution misfeatures */
2052 cpu_bugs_smt_update();
2053 /* Check whether IPI broadcasting can be enabled */