1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/init.h>
18 #include <linux/kprobes.h>
19 #include <linux/kgdb.h>
20 #include <linux/smp.h>
22 #include <linux/syscore_ops.h>
24 #include <asm/stackprotector.h>
25 #include <asm/perf_event.h>
26 #include <asm/mmu_context.h>
27 #include <asm/archrandom.h>
28 #include <asm/hypervisor.h>
29 #include <asm/processor.h>
30 #include <asm/tlbflush.h>
31 #include <asm/debugreg.h>
32 #include <asm/sections.h>
33 #include <asm/vsyscall.h>
34 #include <linux/topology.h>
35 #include <linux/cpumask.h>
36 #include <asm/pgtable.h>
37 #include <linux/atomic.h>
38 #include <asm/proto.h>
39 #include <asm/setup.h>
42 #include <asm/fpu/internal.h>
44 #include <asm/hwcap2.h>
45 #include <linux/numa.h>
52 #include <asm/microcode.h>
53 #include <asm/microcode_intel.h>
54 #include <asm/intel-family.h>
55 #include <asm/cpu_device_id.h>
57 #ifdef CONFIG_X86_LOCAL_APIC
58 #include <asm/uv/uv.h>
63 u32 elf_hwcap2 __read_mostly;
65 /* all of these masks are initialized in setup_cpu_local_masks() */
66 cpumask_var_t cpu_initialized_mask;
67 cpumask_var_t cpu_callout_mask;
68 cpumask_var_t cpu_callin_mask;
70 /* representing cpus for which sibling maps can be computed */
71 cpumask_var_t cpu_sibling_setup_mask;
73 /* Number of siblings per CPU package */
74 int smp_num_siblings = 1;
75 EXPORT_SYMBOL(smp_num_siblings);
77 /* Last level cache ID of each logical CPU */
78 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
80 /* correctly size the local cpu masks */
81 void __init setup_cpu_local_masks(void)
83 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
84 alloc_bootmem_cpumask_var(&cpu_callin_mask);
85 alloc_bootmem_cpumask_var(&cpu_callout_mask);
86 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
89 static void default_init(struct cpuinfo_x86 *c)
92 cpu_detect_cache_sizes(c);
94 /* Not much we can do here... */
95 /* Check if at least it has cpuid */
96 if (c->cpuid_level == -1) {
97 /* No cpuid. It must be an ancient CPU */
99 strcpy(c->x86_model_id, "486");
100 else if (c->x86 == 3)
101 strcpy(c->x86_model_id, "386");
106 static const struct cpu_dev default_cpu = {
107 .c_init = default_init,
108 .c_vendor = "Unknown",
109 .c_x86_vendor = X86_VENDOR_UNKNOWN,
112 static const struct cpu_dev *this_cpu = &default_cpu;
114 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
117 * We need valid kernel segments for data and code in long mode too
118 * IRET will check the segment types kkeil 2000/10/28
119 * Also sysret mandates a special GDT layout
121 * TLS descriptors are currently at a different place compared to i386.
122 * Hopefully nobody expects them at a fixed place (Wine?)
124 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
125 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
126 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
127 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
129 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
131 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
132 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
133 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
134 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
136 * Segments used for calling PnP BIOS have byte granularity.
137 * They code segments and data segments have fixed 64k limits,
138 * the transfer segment sizes are set at run time.
141 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
143 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
145 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
147 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
149 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
151 * The APM segments have byte granularity and their bases
152 * are set at run time. All have 64k limits.
155 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
157 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
159 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
161 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
162 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
163 GDT_STACK_CANARY_INIT
166 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
168 static int __init x86_mpx_setup(char *s)
170 /* require an exact match without trailing characters */
174 /* do not emit a message if the feature is not present */
175 if (!boot_cpu_has(X86_FEATURE_MPX))
178 setup_clear_cpu_cap(X86_FEATURE_MPX);
179 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
182 __setup("nompx", x86_mpx_setup);
185 static int __init x86_nopcid_setup(char *s)
187 /* nopcid doesn't accept parameters */
191 /* do not emit a message if the feature is not present */
192 if (!boot_cpu_has(X86_FEATURE_PCID))
195 setup_clear_cpu_cap(X86_FEATURE_PCID);
196 pr_info("nopcid: PCID feature disabled\n");
199 early_param("nopcid", x86_nopcid_setup);
202 static int __init x86_noinvpcid_setup(char *s)
204 /* noinvpcid doesn't accept parameters */
208 /* do not emit a message if the feature is not present */
209 if (!boot_cpu_has(X86_FEATURE_INVPCID))
212 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
213 pr_info("noinvpcid: INVPCID feature disabled\n");
216 early_param("noinvpcid", x86_noinvpcid_setup);
219 static int cachesize_override = -1;
220 static int disable_x86_serial_nr = 1;
222 static int __init cachesize_setup(char *str)
224 get_option(&str, &cachesize_override);
227 __setup("cachesize=", cachesize_setup);
229 static int __init x86_sep_setup(char *s)
231 setup_clear_cpu_cap(X86_FEATURE_SEP);
234 __setup("nosep", x86_sep_setup);
236 /* Standard macro to see if a specific flag is changeable */
237 static inline int flag_is_changeable_p(u32 flag)
242 * Cyrix and IDT cpus allow disabling of CPUID
243 * so the code below may return different results
244 * when it is executed before and after enabling
245 * the CPUID. Add "volatile" to not allow gcc to
246 * optimize the subsequent calls to this function.
248 asm volatile ("pushfl \n\t"
259 : "=&r" (f1), "=&r" (f2)
262 return ((f1^f2) & flag) != 0;
265 /* Probe for the CPUID instruction */
266 int have_cpuid_p(void)
268 return flag_is_changeable_p(X86_EFLAGS_ID);
271 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
273 unsigned long lo, hi;
275 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
278 /* Disable processor serial number: */
280 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
282 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
284 pr_notice("CPU serial number disabled.\n");
285 clear_cpu_cap(c, X86_FEATURE_PN);
287 /* Disabling the serial number may affect the cpuid level */
288 c->cpuid_level = cpuid_eax(0);
291 static int __init x86_serial_nr_setup(char *s)
293 disable_x86_serial_nr = 0;
296 __setup("serialnumber", x86_serial_nr_setup);
298 static inline int flag_is_changeable_p(u32 flag)
302 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
307 static __init int setup_disable_smep(char *arg)
309 setup_clear_cpu_cap(X86_FEATURE_SMEP);
310 /* Check for things that depend on SMEP being enabled: */
311 check_mpx_erratum(&boot_cpu_data);
314 __setup("nosmep", setup_disable_smep);
316 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
318 if (cpu_has(c, X86_FEATURE_SMEP))
319 cr4_set_bits(X86_CR4_SMEP);
322 static __init int setup_disable_smap(char *arg)
324 setup_clear_cpu_cap(X86_FEATURE_SMAP);
327 __setup("nosmap", setup_disable_smap);
329 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
331 unsigned long eflags = native_save_fl();
333 /* This should have been cleared long ago */
334 BUG_ON(eflags & X86_EFLAGS_AC);
336 if (cpu_has(c, X86_FEATURE_SMAP)) {
337 #ifdef CONFIG_X86_SMAP
338 cr4_set_bits(X86_CR4_SMAP);
340 cr4_clear_bits(X86_CR4_SMAP);
345 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
347 /* Check the boot processor, plus build option for UMIP. */
348 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
351 /* Check the current processor's cpuid bits. */
352 if (!cpu_has(c, X86_FEATURE_UMIP))
355 cr4_set_bits(X86_CR4_UMIP);
357 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
363 * Make sure UMIP is disabled in case it was enabled in a
364 * previous boot (e.g., via kexec).
366 cr4_clear_bits(X86_CR4_UMIP);
369 static __init int x86_nofsgsbase_setup(char *arg)
371 /* Require an exact match without trailing characters. */
375 /* Do not emit a message if the feature is not present. */
376 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
379 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
380 pr_info("FSGSBASE disabled via kernel command line\n");
383 __setup("nofsgsbase", x86_nofsgsbase_setup);
386 * Protection Keys are not available in 32-bit mode.
388 static bool pku_disabled;
390 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
392 struct pkru_state *pk;
394 /* check the boot processor, plus compile options for PKU: */
395 if (!cpu_feature_enabled(X86_FEATURE_PKU))
397 /* checks the actual processor's cpuid bits: */
398 if (!cpu_has(c, X86_FEATURE_PKU))
403 cr4_set_bits(X86_CR4_PKE);
404 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU);
406 pk->pkru = init_pkru_value;
408 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
409 * cpuid bit to be set. We need to ensure that we
410 * update that bit in this CPU's "cpu_info".
415 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
416 static __init int setup_disable_pku(char *arg)
419 * Do not clear the X86_FEATURE_PKU bit. All of the
420 * runtime checks are against OSPKE so clearing the
423 * This way, we will see "pku" in cpuinfo, but not
424 * "ospke", which is exactly what we want. It shows
425 * that the CPU has PKU, but the OS has not enabled it.
426 * This happens to be exactly how a system would look
427 * if we disabled the config option.
429 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
433 __setup("nopku", setup_disable_pku);
434 #endif /* CONFIG_X86_64 */
437 * Some CPU features depend on higher CPUID levels, which may not always
438 * be available due to CPUID level capping or broken virtualization
439 * software. Add those features to this table to auto-disable them.
441 struct cpuid_dependent_feature {
446 static const struct cpuid_dependent_feature
447 cpuid_dependent_features[] = {
448 { X86_FEATURE_MWAIT, 0x00000005 },
449 { X86_FEATURE_DCA, 0x00000009 },
450 { X86_FEATURE_XSAVE, 0x0000000d },
454 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
456 const struct cpuid_dependent_feature *df;
458 for (df = cpuid_dependent_features; df->feature; df++) {
460 if (!cpu_has(c, df->feature))
463 * Note: cpuid_level is set to -1 if unavailable, but
464 * extended_extended_level is set to 0 if unavailable
465 * and the legitimate extended levels are all negative
466 * when signed; hence the weird messing around with
469 if (!((s32)df->level < 0 ?
470 (u32)df->level > (u32)c->extended_cpuid_level :
471 (s32)df->level > (s32)c->cpuid_level))
474 clear_cpu_cap(c, df->feature);
478 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
479 x86_cap_flag(df->feature), df->level);
484 * Naming convention should be: <Name> [(<Codename>)]
485 * This table only is used unless init_<vendor>() below doesn't set it;
486 * in particular, if CPUID levels 0x80000002..4 are supported, this
490 /* Look up CPU names by table lookup. */
491 static const char *table_lookup_model(struct cpuinfo_x86 *c)
494 const struct legacy_cpu_model_info *info;
496 if (c->x86_model >= 16)
497 return NULL; /* Range check */
502 info = this_cpu->legacy_models;
504 while (info->family) {
505 if (info->family == c->x86)
506 return info->model_names[c->x86_model];
510 return NULL; /* Not found */
513 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
514 __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
516 void load_percpu_segment(int cpu)
519 loadsegment(fs, __KERNEL_PERCPU);
521 __loadsegment_simple(gs, 0);
522 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
524 load_stack_canary_segment();
528 /* The 32-bit entry code needs to find cpu_entry_area. */
529 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
532 /* Load the original GDT from the per-cpu structure */
533 void load_direct_gdt(int cpu)
535 struct desc_ptr gdt_descr;
537 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
538 gdt_descr.size = GDT_SIZE - 1;
539 load_gdt(&gdt_descr);
541 EXPORT_SYMBOL_GPL(load_direct_gdt);
543 /* Load a fixmap remapping of the per-cpu GDT */
544 void load_fixmap_gdt(int cpu)
546 struct desc_ptr gdt_descr;
548 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
549 gdt_descr.size = GDT_SIZE - 1;
550 load_gdt(&gdt_descr);
552 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
555 * Current gdt points %fs at the "master" per-cpu area: after this,
556 * it's on the real one.
558 void switch_to_new_gdt(int cpu)
560 /* Load the original GDT */
561 load_direct_gdt(cpu);
562 /* Reload the per-cpu base */
563 load_percpu_segment(cpu);
566 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
568 static void get_model_name(struct cpuinfo_x86 *c)
573 if (c->extended_cpuid_level < 0x80000004)
576 v = (unsigned int *)c->x86_model_id;
577 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
578 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
579 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
580 c->x86_model_id[48] = 0;
582 /* Trim whitespace */
583 p = q = s = &c->x86_model_id[0];
589 /* Note the last non-whitespace index */
599 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
601 unsigned int eax, ebx, ecx, edx;
603 c->x86_max_cores = 1;
604 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
607 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
609 c->x86_max_cores = (eax >> 26) + 1;
612 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
614 unsigned int n, dummy, ebx, ecx, edx, l2size;
616 n = c->extended_cpuid_level;
618 if (n >= 0x80000005) {
619 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
620 c->x86_cache_size = (ecx>>24) + (edx>>24);
622 /* On K8 L1 TLB is inclusive, so don't count it */
627 if (n < 0x80000006) /* Some chips just has a large L1. */
630 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
634 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
636 /* do processor-specific cache resizing */
637 if (this_cpu->legacy_cache_size)
638 l2size = this_cpu->legacy_cache_size(c, l2size);
640 /* Allow user to override all this if necessary. */
641 if (cachesize_override != -1)
642 l2size = cachesize_override;
645 return; /* Again, no L2 cache is possible */
648 c->x86_cache_size = l2size;
651 u16 __read_mostly tlb_lli_4k[NR_INFO];
652 u16 __read_mostly tlb_lli_2m[NR_INFO];
653 u16 __read_mostly tlb_lli_4m[NR_INFO];
654 u16 __read_mostly tlb_lld_4k[NR_INFO];
655 u16 __read_mostly tlb_lld_2m[NR_INFO];
656 u16 __read_mostly tlb_lld_4m[NR_INFO];
657 u16 __read_mostly tlb_lld_1g[NR_INFO];
659 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
661 if (this_cpu->c_detect_tlb)
662 this_cpu->c_detect_tlb(c);
664 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
665 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
666 tlb_lli_4m[ENTRIES]);
668 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
669 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
670 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
673 int detect_ht_early(struct cpuinfo_x86 *c)
676 u32 eax, ebx, ecx, edx;
678 if (!cpu_has(c, X86_FEATURE_HT))
681 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
684 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
687 cpuid(1, &eax, &ebx, &ecx, &edx);
689 smp_num_siblings = (ebx & 0xff0000) >> 16;
690 if (smp_num_siblings == 1)
691 pr_info_once("CPU0: Hyper-Threading is disabled\n");
696 void detect_ht(struct cpuinfo_x86 *c)
699 int index_msb, core_bits;
701 if (detect_ht_early(c) < 0)
704 index_msb = get_count_order(smp_num_siblings);
705 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
707 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
709 index_msb = get_count_order(smp_num_siblings);
711 core_bits = get_count_order(c->x86_max_cores);
713 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
714 ((1 << core_bits) - 1);
718 static void get_cpu_vendor(struct cpuinfo_x86 *c)
720 char *v = c->x86_vendor_id;
723 for (i = 0; i < X86_VENDOR_NUM; i++) {
727 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
728 (cpu_devs[i]->c_ident[1] &&
729 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
731 this_cpu = cpu_devs[i];
732 c->x86_vendor = this_cpu->c_x86_vendor;
737 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
738 "CPU: Your system may be unstable.\n", v);
740 c->x86_vendor = X86_VENDOR_UNKNOWN;
741 this_cpu = &default_cpu;
744 void cpu_detect(struct cpuinfo_x86 *c)
746 /* Get vendor name */
747 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
748 (unsigned int *)&c->x86_vendor_id[0],
749 (unsigned int *)&c->x86_vendor_id[8],
750 (unsigned int *)&c->x86_vendor_id[4]);
753 /* Intel-defined flags: level 0x00000001 */
754 if (c->cpuid_level >= 0x00000001) {
755 u32 junk, tfms, cap0, misc;
757 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
758 c->x86 = x86_family(tfms);
759 c->x86_model = x86_model(tfms);
760 c->x86_stepping = x86_stepping(tfms);
762 if (cap0 & (1<<19)) {
763 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
764 c->x86_cache_alignment = c->x86_clflush_size;
769 static void apply_forced_caps(struct cpuinfo_x86 *c)
773 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
774 c->x86_capability[i] &= ~cpu_caps_cleared[i];
775 c->x86_capability[i] |= cpu_caps_set[i];
779 static void init_speculation_control(struct cpuinfo_x86 *c)
782 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
783 * and they also have a different bit for STIBP support. Also,
784 * a hypervisor might have set the individual AMD bits even on
785 * Intel CPUs, for finer-grained selection of what's available.
787 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
788 set_cpu_cap(c, X86_FEATURE_IBRS);
789 set_cpu_cap(c, X86_FEATURE_IBPB);
790 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
793 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
794 set_cpu_cap(c, X86_FEATURE_STIBP);
796 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
797 cpu_has(c, X86_FEATURE_VIRT_SSBD))
798 set_cpu_cap(c, X86_FEATURE_SSBD);
800 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
801 set_cpu_cap(c, X86_FEATURE_IBRS);
802 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
805 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
806 set_cpu_cap(c, X86_FEATURE_IBPB);
808 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
809 set_cpu_cap(c, X86_FEATURE_STIBP);
810 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
813 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
814 set_cpu_cap(c, X86_FEATURE_SSBD);
815 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
816 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
820 static void init_cqm(struct cpuinfo_x86 *c)
822 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
823 c->x86_cache_max_rmid = -1;
824 c->x86_cache_occ_scale = -1;
828 /* will be overridden if occupancy monitoring exists */
829 c->x86_cache_max_rmid = cpuid_ebx(0xf);
831 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) ||
832 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) ||
833 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) {
834 u32 eax, ebx, ecx, edx;
836 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
837 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx);
839 c->x86_cache_max_rmid = ecx;
840 c->x86_cache_occ_scale = ebx;
844 void get_cpu_cap(struct cpuinfo_x86 *c)
846 u32 eax, ebx, ecx, edx;
848 /* Intel-defined flags: level 0x00000001 */
849 if (c->cpuid_level >= 0x00000001) {
850 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
852 c->x86_capability[CPUID_1_ECX] = ecx;
853 c->x86_capability[CPUID_1_EDX] = edx;
856 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
857 if (c->cpuid_level >= 0x00000006)
858 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
860 /* Additional Intel-defined flags: level 0x00000007 */
861 if (c->cpuid_level >= 0x00000007) {
862 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
863 c->x86_capability[CPUID_7_0_EBX] = ebx;
864 c->x86_capability[CPUID_7_ECX] = ecx;
865 c->x86_capability[CPUID_7_EDX] = edx;
867 /* Check valid sub-leaf index before accessing it */
869 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
870 c->x86_capability[CPUID_7_1_EAX] = eax;
874 /* Extended state features: level 0x0000000d */
875 if (c->cpuid_level >= 0x0000000d) {
876 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
878 c->x86_capability[CPUID_D_1_EAX] = eax;
881 /* AMD-defined flags: level 0x80000001 */
882 eax = cpuid_eax(0x80000000);
883 c->extended_cpuid_level = eax;
885 if ((eax & 0xffff0000) == 0x80000000) {
886 if (eax >= 0x80000001) {
887 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
889 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
890 c->x86_capability[CPUID_8000_0001_EDX] = edx;
894 if (c->extended_cpuid_level >= 0x80000007) {
895 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
897 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
901 if (c->extended_cpuid_level >= 0x80000008) {
902 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
903 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
906 if (c->extended_cpuid_level >= 0x8000000a)
907 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
909 init_scattered_cpuid_features(c);
910 init_speculation_control(c);
914 * Clear/Set all flags overridden by options, after probe.
915 * This needs to happen each time we re-probe, which may happen
916 * several times during CPU initialization.
918 apply_forced_caps(c);
921 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
923 u32 eax, ebx, ecx, edx;
925 if (c->extended_cpuid_level >= 0x80000008) {
926 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
928 c->x86_virt_bits = (eax >> 8) & 0xff;
929 c->x86_phys_bits = eax & 0xff;
932 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
933 c->x86_phys_bits = 36;
935 c->x86_cache_bits = c->x86_phys_bits;
938 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
944 * First of all, decide if this is a 486 or higher
945 * It's a 486 if we can modify the AC flag
947 if (flag_is_changeable_p(X86_EFLAGS_AC))
952 for (i = 0; i < X86_VENDOR_NUM; i++)
953 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
954 c->x86_vendor_id[0] = 0;
955 cpu_devs[i]->c_identify(c);
956 if (c->x86_vendor_id[0]) {
964 #define NO_SPECULATION BIT(0)
965 #define NO_MELTDOWN BIT(1)
966 #define NO_SSB BIT(2)
967 #define NO_L1TF BIT(3)
968 #define NO_MDS BIT(4)
969 #define MSBDS_ONLY BIT(5)
971 #define VULNWL(_vendor, _family, _model, _whitelist) \
972 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
974 #define VULNWL_INTEL(model, whitelist) \
975 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
977 #define VULNWL_AMD(family, whitelist) \
978 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
980 #define VULNWL_HYGON(family, whitelist) \
981 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
983 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
984 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
985 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
986 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
987 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
990 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION),
991 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION),
992 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION),
993 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION),
994 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION),
996 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY),
997 VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY),
998 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY),
999 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY),
1000 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY),
1001 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY),
1003 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1005 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY),
1007 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF),
1008 VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF),
1009 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF),
1011 /* AMD Family 0xf - 0x12 */
1012 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
1013 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
1014 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
1015 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
1017 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1018 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS),
1019 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS),
1023 static bool __init cpu_matches(unsigned long which)
1025 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist);
1027 return m && !!(m->driver_data & which);
1030 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1034 if (cpu_matches(NO_SPECULATION))
1037 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1038 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1040 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
1041 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1043 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) &&
1044 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1045 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1047 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1048 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1050 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) {
1051 setup_force_cpu_bug(X86_BUG_MDS);
1052 if (cpu_matches(MSBDS_ONLY))
1053 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1056 if (cpu_matches(NO_MELTDOWN))
1059 /* Rogue Data Cache Load? No! */
1060 if (ia32_cap & ARCH_CAP_RDCL_NO)
1063 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1065 if (cpu_matches(NO_L1TF))
1068 setup_force_cpu_bug(X86_BUG_L1TF);
1072 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1073 * unfortunately, that's not true in practice because of early VIA
1074 * chips and (more importantly) broken virtualizers that are not easy
1075 * to detect. In the latter case it doesn't even *fail* reliably, so
1076 * probing for it doesn't even work. Disable it completely on 32-bit
1077 * unless we can find a reliable way to detect all the broken cases.
1078 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1080 static void detect_nopl(void)
1082 #ifdef CONFIG_X86_32
1083 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1085 setup_force_cpu_cap(X86_FEATURE_NOPL);
1090 * Do minimum CPU detection early.
1091 * Fields really needed: vendor, cpuid_level, family, model, mask,
1093 * The others are not touched to avoid unwanted side effects.
1095 * WARNING: this function is only called on the boot CPU. Don't add code
1096 * here that is supposed to run on all CPUs.
1098 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1100 #ifdef CONFIG_X86_64
1101 c->x86_clflush_size = 64;
1102 c->x86_phys_bits = 36;
1103 c->x86_virt_bits = 48;
1105 c->x86_clflush_size = 32;
1106 c->x86_phys_bits = 32;
1107 c->x86_virt_bits = 32;
1109 c->x86_cache_alignment = c->x86_clflush_size;
1111 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1112 c->extended_cpuid_level = 0;
1114 if (!have_cpuid_p())
1115 identify_cpu_without_cpuid(c);
1117 /* cyrix could have cpuid enabled via c_identify()*/
1118 if (have_cpuid_p()) {
1122 get_cpu_address_sizes(c);
1123 setup_force_cpu_cap(X86_FEATURE_CPUID);
1125 if (this_cpu->c_early_init)
1126 this_cpu->c_early_init(c);
1129 filter_cpuid_features(c, false);
1131 if (this_cpu->c_bsp_init)
1132 this_cpu->c_bsp_init(c);
1134 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1137 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1139 cpu_set_bug_bits(c);
1141 fpu__init_system(c);
1143 #ifdef CONFIG_X86_32
1145 * Regardless of whether PCID is enumerated, the SDM says
1146 * that it can't be enabled in 32-bit mode.
1148 setup_clear_cpu_cap(X86_FEATURE_PCID);
1152 * Later in the boot process pgtable_l5_enabled() relies on
1153 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1154 * enabled by this point we need to clear the feature bit to avoid
1155 * false-positives at the later stage.
1157 * pgtable_l5_enabled() can be false here for several reasons:
1158 * - 5-level paging is disabled compile-time;
1159 * - it's 32-bit kernel;
1160 * - machine doesn't support 5-level paging;
1161 * - user specified 'no5lvl' in kernel command line.
1163 if (!pgtable_l5_enabled())
1164 setup_clear_cpu_cap(X86_FEATURE_LA57);
1169 void __init early_cpu_init(void)
1171 const struct cpu_dev *const *cdev;
1174 #ifdef CONFIG_PROCESSOR_SELECT
1175 pr_info("KERNEL supported cpus:\n");
1178 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1179 const struct cpu_dev *cpudev = *cdev;
1181 if (count >= X86_VENDOR_NUM)
1183 cpu_devs[count] = cpudev;
1186 #ifdef CONFIG_PROCESSOR_SELECT
1190 for (j = 0; j < 2; j++) {
1191 if (!cpudev->c_ident[j])
1193 pr_info(" %s %s\n", cpudev->c_vendor,
1194 cpudev->c_ident[j]);
1199 early_identify_cpu(&boot_cpu_data);
1202 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1204 #ifdef CONFIG_X86_64
1206 * Empirically, writing zero to a segment selector on AMD does
1207 * not clear the base, whereas writing zero to a segment
1208 * selector on Intel does clear the base. Intel's behavior
1209 * allows slightly faster context switches in the common case
1210 * where GS is unused by the prev and next threads.
1212 * Since neither vendor documents this anywhere that I can see,
1213 * detect it directly instead of hardcoding the choice by
1216 * I've designated AMD's behavior as the "bug" because it's
1217 * counterintuitive and less friendly.
1220 unsigned long old_base, tmp;
1221 rdmsrl(MSR_FS_BASE, old_base);
1222 wrmsrl(MSR_FS_BASE, 1);
1224 rdmsrl(MSR_FS_BASE, tmp);
1226 set_cpu_bug(c, X86_BUG_NULL_SEG);
1227 wrmsrl(MSR_FS_BASE, old_base);
1231 static void generic_identify(struct cpuinfo_x86 *c)
1233 c->extended_cpuid_level = 0;
1235 if (!have_cpuid_p())
1236 identify_cpu_without_cpuid(c);
1238 /* cyrix could have cpuid enabled via c_identify()*/
1239 if (!have_cpuid_p())
1248 get_cpu_address_sizes(c);
1250 if (c->cpuid_level >= 0x00000001) {
1251 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1252 #ifdef CONFIG_X86_32
1254 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1256 c->apicid = c->initial_apicid;
1259 c->phys_proc_id = c->initial_apicid;
1262 get_model_name(c); /* Default name */
1264 detect_null_seg_behavior(c);
1267 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1268 * systems that run Linux at CPL > 0 may or may not have the
1269 * issue, but, even if they have the issue, there's absolutely
1270 * nothing we can do about it because we can't use the real IRET
1273 * NB: For the time being, only 32-bit kernels support
1274 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1275 * whether to apply espfix using paravirt hooks. If any
1276 * non-paravirt system ever shows up that does *not* have the
1277 * ESPFIX issue, we can change this.
1279 #ifdef CONFIG_X86_32
1280 # ifdef CONFIG_PARAVIRT_XXL
1282 extern void native_iret(void);
1283 if (pv_ops.cpu.iret == native_iret)
1284 set_cpu_bug(c, X86_BUG_ESPFIX);
1287 set_cpu_bug(c, X86_BUG_ESPFIX);
1292 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1295 * The heavy lifting of max_rmid and cache_occ_scale are handled
1296 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1297 * in case CQM bits really aren't there in this CPU.
1299 if (c != &boot_cpu_data) {
1300 boot_cpu_data.x86_cache_max_rmid =
1301 min(boot_cpu_data.x86_cache_max_rmid,
1302 c->x86_cache_max_rmid);
1307 * Validate that ACPI/mptables have the same information about the
1308 * effective APIC id and update the package map.
1310 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1313 unsigned int apicid, cpu = smp_processor_id();
1315 apicid = apic->cpu_present_to_apicid(cpu);
1317 if (apicid != c->apicid) {
1318 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1319 cpu, apicid, c->initial_apicid);
1321 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1323 c->logical_proc_id = 0;
1328 * This does the hard work of actually picking apart the CPU stuff...
1330 static void identify_cpu(struct cpuinfo_x86 *c)
1334 c->loops_per_jiffy = loops_per_jiffy;
1335 c->x86_cache_size = 0;
1336 c->x86_vendor = X86_VENDOR_UNKNOWN;
1337 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1338 c->x86_vendor_id[0] = '\0'; /* Unset */
1339 c->x86_model_id[0] = '\0'; /* Unset */
1340 c->x86_max_cores = 1;
1341 c->x86_coreid_bits = 0;
1343 #ifdef CONFIG_X86_64
1344 c->x86_clflush_size = 64;
1345 c->x86_phys_bits = 36;
1346 c->x86_virt_bits = 48;
1348 c->cpuid_level = -1; /* CPUID not detected */
1349 c->x86_clflush_size = 32;
1350 c->x86_phys_bits = 32;
1351 c->x86_virt_bits = 32;
1353 c->x86_cache_alignment = c->x86_clflush_size;
1354 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1356 generic_identify(c);
1358 if (this_cpu->c_identify)
1359 this_cpu->c_identify(c);
1361 /* Clear/Set all flags overridden by options, after probe */
1362 apply_forced_caps(c);
1364 #ifdef CONFIG_X86_64
1365 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1369 * Vendor-specific initialization. In this section we
1370 * canonicalize the feature flags, meaning if there are
1371 * features a certain CPU supports which CPUID doesn't
1372 * tell us, CPUID claiming incorrect flags, or other bugs,
1373 * we handle them here.
1375 * At the end of this section, c->x86_capability better
1376 * indicate the features this CPU genuinely supports!
1378 if (this_cpu->c_init)
1379 this_cpu->c_init(c);
1381 /* Disable the PN if appropriate */
1382 squash_the_stupid_serial_number(c);
1384 /* Set up SMEP/SMAP/UMIP */
1389 /* Enable FSGSBASE instructions if available. */
1390 if (cpu_has(c, X86_FEATURE_FSGSBASE))
1391 cr4_set_bits(X86_CR4_FSGSBASE);
1394 * The vendor-specific functions might have changed features.
1395 * Now we do "generic changes."
1398 /* Filter out anything that depends on CPUID levels we don't have */
1399 filter_cpuid_features(c, true);
1401 /* If the model name is still unset, do table lookup. */
1402 if (!c->x86_model_id[0]) {
1404 p = table_lookup_model(c);
1406 strcpy(c->x86_model_id, p);
1408 /* Last resort... */
1409 sprintf(c->x86_model_id, "%02x/%02x",
1410 c->x86, c->x86_model);
1413 #ifdef CONFIG_X86_64
1418 x86_init_cache_qos(c);
1422 * Clear/Set all flags overridden by options, need do it
1423 * before following smp all cpus cap AND.
1425 apply_forced_caps(c);
1428 * On SMP, boot_cpu_data holds the common feature set between
1429 * all CPUs; so make sure that we indicate which features are
1430 * common between the CPUs. The first time this routine gets
1431 * executed, c == &boot_cpu_data.
1433 if (c != &boot_cpu_data) {
1434 /* AND the already accumulated flags with these */
1435 for (i = 0; i < NCAPINTS; i++)
1436 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1438 /* OR, i.e. replicate the bug flags */
1439 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1440 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1443 /* Init Machine Check Exception if available. */
1446 select_idle_routine(c);
1449 numa_add_cpu(smp_processor_id());
1454 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1455 * on 32-bit kernels:
1457 #ifdef CONFIG_X86_32
1458 void enable_sep_cpu(void)
1460 struct tss_struct *tss;
1463 if (!boot_cpu_has(X86_FEATURE_SEP))
1467 tss = &per_cpu(cpu_tss_rw, cpu);
1470 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1471 * see the big comment in struct x86_hw_tss's definition.
1474 tss->x86_tss.ss1 = __KERNEL_CS;
1475 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1476 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1477 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1483 void __init identify_boot_cpu(void)
1485 identify_cpu(&boot_cpu_data);
1486 #ifdef CONFIG_X86_32
1490 cpu_detect_tlb(&boot_cpu_data);
1493 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1495 BUG_ON(c == &boot_cpu_data);
1497 #ifdef CONFIG_X86_32
1501 validate_apic_and_package_id(c);
1502 x86_spec_ctrl_setup_ap();
1505 static __init int setup_noclflush(char *arg)
1507 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1508 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1511 __setup("noclflush", setup_noclflush);
1513 void print_cpu_info(struct cpuinfo_x86 *c)
1515 const char *vendor = NULL;
1517 if (c->x86_vendor < X86_VENDOR_NUM) {
1518 vendor = this_cpu->c_vendor;
1520 if (c->cpuid_level >= 0)
1521 vendor = c->x86_vendor_id;
1524 if (vendor && !strstr(c->x86_model_id, vendor))
1525 pr_cont("%s ", vendor);
1527 if (c->x86_model_id[0])
1528 pr_cont("%s", c->x86_model_id);
1530 pr_cont("%d86", c->x86);
1532 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1534 if (c->x86_stepping || c->cpuid_level >= 0)
1535 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1541 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1542 * But we need to keep a dummy __setup around otherwise it would
1543 * show up as an environment variable for init.
1545 static __init int setup_clearcpuid(char *arg)
1549 __setup("clearcpuid=", setup_clearcpuid);
1551 #ifdef CONFIG_X86_64
1552 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
1553 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
1554 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
1557 * The following percpu variables are hot. Align current_task to
1558 * cacheline size such that they fall in the same cacheline.
1560 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1562 EXPORT_PER_CPU_SYMBOL(current_task);
1564 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
1565 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1567 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1568 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1570 /* May not be marked __init: used by software suspend */
1571 void syscall_init(void)
1573 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1574 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1576 #ifdef CONFIG_IA32_EMULATION
1577 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1579 * This only works on Intel CPUs.
1580 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1581 * This does not cause SYSENTER to jump to the wrong location, because
1582 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1584 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1585 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1586 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1587 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1589 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1590 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1591 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1592 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1595 /* Flags to clear on syscall */
1596 wrmsrl(MSR_SYSCALL_MASK,
1597 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1598 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1601 DEFINE_PER_CPU(int, debug_stack_usage);
1602 DEFINE_PER_CPU(u32, debug_idt_ctr);
1604 void debug_stack_set_zero(void)
1606 this_cpu_inc(debug_idt_ctr);
1609 NOKPROBE_SYMBOL(debug_stack_set_zero);
1611 void debug_stack_reset(void)
1613 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1615 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1618 NOKPROBE_SYMBOL(debug_stack_reset);
1620 #else /* CONFIG_X86_64 */
1622 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1623 EXPORT_PER_CPU_SYMBOL(current_task);
1624 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1625 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1628 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1629 * the top of the kernel stack. Use an extra percpu variable to track the
1630 * top of the kernel stack directly.
1632 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1633 (unsigned long)&init_thread_union + THREAD_SIZE;
1634 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1636 #ifdef CONFIG_STACKPROTECTOR
1637 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1640 #endif /* CONFIG_X86_64 */
1643 * Clear all 6 debug registers:
1645 static void clear_all_debug_regs(void)
1649 for (i = 0; i < 8; i++) {
1650 /* Ignore db4, db5 */
1651 if ((i == 4) || (i == 5))
1660 * Restore debug regs if using kgdbwait and you have a kernel debugger
1661 * connection established.
1663 static void dbg_restore_debug_regs(void)
1665 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1666 arch_kgdb_ops.correct_hw_break();
1668 #else /* ! CONFIG_KGDB */
1669 #define dbg_restore_debug_regs()
1670 #endif /* ! CONFIG_KGDB */
1672 static void wait_for_master_cpu(int cpu)
1676 * wait for ACK from master CPU before continuing
1677 * with AP initialization
1679 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1680 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1685 #ifdef CONFIG_X86_64
1686 static void setup_getcpu(int cpu)
1688 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
1689 struct desc_struct d = { };
1691 if (boot_cpu_has(X86_FEATURE_RDTSCP))
1692 write_rdtscp_aux(cpudata);
1694 /* Store CPU and node number in limit. */
1696 d.limit1 = cpudata >> 16;
1698 d.type = 5; /* RO data, expand down, accessed */
1699 d.dpl = 3; /* Visible to user code */
1700 d.s = 1; /* Not a system segment */
1701 d.p = 1; /* Present */
1702 d.d = 1; /* 32-bit */
1704 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
1709 * cpu_init() initializes state that is per-CPU. Some data is already
1710 * initialized (naturally) in the bootstrap process, such as the GDT
1711 * and IDT. We reload them nevertheless, this function acts as a
1712 * 'CPU state barrier', nothing should get across.
1714 #ifdef CONFIG_X86_64
1718 int cpu = raw_smp_processor_id();
1719 struct task_struct *me;
1720 struct tss_struct *t;
1723 wait_for_master_cpu(cpu);
1726 * Initialize the CR4 shadow before doing anything that could
1734 t = &per_cpu(cpu_tss_rw, cpu);
1737 if (this_cpu_read(numa_node) == 0 &&
1738 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1739 set_numa_node(early_cpu_to_node(cpu));
1745 pr_debug("Initializing CPU#%d\n", cpu);
1747 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1750 * Initialize the per-CPU GDT with the boot GDT,
1751 * and set up the GDT descriptor:
1754 switch_to_new_gdt(cpu);
1759 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1762 wrmsrl(MSR_FS_BASE, 0);
1763 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1770 * set up and load the per-CPU TSS
1772 if (!t->x86_tss.ist[0]) {
1773 t->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
1774 t->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
1775 t->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
1776 t->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
1779 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1782 * <= is required because the CPU will access up to
1783 * 8 bits beyond the end of the IO permission bitmap.
1785 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1786 t->io_bitmap[i] = ~0UL;
1789 me->active_mm = &init_mm;
1791 initialize_tlbstate_and_flush();
1792 enter_lazy_tlb(&init_mm, me);
1795 * Initialize the TSS. sp0 points to the entry trampoline stack
1796 * regardless of what task is running.
1798 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1800 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1802 load_mm_ldt(&init_mm);
1804 clear_all_debug_regs();
1805 dbg_restore_debug_regs();
1812 load_fixmap_gdt(cpu);
1819 int cpu = smp_processor_id();
1820 struct task_struct *curr = current;
1821 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu);
1823 wait_for_master_cpu(cpu);
1826 * Initialize the CR4 shadow before doing anything that could
1831 show_ucode_info_early();
1833 pr_info("Initializing CPU#%d\n", cpu);
1835 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1836 boot_cpu_has(X86_FEATURE_TSC) ||
1837 boot_cpu_has(X86_FEATURE_DE))
1838 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1841 switch_to_new_gdt(cpu);
1844 * Set up and load the per-CPU TSS and LDT
1847 curr->active_mm = &init_mm;
1849 initialize_tlbstate_and_flush();
1850 enter_lazy_tlb(&init_mm, curr);
1853 * Initialize the TSS. sp0 points to the entry trampoline stack
1854 * regardless of what task is running.
1856 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1858 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1860 load_mm_ldt(&init_mm);
1862 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1864 #ifdef CONFIG_DOUBLEFAULT
1865 /* Set up doublefault TSS pointer in the GDT */
1866 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1869 clear_all_debug_regs();
1870 dbg_restore_debug_regs();
1874 load_fixmap_gdt(cpu);
1879 * The microcode loader calls this upon late microcode load to recheck features,
1880 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1883 void microcode_check(void)
1885 struct cpuinfo_x86 info;
1887 perf_check_microcode();
1889 /* Reload CPUID max function as it might've changed. */
1890 info.cpuid_level = cpuid_eax(0);
1893 * Copy all capability leafs to pick up the synthetic ones so that
1894 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1895 * get overwritten in get_cpu_cap().
1897 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
1901 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
1904 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1905 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");