1 #include <linux/bitops.h>
2 #include <linux/kernel.h>
4 #include <asm/processor.h>
11 #ifdef CONFIG_X86_OOSTORE
13 static u32 power2(u32 x)
25 * Set up an actual MCR
27 static void centaur_mcr_insert(int reg, u32 base, u32 size, int key)
32 lo = ~(size-1); /* Size is a power of 2 so this makes a mask */
33 lo &= ~0xFFF; /* Remove the ctrl value bits */
34 lo |= key; /* Attribute we wish to set */
35 wrmsr(reg+MSR_IDT_MCR0, lo, hi);
36 mtrr_centaur_report_mcr(reg, lo, hi); /* Tell the mtrr driver */
40 * Figure what we can cover with MCR's
42 * Shortcut: We know you can't put 4Gig of RAM on a winchip
44 static u32 ramtop(void)
46 u32 clip = 0xFFFFFFFFUL;
50 for (i = 0; i < e820.nr_map; i++) {
51 unsigned long start, end;
53 if (e820.map[i].addr > 0xFFFFFFFFUL)
56 * Don't MCR over reserved space. Ignore the ISA hole
57 * we frob around that catastrophe already
59 if (e820.map[i].type == E820_RESERVED) {
60 if (e820.map[i].addr >= 0x100000UL &&
61 e820.map[i].addr < clip)
62 clip = e820.map[i].addr;
65 start = e820.map[i].addr;
66 end = e820.map[i].addr + e820.map[i].size;
73 * Everything below 'top' should be RAM except for the ISA hole.
74 * Because of the limited MCR's we want to map NV/ACPI into our
75 * MCR range for gunk in RAM
77 * Clip might cause us to MCR insufficient RAM but that is an
78 * acceptable failure mode and should only bite obscure boxes with
81 * The second case Clip sometimes kicks in is when the EBDA is marked
82 * as reserved. Again we fail safe with reasonable results
91 * Compute a set of MCR's to give maximum coverage
93 static int centaur_mcr_compute(int nr, int key)
96 u32 root = power2(mem);
108 * Find the largest block we will fill going upwards
110 high = power2(mem-top);
113 * Find the largest block we will fill going downwards
118 * Don't fill below 1Mb going downwards as there
119 * is an ISA hole in the way.
121 if (base <= 1024*1024)
125 * See how much space we could cover by filling below
131 else if (floor == 512*1024)
134 /* And forget ROM space */
137 * Now install the largest coverage we get
139 if (fspace > high && fspace > low) {
140 centaur_mcr_insert(ct, floor, fspace, key);
142 } else if (high > low) {
143 centaur_mcr_insert(ct, top, high, key);
145 } else if (low > 0) {
147 centaur_mcr_insert(ct, base, low, key);
153 * We loaded ct values. We now need to set the mask. The caller
159 static void centaur_create_optimal_mcr(void)
165 * Allocate up to 6 mcrs to mark as much of ram as possible
166 * as write combining and weak write ordered.
168 * To experiment with: Linux never uses stack operations for
169 * mmio spaces so we could globally enable stack operation wc
171 * Load the registers with type 31 - full write combining, all
172 * writes weakly ordered.
174 used = centaur_mcr_compute(6, 31);
179 for (i = used; i < 8; i++)
180 wrmsr(MSR_IDT_MCR0+i, 0, 0);
183 static void winchip2_create_optimal_mcr(void)
190 * Allocate up to 6 mcrs to mark as much of ram as possible
191 * as write combining, weak store ordered.
193 * Load the registers with type 25
194 * 8 - weak write ordering
195 * 16 - weak read ordering
196 * 1 - write combining
198 used = centaur_mcr_compute(6, 25);
201 * Mark the registers we are using.
203 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
204 for (i = 0; i < used; i++)
206 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
212 for (i = used; i < 8; i++)
213 wrmsr(MSR_IDT_MCR0+i, 0, 0);
217 * Handle the MCR key on the Winchip 2.
219 static void winchip2_unprotect_mcr(void)
224 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
225 lo &= ~0x1C0; /* blank bits 8-6 */
227 lo |= key<<6; /* replace with unlock key */
228 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
231 static void winchip2_protect_mcr(void)
235 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
236 lo &= ~0x1C0; /* blank bits 8-6 */
237 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
239 #endif /* CONFIG_X86_OOSTORE */
241 #define ACE_PRESENT (1 << 6)
242 #define ACE_ENABLED (1 << 7)
243 #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
245 #define RNG_PRESENT (1 << 2)
246 #define RNG_ENABLED (1 << 3)
247 #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
249 static void init_c3(struct cpuinfo_x86 *c)
253 /* Test for Centaur Extended Feature Flags presence */
254 if (cpuid_eax(0xC0000000) >= 0xC0000001) {
255 u32 tmp = cpuid_edx(0xC0000001);
257 /* enable ACE unit, if present and disabled */
258 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
259 rdmsr(MSR_VIA_FCR, lo, hi);
260 lo |= ACE_FCR; /* enable ACE unit */
261 wrmsr(MSR_VIA_FCR, lo, hi);
262 printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n");
265 /* enable RNG unit, if present and disabled */
266 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
267 rdmsr(MSR_VIA_RNG, lo, hi);
268 lo |= RNG_ENABLE; /* enable RNG unit */
269 wrmsr(MSR_VIA_RNG, lo, hi);
270 printk(KERN_INFO "CPU: Enabled h/w RNG\n");
273 /* store Centaur Extended Feature Flags as
274 * word 5 of the CPU capability bit array
276 c->x86_capability[5] = cpuid_edx(0xC0000001);
279 /* Cyrix III family needs CX8 & PGE explicitly enabled. */
280 if (c->x86_model >= 6 && c->x86_model <= 13) {
281 rdmsr(MSR_VIA_FCR, lo, hi);
283 wrmsr(MSR_VIA_FCR, lo, hi);
284 set_cpu_cap(c, X86_FEATURE_CX8);
287 /* Before Nehemiah, the C3's had 3dNOW! */
288 if (c->x86_model >= 6 && c->x86_model < 9)
289 set_cpu_cap(c, X86_FEATURE_3DNOW);
291 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
292 c->x86_cache_alignment = c->x86_clflush_size * 2;
293 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
296 cpu_detect_cache_sizes(c);
320 static void early_init_centaur(struct cpuinfo_x86 *c)
325 /* Emulate MTRRs using Centaur's MCR. */
326 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
330 if (c->x86_model >= 0xf)
331 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
335 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
339 static void init_centaur(struct cpuinfo_x86 *c)
349 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
350 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
352 clear_cpu_cap(c, 0*32+31);
354 early_init_centaur(c);
358 switch (c->x86_model) {
361 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
363 printk(KERN_NOTICE "Disabling bugged TSC.\n");
364 clear_cpu_cap(c, X86_FEATURE_TSC);
365 #ifdef CONFIG_X86_OOSTORE
366 centaur_create_optimal_mcr();
369 * write combining on non-stack, non-string
370 * write combining on string, all types
371 * weak write ordering
373 * The C6 original lacks weak read order
375 * Note 0x120 is write only on Winchip 1
377 wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
381 switch (c->x86_mask) {
392 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
395 #ifdef CONFIG_X86_OOSTORE
396 winchip2_unprotect_mcr();
397 winchip2_create_optimal_mcr();
398 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
401 * write combining on non-stack, non-string
402 * write combining on string, all types
403 * weak write ordering
406 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
407 winchip2_protect_mcr();
412 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
415 #ifdef CONFIG_X86_OOSTORE
416 winchip2_unprotect_mcr();
417 winchip2_create_optimal_mcr();
418 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
421 * write combining on non-stack, non-string
422 * write combining on string, all types
423 * weak write ordering
426 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
427 winchip2_protect_mcr();
434 rdmsr(MSR_IDT_FCR1, lo, hi);
435 newlo = (lo|fcr_set) & (~fcr_clr);
438 printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n",
440 wrmsr(MSR_IDT_FCR1, newlo, hi);
442 printk(KERN_INFO "Centaur FCR is 0x%X\n", lo);
444 /* Emulate MTRRs using Centaur's MCR. */
445 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
447 set_cpu_cap(c, X86_FEATURE_CX8);
448 /* Set 3DNow! on Winchip 2 and above. */
449 if (c->x86_model >= 8)
450 set_cpu_cap(c, X86_FEATURE_3DNOW);
451 /* See if we can find out some more. */
452 if (cpuid_eax(0x80000000) >= 0x80000005) {
454 cpuid(0x80000005, &aa, &bb, &cc, &dd);
455 /* Add L1 data and code cache sizes. */
456 c->x86_cache_size = (cc>>24)+(dd>>24);
458 sprintf(c->x86_model_id, "WinChip %s", name);
466 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
472 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
474 /* VIA C3 CPUs (670-68F) need further shifting. */
475 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
479 * There's also an erratum in Nehemiah stepping 1, which
480 * returns '65KB' instead of '64KB'
481 * - Note, it seems this may only be in engineering samples.
483 if ((c->x86 == 6) && (c->x86_model == 9) &&
484 (c->x86_mask == 1) && (size == 65))
490 static const struct cpu_dev centaur_cpu_dev = {
491 .c_vendor = "Centaur",
492 .c_ident = { "CentaurHauls" },
493 .c_early_init = early_init_centaur,
494 .c_init = init_centaur,
496 .legacy_cache_size = centaur_size_cache,
498 .c_x86_vendor = X86_VENDOR_CENTAUR,
501 cpu_dev_register(centaur_cpu_dev);