1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/sched.h>
4 #include <linux/sched/clock.h>
6 #include <asm/cpufeature.h>
7 #include <asm/e820/api.h>
13 #define ACE_PRESENT (1 << 6)
14 #define ACE_ENABLED (1 << 7)
15 #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
17 #define RNG_PRESENT (1 << 2)
18 #define RNG_ENABLED (1 << 3)
19 #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
21 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
22 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
23 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
24 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
25 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
26 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
28 static void init_c3(struct cpuinfo_x86 *c)
32 /* Test for Centaur Extended Feature Flags presence */
33 if (cpuid_eax(0xC0000000) >= 0xC0000001) {
34 u32 tmp = cpuid_edx(0xC0000001);
36 /* enable ACE unit, if present and disabled */
37 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
38 rdmsr(MSR_VIA_FCR, lo, hi);
39 lo |= ACE_FCR; /* enable ACE unit */
40 wrmsr(MSR_VIA_FCR, lo, hi);
41 pr_info("CPU: Enabled ACE h/w crypto\n");
44 /* enable RNG unit, if present and disabled */
45 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
46 rdmsr(MSR_VIA_RNG, lo, hi);
47 lo |= RNG_ENABLE; /* enable RNG unit */
48 wrmsr(MSR_VIA_RNG, lo, hi);
49 pr_info("CPU: Enabled h/w RNG\n");
52 /* store Centaur Extended Feature Flags as
53 * word 5 of the CPU capability bit array
55 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
58 /* Cyrix III family needs CX8 & PGE explicitly enabled. */
59 if (c->x86_model >= 6 && c->x86_model <= 13) {
60 rdmsr(MSR_VIA_FCR, lo, hi);
62 wrmsr(MSR_VIA_FCR, lo, hi);
63 set_cpu_cap(c, X86_FEATURE_CX8);
66 /* Before Nehemiah, the C3's had 3dNOW! */
67 if (c->x86_model >= 6 && c->x86_model < 9)
68 set_cpu_cap(c, X86_FEATURE_3DNOW);
70 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
71 c->x86_cache_alignment = c->x86_clflush_size * 2;
72 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
75 cpu_detect_cache_sizes(c);
99 static void early_init_centaur(struct cpuinfo_x86 *c)
104 /* Emulate MTRRs using Centaur's MCR. */
105 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
109 if (c->x86_model >= 0xf)
110 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
114 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
116 if (c->x86_power & (1 << 8)) {
117 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
118 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
122 static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c)
124 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
126 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
127 msr_ctl = vmx_msr_high | vmx_msr_low;
129 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
130 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
131 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
132 set_cpu_cap(c, X86_FEATURE_VNMI);
133 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
134 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
135 vmx_msr_low, vmx_msr_high);
136 msr_ctl2 = vmx_msr_high | vmx_msr_low;
137 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
138 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
139 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
140 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
141 set_cpu_cap(c, X86_FEATURE_EPT);
142 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
143 set_cpu_cap(c, X86_FEATURE_VPID);
147 static void init_centaur(struct cpuinfo_x86 *c)
157 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
158 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
160 clear_cpu_cap(c, 0*32+31);
162 early_init_centaur(c);
163 init_intel_cacheinfo(c);
164 detect_num_cpu_cores(c);
169 if (c->cpuid_level > 9) {
170 unsigned int eax = cpuid_eax(10);
173 * Check for version and the number of counters
174 * Version(eax[7:0]) can't be 0;
175 * Counters(eax[15:8]) should be greater than 1;
177 if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
178 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
184 switch (c->x86_model) {
187 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
189 pr_notice("Disabling bugged TSC.\n");
190 clear_cpu_cap(c, X86_FEATURE_TSC);
193 switch (c->x86_stepping) {
204 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
210 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
218 rdmsr(MSR_IDT_FCR1, lo, hi);
219 newlo = (lo|fcr_set) & (~fcr_clr);
222 pr_info("Centaur FCR was 0x%X now 0x%X\n",
224 wrmsr(MSR_IDT_FCR1, newlo, hi);
226 pr_info("Centaur FCR is 0x%X\n", lo);
228 /* Emulate MTRRs using Centaur's MCR. */
229 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
231 set_cpu_cap(c, X86_FEATURE_CX8);
232 /* Set 3DNow! on Winchip 2 and above. */
233 if (c->x86_model >= 8)
234 set_cpu_cap(c, X86_FEATURE_3DNOW);
235 /* See if we can find out some more. */
236 if (cpuid_eax(0x80000000) >= 0x80000005) {
238 cpuid(0x80000005, &aa, &bb, &cc, &dd);
239 /* Add L1 data and code cache sizes. */
240 c->x86_cache_size = (cc>>24)+(dd>>24);
242 sprintf(c->x86_model_id, "WinChip %s", name);
250 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
253 if (cpu_has(c, X86_FEATURE_VMX))
254 centaur_detect_vmx_virtcap(c);
259 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
261 /* VIA C3 CPUs (670-68F) need further shifting. */
262 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
266 * There's also an erratum in Nehemiah stepping 1, which
267 * returns '65KB' instead of '64KB'
268 * - Note, it seems this may only be in engineering samples.
270 if ((c->x86 == 6) && (c->x86_model == 9) &&
271 (c->x86_stepping == 1) && (size == 65))
277 static const struct cpu_dev centaur_cpu_dev = {
278 .c_vendor = "Centaur",
279 .c_ident = { "CentaurHauls" },
280 .c_early_init = early_init_centaur,
281 .c_init = init_centaur,
283 .legacy_cache_size = centaur_size_cache,
285 .c_x86_vendor = X86_VENDOR_CENTAUR,
288 cpu_dev_register(centaur_cpu_dev);