arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17
  18 #include <asm/spec-ctrl.h>
  19 #include <asm/cmdline.h>
  20 #include <asm/bugs.h>
  21 #include <asm/processor.h>
  22 #include <asm/processor-flags.h>
  23 #include <asm/fpu/internal.h>
  24 #include <asm/msr.h>
  25 #include <asm/paravirt.h>
  26 #include <asm/alternative.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/set_memory.h>
  29 #include <asm/intel-family.h>
  30
  31 static void __init spectre_v2_select_mitigation(void);
  32 static void __init ssb_select_mitigation(void);
  33
  34 /*
  35  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  36  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  37  */
  38 u64 __ro_after_init x86_spec_ctrl_base;
  39 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  40
  41 /*
  42  * The vendor and possibly platform specific bits which can be modified in
  43  * x86_spec_ctrl_base.
  44  */
  45 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  46
  47 /*
  48  * AMD specific MSR info for Speculative Store Bypass control.
  49  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  50  */
  51 u64 __ro_after_init x86_amd_ls_cfg_base;
  52 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  53
  54 void __init check_bugs(void)
  55 {
  56         identify_boot_cpu();
  57
  58         if (!IS_ENABLED(CONFIG_SMP)) {
  59                 pr_info("CPU: ");
  60                 print_cpu_info(&boot_cpu_data);
  61         }
  62
  63         /*
  64          * Read the SPEC_CTRL MSR to account for reserved bits which may
  65          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  66          * init code as it is not enumerated and depends on the family.
  67          */
  68         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  69                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  70
  71         /* Allow STIBP in MSR_SPEC_CTRL if supported */
  72         if (boot_cpu_has(X86_FEATURE_STIBP))
  73                 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
  74
  75         /* Select the proper spectre mitigation before patching alternatives */
  76         spectre_v2_select_mitigation();
  77
  78         /*
  79          * Select proper mitigation for any exposure to the Speculative Store
  80          * Bypass vulnerability.
  81          */
  82         ssb_select_mitigation();
  83
  84 #ifdef CONFIG_X86_32
  85         /*
  86          * Check whether we are able to run this kernel safely on SMP.
  87          *
  88          * - i386 is no longer supported.
  89          * - In order to run on anything without a TSC, we need to be
  90          *   compiled for a i486.
  91          */
  92         if (boot_cpu_data.x86 < 4)
  93                 panic("Kernel requires i486+ for 'invlpg' and other features");
  94
  95         init_utsname()->machine[1] =
  96                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
  97         alternative_instructions();
  98
  99         fpu__init_check_bugs();
 100 #else /* CONFIG_X86_64 */
 101         alternative_instructions();
 102
 103         /*
 104          * Make sure the first 2MB area is not mapped by huge pages
 105          * There are typically fixed size MTRRs in there and overlapping
 106          * MTRRs into large pages causes slow downs.
 107          *
 108          * Right now we don't do that with gbpages because there seems
 109          * very little benefit for that case.
 110          */
 111         if (!direct_gbpages)
 112                 set_memory_4k((unsigned long)__va(0), 1);
 113 #endif
 114 }
 115
 116 /* The kernel command line selection */
 117 enum spectre_v2_mitigation_cmd {
 118         SPECTRE_V2_CMD_NONE,
 119         SPECTRE_V2_CMD_AUTO,
 120         SPECTRE_V2_CMD_FORCE,
 121         SPECTRE_V2_CMD_RETPOLINE,
 122         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 123         SPECTRE_V2_CMD_RETPOLINE_AMD,
 124 };
 125
 126 static const char *spectre_v2_strings[] = {
 127         [SPECTRE_V2_NONE]                       = "Vulnerable",
 128         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 129         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 130         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 131         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 132 };
 133
 134 #undef pr_fmt
 135 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 136
 137 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 138         SPECTRE_V2_NONE;
 139
 140 void
 141 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 142 {
 143         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 144         struct thread_info *ti = current_thread_info();
 145
 146         /* Is MSR_SPEC_CTRL implemented ? */
 147         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 148                 /*
 149                  * Restrict guest_spec_ctrl to supported values. Clear the
 150                  * modifiable bits in the host base value and or the
 151                  * modifiable bits from the guest value.
 152                  */
 153                 guestval = hostval & ~x86_spec_ctrl_mask;
 154                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 155
 156                 /* SSBD controlled in MSR_SPEC_CTRL */
 157                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
 158                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 159
 160                 if (hostval != guestval) {
 161                         msrval = setguest ? guestval : hostval;
 162                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 163                 }
 164         }
 165
 166         /*
 167          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 168          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 169          */
 170         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 171             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 172                 return;
 173
 174         /*
 175          * If the host has SSBD mitigation enabled, force it in the host's
 176          * virtual MSR value. If its not permanently enabled, evaluate
 177          * current's TIF_SSBD thread flag.
 178          */
 179         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 180                 hostval = SPEC_CTRL_SSBD;
 181         else
 182                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 183
 184         /* Sanitize the guest value */
 185         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 186
 187         if (hostval != guestval) {
 188                 unsigned long tif;
 189
 190                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 191                                  ssbd_spec_ctrl_to_tif(hostval);
 192
 193                 speculative_store_bypass_update(tif);
 194         }
 195 }
 196 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 197
 198 static void x86_amd_ssb_disable(void)
 199 {
 200         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 201
 202         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 203                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 204         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 205                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 206 }
 207
 208 #ifdef RETPOLINE
 209 static bool spectre_v2_bad_module;
 210
 211 bool retpoline_module_ok(bool has_retpoline)
 212 {
 213         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 214                 return true;
 215
 216         pr_err("System may be vulnerable to spectre v2\n");
 217         spectre_v2_bad_module = true;
 218         return false;
 219 }
 220
 221 static inline const char *spectre_v2_module_string(void)
 222 {
 223         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 224 }
 225 #else
 226 static inline const char *spectre_v2_module_string(void) { return ""; }
 227 #endif
 228
 229 static void __init spec2_print_if_insecure(const char *reason)
 230 {
 231         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 232                 pr_info("%s selected on command line.\n", reason);
 233 }
 234
 235 static void __init spec2_print_if_secure(const char *reason)
 236 {
 237         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 238                 pr_info("%s selected on command line.\n", reason);
 239 }
 240
 241 static inline bool retp_compiler(void)
 242 {
 243         return __is_defined(RETPOLINE);
 244 }
 245
 246 static inline bool match_option(const char *arg, int arglen, const char *opt)
 247 {
 248         int len = strlen(opt);
 249
 250         return len == arglen && !strncmp(arg, opt, len);
 251 }
 252
 253 static const struct {
 254         const char *option;
 255         enum spectre_v2_mitigation_cmd cmd;
 256         bool secure;
 257 } mitigation_options[] = {
 258         { "off",               SPECTRE_V2_CMD_NONE,              false },
 259         { "on",                SPECTRE_V2_CMD_FORCE,             true },
 260         { "retpoline",         SPECTRE_V2_CMD_RETPOLINE,         false },
 261         { "retpoline,amd",     SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 262         { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 263         { "auto",              SPECTRE_V2_CMD_AUTO,              false },
 264 };
 265
 266 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 267 {
 268         char arg[20];
 269         int ret, i;
 270         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 271
 272         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 273                 return SPECTRE_V2_CMD_NONE;
 274         else {
 275                 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 276                 if (ret < 0)
 277                         return SPECTRE_V2_CMD_AUTO;
 278
 279                 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 280                         if (!match_option(arg, ret, mitigation_options[i].option))
 281                                 continue;
 282                         cmd = mitigation_options[i].cmd;
 283                         break;
 284                 }
 285
 286                 if (i >= ARRAY_SIZE(mitigation_options)) {
 287                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 288                         return SPECTRE_V2_CMD_AUTO;
 289                 }
 290         }
 291
 292         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 293              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 294              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 295             !IS_ENABLED(CONFIG_RETPOLINE)) {
 296                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 297                 return SPECTRE_V2_CMD_AUTO;
 298         }
 299
 300         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 301             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 302                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 303                 return SPECTRE_V2_CMD_AUTO;
 304         }
 305
 306         if (mitigation_options[i].secure)
 307                 spec2_print_if_secure(mitigation_options[i].option);
 308         else
 309                 spec2_print_if_insecure(mitigation_options[i].option);
 310
 311         return cmd;
 312 }
 313
 314 /* Check for Skylake-like CPUs (for RSB handling) */
 315 static bool __init is_skylake_era(void)
 316 {
 317         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 318             boot_cpu_data.x86 == 6) {
 319                 switch (boot_cpu_data.x86_model) {
 320                 case INTEL_FAM6_SKYLAKE_MOBILE:
 321                 case INTEL_FAM6_SKYLAKE_DESKTOP:
 322                 case INTEL_FAM6_SKYLAKE_X:
 323                 case INTEL_FAM6_KABYLAKE_MOBILE:
 324                 case INTEL_FAM6_KABYLAKE_DESKTOP:
 325                         return true;
 326                 }
 327         }
 328         return false;
 329 }
 330
 331 static void __init spectre_v2_select_mitigation(void)
 332 {
 333         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 334         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 335
 336         /*
 337          * If the CPU is not affected and the command line mode is NONE or AUTO
 338          * then nothing to do.
 339          */
 340         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 341             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 342                 return;
 343
 344         switch (cmd) {
 345         case SPECTRE_V2_CMD_NONE:
 346                 return;
 347
 348         case SPECTRE_V2_CMD_FORCE:
 349         case SPECTRE_V2_CMD_AUTO:
 350                 if (IS_ENABLED(CONFIG_RETPOLINE))
 351                         goto retpoline_auto;
 352                 break;
 353         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 354                 if (IS_ENABLED(CONFIG_RETPOLINE))
 355                         goto retpoline_amd;
 356                 break;
 357         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 358                 if (IS_ENABLED(CONFIG_RETPOLINE))
 359                         goto retpoline_generic;
 360                 break;
 361         case SPECTRE_V2_CMD_RETPOLINE:
 362                 if (IS_ENABLED(CONFIG_RETPOLINE))
 363                         goto retpoline_auto;
 364                 break;
 365         }
 366         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 367         return;
 368
 369 retpoline_auto:
 370         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 371         retpoline_amd:
 372                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 373                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 374                         goto retpoline_generic;
 375                 }
 376                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 377                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 378                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 379                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 380         } else {
 381         retpoline_generic:
 382                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 383                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 384                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 385         }
 386
 387         spectre_v2_enabled = mode;
 388         pr_info("%s\n", spectre_v2_strings[mode]);
 389
 390         /*
 391          * If neither SMEP nor PTI are available, there is a risk of
 392          * hitting userspace addresses in the RSB after a context switch
 393          * from a shallow call stack to a deeper one. To prevent this fill
 394          * the entire RSB, even when using IBRS.
 395          *
 396          * Skylake era CPUs have a separate issue with *underflow* of the
 397          * RSB, when they will predict 'ret' targets from the generic BTB.
 398          * The proper mitigation for this is IBRS. If IBRS is not supported
 399          * or deactivated in favour of retpolines the RSB fill on context
 400          * switch is required.
 401          */
 402         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
 403              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
 404                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 405                 pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
 406         }
 407
 408         /* Initialize Indirect Branch Prediction Barrier if supported */
 409         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 410                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 411                 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
 412         }
 413
 414         /*
 415          * Retpoline means the kernel is safe because it has no indirect
 416          * branches. But firmware isn't, so use IBRS to protect that.
 417          */
 418         if (boot_cpu_has(X86_FEATURE_IBRS)) {
 419                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 420                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 421         }
 422 }
 423
 424 #undef pr_fmt
 425 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 426
 427 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 428
 429 /* The kernel command line selection */
 430 enum ssb_mitigation_cmd {
 431         SPEC_STORE_BYPASS_CMD_NONE,
 432         SPEC_STORE_BYPASS_CMD_AUTO,
 433         SPEC_STORE_BYPASS_CMD_ON,
 434         SPEC_STORE_BYPASS_CMD_PRCTL,
 435         SPEC_STORE_BYPASS_CMD_SECCOMP,
 436 };
 437
 438 static const char *ssb_strings[] = {
 439         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 440         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 441         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 442         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 443 };
 444
 445 static const struct {
 446         const char *option;
 447         enum ssb_mitigation_cmd cmd;
 448 } ssb_mitigation_options[] = {
 449         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 450         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 451         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 452         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 453         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 454 };
 455
 456 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 457 {
 458         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 459         char arg[20];
 460         int ret, i;
 461
 462         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 463                 return SPEC_STORE_BYPASS_CMD_NONE;
 464         } else {
 465                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 466                                           arg, sizeof(arg));
 467                 if (ret < 0)
 468                         return SPEC_STORE_BYPASS_CMD_AUTO;
 469
 470                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 471                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 472                                 continue;
 473
 474                         cmd = ssb_mitigation_options[i].cmd;
 475                         break;
 476                 }
 477
 478                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 479                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 480                         return SPEC_STORE_BYPASS_CMD_AUTO;
 481                 }
 482         }
 483
 484         return cmd;
 485 }
 486
 487 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 488 {
 489         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 490         enum ssb_mitigation_cmd cmd;
 491
 492         if (!boot_cpu_has(X86_FEATURE_SSBD))
 493                 return mode;
 494
 495         cmd = ssb_parse_cmdline();
 496         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 497             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 498              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 499                 return mode;
 500
 501         switch (cmd) {
 502         case SPEC_STORE_BYPASS_CMD_AUTO:
 503         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 504                 /*
 505                  * Choose prctl+seccomp as the default mode if seccomp is
 506                  * enabled.
 507                  */
 508                 if (IS_ENABLED(CONFIG_SECCOMP))
 509                         mode = SPEC_STORE_BYPASS_SECCOMP;
 510                 else
 511                         mode = SPEC_STORE_BYPASS_PRCTL;
 512                 break;
 513         case SPEC_STORE_BYPASS_CMD_ON:
 514                 mode = SPEC_STORE_BYPASS_DISABLE;
 515                 break;
 516         case SPEC_STORE_BYPASS_CMD_PRCTL:
 517                 mode = SPEC_STORE_BYPASS_PRCTL;
 518                 break;
 519         case SPEC_STORE_BYPASS_CMD_NONE:
 520                 break;
 521         }
 522
 523         /*
 524          * We have three CPU feature flags that are in play here:
 525          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 526          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 527          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 528          */
 529         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 530                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 531                 /*
 532                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
 533                  * a completely different MSR and bit dependent on family.
 534                  */
 535                 switch (boot_cpu_data.x86_vendor) {
 536                 case X86_VENDOR_INTEL:
 537                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 538                         x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
 539                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 540                         break;
 541                 case X86_VENDOR_AMD:
 542                         x86_amd_ssb_disable();
 543                         break;
 544                 }
 545         }
 546
 547         return mode;
 548 }
 549
 550 static void ssb_select_mitigation(void)
 551 {
 552         ssb_mode = __ssb_select_mitigation();
 553
 554         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 555                 pr_info("%s\n", ssb_strings[ssb_mode]);
 556 }
 557
 558 #undef pr_fmt
 559 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 560
 561 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 562 {
 563         bool update;
 564
 565         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 566             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 567                 return -ENXIO;
 568
 569         switch (ctrl) {
 570         case PR_SPEC_ENABLE:
 571                 /* If speculation is force disabled, enable is not allowed */
 572                 if (task_spec_ssb_force_disable(task))
 573                         return -EPERM;
 574                 task_clear_spec_ssb_disable(task);
 575                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 576                 break;
 577         case PR_SPEC_DISABLE:
 578                 task_set_spec_ssb_disable(task);
 579                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 580                 break;
 581         case PR_SPEC_FORCE_DISABLE:
 582                 task_set_spec_ssb_disable(task);
 583                 task_set_spec_ssb_force_disable(task);
 584                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 585                 break;
 586         default:
 587                 return -ERANGE;
 588         }
 589
 590         /*
 591          * If being set on non-current task, delay setting the CPU
 592          * mitigation until it is next scheduled.
 593          */
 594         if (task == current && update)
 595                 speculative_store_bypass_update_current();
 596
 597         return 0;
 598 }
 599
 600 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 601                              unsigned long ctrl)
 602 {
 603         switch (which) {
 604         case PR_SPEC_STORE_BYPASS:
 605                 return ssb_prctl_set(task, ctrl);
 606         default:
 607                 return -ENODEV;
 608         }
 609 }
 610
 611 #ifdef CONFIG_SECCOMP
 612 void arch_seccomp_spec_mitigate(struct task_struct *task)
 613 {
 614         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 615                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 616 }
 617 #endif
 618
 619 static int ssb_prctl_get(struct task_struct *task)
 620 {
 621         switch (ssb_mode) {
 622         case SPEC_STORE_BYPASS_DISABLE:
 623                 return PR_SPEC_DISABLE;
 624         case SPEC_STORE_BYPASS_SECCOMP:
 625         case SPEC_STORE_BYPASS_PRCTL:
 626                 if (task_spec_ssb_force_disable(task))
 627                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 628                 if (task_spec_ssb_disable(task))
 629                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 630                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 631         default:
 632                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 633                         return PR_SPEC_ENABLE;
 634                 return PR_SPEC_NOT_AFFECTED;
 635         }
 636 }
 637
 638 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 639 {
 640         switch (which) {
 641         case PR_SPEC_STORE_BYPASS:
 642                 return ssb_prctl_get(task);
 643         default:
 644                 return -ENODEV;
 645         }
 646 }
 647
 648 void x86_spec_ctrl_setup_ap(void)
 649 {
 650         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 651                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 652
 653         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 654                 x86_amd_ssb_disable();
 655 }
 656
 657 #ifdef CONFIG_SYSFS
 658
 659 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 660                                char *buf, unsigned int bug)
 661 {
 662         if (!boot_cpu_has_bug(bug))
 663                 return sprintf(buf, "Not affected\n");
 664
 665         switch (bug) {
 666         case X86_BUG_CPU_MELTDOWN:
 667                 if (boot_cpu_has(X86_FEATURE_PTI))
 668                         return sprintf(buf, "Mitigation: PTI\n");
 669
 670                 break;
 671
 672         case X86_BUG_SPECTRE_V1:
 673                 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
 674
 675         case X86_BUG_SPECTRE_V2:
 676                 return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
 677                                boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
 678                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
 679                                spectre_v2_module_string());
 680
 681         case X86_BUG_SPEC_STORE_BYPASS:
 682                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 683
 684         default:
 685                 break;
 686         }
 687
 688         return sprintf(buf, "Vulnerable\n");
 689 }
 690
 691 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
 692 {
 693         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 694 }
 695
 696 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
 697 {
 698         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 699 }
 700
 701 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
 702 {
 703         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 704 }
 705
 706 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 707 {
 708         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 709 }
 710 #endif