1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
18 #include <linux/pgtable.h>
20 #include <asm/spec-ctrl.h>
21 #include <asm/cmdline.h>
23 #include <asm/processor.h>
24 #include <asm/processor-flags.h>
25 #include <asm/fpu/internal.h>
28 #include <asm/paravirt.h>
29 #include <asm/alternative.h>
30 #include <asm/set_memory.h>
31 #include <asm/intel-family.h>
32 #include <asm/e820/api.h>
33 #include <asm/hypervisor.h>
34 #include <asm/tlbflush.h>
38 static void __init spectre_v1_select_mitigation(void);
39 static void __init spectre_v2_select_mitigation(void);
40 static void __init ssb_select_mitigation(void);
41 static void __init l1tf_select_mitigation(void);
42 static void __init mds_select_mitigation(void);
43 static void __init mds_print_mitigation(void);
44 static void __init taa_select_mitigation(void);
45 static void __init srbds_select_mitigation(void);
47 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
48 u64 x86_spec_ctrl_base;
49 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
50 static DEFINE_MUTEX(spec_ctrl_mutex);
53 * The vendor and possibly platform specific bits which can be modified in
56 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
59 * AMD specific MSR info for Speculative Store Bypass control.
60 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
62 u64 __ro_after_init x86_amd_ls_cfg_base;
63 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
65 /* Control conditional STIBP in switch_to() */
66 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
67 /* Control conditional IBPB in switch_mm() */
68 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
69 /* Control unconditional IBPB in switch_mm() */
70 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
72 /* Control MDS CPU buffer clear before returning to user space */
73 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
74 EXPORT_SYMBOL_GPL(mds_user_clear);
75 /* Control MDS CPU buffer clear before idling (halt, mwait) */
76 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
77 EXPORT_SYMBOL_GPL(mds_idle_clear);
79 void __init check_bugs(void)
84 * identify_boot_cpu() initialized SMT support information, let the
87 cpu_smt_check_topology();
89 if (!IS_ENABLED(CONFIG_SMP)) {
91 print_cpu_info(&boot_cpu_data);
95 * Read the SPEC_CTRL MSR to account for reserved bits which may
96 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
97 * init code as it is not enumerated and depends on the family.
99 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
100 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
102 /* Allow STIBP in MSR_SPEC_CTRL if supported */
103 if (boot_cpu_has(X86_FEATURE_STIBP))
104 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
106 /* Select the proper CPU mitigations before patching alternatives: */
107 spectre_v1_select_mitigation();
108 spectre_v2_select_mitigation();
109 ssb_select_mitigation();
110 l1tf_select_mitigation();
111 mds_select_mitigation();
112 taa_select_mitigation();
113 srbds_select_mitigation();
116 * As MDS and TAA mitigations are inter-related, print MDS
117 * mitigation until after TAA mitigation selection is done.
119 mds_print_mitigation();
125 * Check whether we are able to run this kernel safely on SMP.
127 * - i386 is no longer supported.
128 * - In order to run on anything without a TSC, we need to be
129 * compiled for a i486.
131 if (boot_cpu_data.x86 < 4)
132 panic("Kernel requires i486+ for 'invlpg' and other features");
134 init_utsname()->machine[1] =
135 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
136 alternative_instructions();
138 fpu__init_check_bugs();
139 #else /* CONFIG_X86_64 */
140 alternative_instructions();
143 * Make sure the first 2MB area is not mapped by huge pages
144 * There are typically fixed size MTRRs in there and overlapping
145 * MTRRs into large pages causes slow downs.
147 * Right now we don't do that with gbpages because there seems
148 * very little benefit for that case.
151 set_memory_4k((unsigned long)__va(0), 1);
156 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
158 u64 msrval, guestval, hostval = x86_spec_ctrl_base;
159 struct thread_info *ti = current_thread_info();
161 /* Is MSR_SPEC_CTRL implemented ? */
162 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
164 * Restrict guest_spec_ctrl to supported values. Clear the
165 * modifiable bits in the host base value and or the
166 * modifiable bits from the guest value.
168 guestval = hostval & ~x86_spec_ctrl_mask;
169 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
171 /* SSBD controlled in MSR_SPEC_CTRL */
172 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
173 static_cpu_has(X86_FEATURE_AMD_SSBD))
174 hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
176 /* Conditional STIBP enabled? */
177 if (static_branch_unlikely(&switch_to_cond_stibp))
178 hostval |= stibp_tif_to_spec_ctrl(ti->flags);
180 if (hostval != guestval) {
181 msrval = setguest ? guestval : hostval;
182 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
187 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
188 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
190 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
191 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
195 * If the host has SSBD mitigation enabled, force it in the host's
196 * virtual MSR value. If its not permanently enabled, evaluate
197 * current's TIF_SSBD thread flag.
199 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
200 hostval = SPEC_CTRL_SSBD;
202 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
204 /* Sanitize the guest value */
205 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
207 if (hostval != guestval) {
210 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
211 ssbd_spec_ctrl_to_tif(hostval);
213 speculation_ctrl_update(tif);
216 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
218 static void x86_amd_ssb_disable(void)
220 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
222 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
223 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
224 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
225 wrmsrl(MSR_AMD64_LS_CFG, msrval);
229 #define pr_fmt(fmt) "MDS: " fmt
231 /* Default mitigation for MDS-affected CPUs */
232 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
233 static bool mds_nosmt __ro_after_init = false;
235 static const char * const mds_strings[] = {
236 [MDS_MITIGATION_OFF] = "Vulnerable",
237 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers",
238 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
241 static void __init mds_select_mitigation(void)
243 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
244 mds_mitigation = MDS_MITIGATION_OFF;
248 if (mds_mitigation == MDS_MITIGATION_FULL) {
249 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
250 mds_mitigation = MDS_MITIGATION_VMWERV;
252 static_branch_enable(&mds_user_clear);
254 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
255 (mds_nosmt || cpu_mitigations_auto_nosmt()))
256 cpu_smt_disable(false);
260 static void __init mds_print_mitigation(void)
262 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off())
265 pr_info("%s\n", mds_strings[mds_mitigation]);
268 static int __init mds_cmdline(char *str)
270 if (!boot_cpu_has_bug(X86_BUG_MDS))
276 if (!strcmp(str, "off"))
277 mds_mitigation = MDS_MITIGATION_OFF;
278 else if (!strcmp(str, "full"))
279 mds_mitigation = MDS_MITIGATION_FULL;
280 else if (!strcmp(str, "full,nosmt")) {
281 mds_mitigation = MDS_MITIGATION_FULL;
287 early_param("mds", mds_cmdline);
290 #define pr_fmt(fmt) "TAA: " fmt
292 enum taa_mitigations {
294 TAA_MITIGATION_UCODE_NEEDED,
296 TAA_MITIGATION_TSX_DISABLED,
299 /* Default mitigation for TAA-affected CPUs */
300 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
301 static bool taa_nosmt __ro_after_init;
303 static const char * const taa_strings[] = {
304 [TAA_MITIGATION_OFF] = "Vulnerable",
305 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
306 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
307 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled",
310 static void __init taa_select_mitigation(void)
314 if (!boot_cpu_has_bug(X86_BUG_TAA)) {
315 taa_mitigation = TAA_MITIGATION_OFF;
319 /* TSX previously disabled by tsx=off */
320 if (!boot_cpu_has(X86_FEATURE_RTM)) {
321 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
325 if (cpu_mitigations_off()) {
326 taa_mitigation = TAA_MITIGATION_OFF;
331 * TAA mitigation via VERW is turned off if both
332 * tsx_async_abort=off and mds=off are specified.
334 if (taa_mitigation == TAA_MITIGATION_OFF &&
335 mds_mitigation == MDS_MITIGATION_OFF)
338 if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
339 taa_mitigation = TAA_MITIGATION_VERW;
341 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
344 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
345 * A microcode update fixes this behavior to clear CPU buffers. It also
346 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
347 * ARCH_CAP_TSX_CTRL_MSR bit.
349 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
350 * update is required.
352 ia32_cap = x86_read_arch_cap_msr();
353 if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
354 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
355 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
358 * TSX is enabled, select alternate mitigation for TAA which is
359 * the same as MDS. Enable MDS static branch to clear CPU buffers.
361 * For guests that can't determine whether the correct microcode is
362 * present on host, enable the mitigation for UCODE_NEEDED as well.
364 static_branch_enable(&mds_user_clear);
366 if (taa_nosmt || cpu_mitigations_auto_nosmt())
367 cpu_smt_disable(false);
370 * Update MDS mitigation, if necessary, as the mds_user_clear is
371 * now enabled for TAA mitigation.
373 if (mds_mitigation == MDS_MITIGATION_OFF &&
374 boot_cpu_has_bug(X86_BUG_MDS)) {
375 mds_mitigation = MDS_MITIGATION_FULL;
376 mds_select_mitigation();
379 pr_info("%s\n", taa_strings[taa_mitigation]);
382 static int __init tsx_async_abort_parse_cmdline(char *str)
384 if (!boot_cpu_has_bug(X86_BUG_TAA))
390 if (!strcmp(str, "off")) {
391 taa_mitigation = TAA_MITIGATION_OFF;
392 } else if (!strcmp(str, "full")) {
393 taa_mitigation = TAA_MITIGATION_VERW;
394 } else if (!strcmp(str, "full,nosmt")) {
395 taa_mitigation = TAA_MITIGATION_VERW;
401 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
404 #define pr_fmt(fmt) "SRBDS: " fmt
406 enum srbds_mitigations {
407 SRBDS_MITIGATION_OFF,
408 SRBDS_MITIGATION_UCODE_NEEDED,
409 SRBDS_MITIGATION_FULL,
410 SRBDS_MITIGATION_TSX_OFF,
411 SRBDS_MITIGATION_HYPERVISOR,
414 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
416 static const char * const srbds_strings[] = {
417 [SRBDS_MITIGATION_OFF] = "Vulnerable",
418 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
419 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
420 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
421 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
424 static bool srbds_off;
426 void update_srbds_msr(void)
430 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
433 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
436 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
439 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
441 switch (srbds_mitigation) {
442 case SRBDS_MITIGATION_OFF:
443 case SRBDS_MITIGATION_TSX_OFF:
444 mcu_ctrl |= RNGDS_MITG_DIS;
446 case SRBDS_MITIGATION_FULL:
447 mcu_ctrl &= ~RNGDS_MITG_DIS;
453 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
456 static void __init srbds_select_mitigation(void)
460 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
464 * Check to see if this is one of the MDS_NO systems supporting
465 * TSX that are only exposed to SRBDS when TSX is enabled.
467 ia32_cap = x86_read_arch_cap_msr();
468 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM))
469 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
470 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
471 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
472 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
473 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
474 else if (cpu_mitigations_off() || srbds_off)
475 srbds_mitigation = SRBDS_MITIGATION_OFF;
478 pr_info("%s\n", srbds_strings[srbds_mitigation]);
481 static int __init srbds_parse_cmdline(char *str)
486 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
489 srbds_off = !strcmp(str, "off");
492 early_param("srbds", srbds_parse_cmdline);
495 #define pr_fmt(fmt) "Spectre V1 : " fmt
497 enum spectre_v1_mitigation {
498 SPECTRE_V1_MITIGATION_NONE,
499 SPECTRE_V1_MITIGATION_AUTO,
502 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
503 SPECTRE_V1_MITIGATION_AUTO;
505 static const char * const spectre_v1_strings[] = {
506 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
507 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
511 * Does SMAP provide full mitigation against speculative kernel access to
514 static bool smap_works_speculatively(void)
516 if (!boot_cpu_has(X86_FEATURE_SMAP))
520 * On CPUs which are vulnerable to Meltdown, SMAP does not
521 * prevent speculative access to user data in the L1 cache.
522 * Consider SMAP to be non-functional as a mitigation on these
525 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
531 static void __init spectre_v1_select_mitigation(void)
533 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
534 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
538 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
540 * With Spectre v1, a user can speculatively control either
541 * path of a conditional swapgs with a user-controlled GS
542 * value. The mitigation is to add lfences to both code paths.
544 * If FSGSBASE is enabled, the user can put a kernel address in
545 * GS, in which case SMAP provides no protection.
547 * If FSGSBASE is disabled, the user can only put a user space
548 * address in GS. That makes an attack harder, but still
549 * possible if there's no SMAP protection.
551 if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
552 !smap_works_speculatively()) {
554 * Mitigation can be provided from SWAPGS itself or
555 * PTI as the CR3 write in the Meltdown mitigation
558 * If neither is there, mitigate with an LFENCE to
559 * stop speculation through swapgs.
561 if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
562 !boot_cpu_has(X86_FEATURE_PTI))
563 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
566 * Enable lfences in the kernel entry (non-swapgs)
567 * paths, to prevent user entry from speculatively
570 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
574 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
577 static int __init nospectre_v1_cmdline(char *str)
579 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
582 early_param("nospectre_v1", nospectre_v1_cmdline);
585 #define pr_fmt(fmt) "Spectre V2 : " fmt
587 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
590 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
591 SPECTRE_V2_USER_NONE;
592 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
593 SPECTRE_V2_USER_NONE;
595 #ifdef CONFIG_RETPOLINE
596 static bool spectre_v2_bad_module;
598 bool retpoline_module_ok(bool has_retpoline)
600 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
603 pr_err("System may be vulnerable to spectre v2\n");
604 spectre_v2_bad_module = true;
608 static inline const char *spectre_v2_module_string(void)
610 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
613 static inline const char *spectre_v2_module_string(void) { return ""; }
616 static inline bool match_option(const char *arg, int arglen, const char *opt)
618 int len = strlen(opt);
620 return len == arglen && !strncmp(arg, opt, len);
623 /* The kernel command line selection for spectre v2 */
624 enum spectre_v2_mitigation_cmd {
627 SPECTRE_V2_CMD_FORCE,
628 SPECTRE_V2_CMD_RETPOLINE,
629 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
630 SPECTRE_V2_CMD_RETPOLINE_AMD,
633 enum spectre_v2_user_cmd {
634 SPECTRE_V2_USER_CMD_NONE,
635 SPECTRE_V2_USER_CMD_AUTO,
636 SPECTRE_V2_USER_CMD_FORCE,
637 SPECTRE_V2_USER_CMD_PRCTL,
638 SPECTRE_V2_USER_CMD_PRCTL_IBPB,
639 SPECTRE_V2_USER_CMD_SECCOMP,
640 SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
643 static const char * const spectre_v2_user_strings[] = {
644 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable",
645 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection",
646 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection",
647 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl",
648 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl",
651 static const struct {
653 enum spectre_v2_user_cmd cmd;
655 } v2_user_options[] __initconst = {
656 { "auto", SPECTRE_V2_USER_CMD_AUTO, false },
657 { "off", SPECTRE_V2_USER_CMD_NONE, false },
658 { "on", SPECTRE_V2_USER_CMD_FORCE, true },
659 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false },
660 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false },
661 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false },
662 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false },
665 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
667 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
668 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
671 static enum spectre_v2_user_cmd __init
672 spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd)
678 case SPECTRE_V2_CMD_NONE:
679 return SPECTRE_V2_USER_CMD_NONE;
680 case SPECTRE_V2_CMD_FORCE:
681 return SPECTRE_V2_USER_CMD_FORCE;
686 ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
689 return SPECTRE_V2_USER_CMD_AUTO;
691 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
692 if (match_option(arg, ret, v2_user_options[i].option)) {
693 spec_v2_user_print_cond(v2_user_options[i].option,
694 v2_user_options[i].secure);
695 return v2_user_options[i].cmd;
699 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
700 return SPECTRE_V2_USER_CMD_AUTO;
704 spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd)
706 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
707 bool smt_possible = IS_ENABLED(CONFIG_SMP);
708 enum spectre_v2_user_cmd cmd;
710 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
713 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
714 cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
715 smt_possible = false;
717 cmd = spectre_v2_parse_user_cmdline(v2_cmd);
719 case SPECTRE_V2_USER_CMD_NONE:
721 case SPECTRE_V2_USER_CMD_FORCE:
722 mode = SPECTRE_V2_USER_STRICT;
724 case SPECTRE_V2_USER_CMD_PRCTL:
725 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
726 mode = SPECTRE_V2_USER_PRCTL;
728 case SPECTRE_V2_USER_CMD_AUTO:
729 case SPECTRE_V2_USER_CMD_SECCOMP:
730 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
731 if (IS_ENABLED(CONFIG_SECCOMP))
732 mode = SPECTRE_V2_USER_SECCOMP;
734 mode = SPECTRE_V2_USER_PRCTL;
738 /* Initialize Indirect Branch Prediction Barrier */
739 if (boot_cpu_has(X86_FEATURE_IBPB)) {
740 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
742 spectre_v2_user_ibpb = mode;
744 case SPECTRE_V2_USER_CMD_FORCE:
745 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
746 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
747 static_branch_enable(&switch_mm_always_ibpb);
748 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
750 case SPECTRE_V2_USER_CMD_PRCTL:
751 case SPECTRE_V2_USER_CMD_AUTO:
752 case SPECTRE_V2_USER_CMD_SECCOMP:
753 static_branch_enable(&switch_mm_cond_ibpb);
759 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
760 static_key_enabled(&switch_mm_always_ibpb) ?
761 "always-on" : "conditional");
765 * If no STIBP, enhanced IBRS is enabled or SMT impossible, STIBP is not
768 if (!boot_cpu_has(X86_FEATURE_STIBP) ||
770 spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
774 * At this point, an STIBP mode other than "off" has been set.
775 * If STIBP support is not being forced, check if STIBP always-on
778 if (mode != SPECTRE_V2_USER_STRICT &&
779 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
780 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
782 spectre_v2_user_stibp = mode;
785 pr_info("%s\n", spectre_v2_user_strings[mode]);
788 static const char * const spectre_v2_strings[] = {
789 [SPECTRE_V2_NONE] = "Vulnerable",
790 [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline",
791 [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline",
792 [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS",
795 static const struct {
797 enum spectre_v2_mitigation_cmd cmd;
799 } mitigation_options[] __initconst = {
800 { "off", SPECTRE_V2_CMD_NONE, false },
801 { "on", SPECTRE_V2_CMD_FORCE, true },
802 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
803 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false },
804 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
805 { "auto", SPECTRE_V2_CMD_AUTO, false },
808 static void __init spec_v2_print_cond(const char *reason, bool secure)
810 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
811 pr_info("%s selected on command line.\n", reason);
814 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
816 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
820 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
821 cpu_mitigations_off())
822 return SPECTRE_V2_CMD_NONE;
824 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
826 return SPECTRE_V2_CMD_AUTO;
828 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
829 if (!match_option(arg, ret, mitigation_options[i].option))
831 cmd = mitigation_options[i].cmd;
835 if (i >= ARRAY_SIZE(mitigation_options)) {
836 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
837 return SPECTRE_V2_CMD_AUTO;
840 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
841 cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
842 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
843 !IS_ENABLED(CONFIG_RETPOLINE)) {
844 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
845 return SPECTRE_V2_CMD_AUTO;
848 if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
849 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON &&
850 boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
851 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
852 return SPECTRE_V2_CMD_AUTO;
855 spec_v2_print_cond(mitigation_options[i].option,
856 mitigation_options[i].secure);
860 static void __init spectre_v2_select_mitigation(void)
862 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
863 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
866 * If the CPU is not affected and the command line mode is NONE or AUTO
867 * then nothing to do.
869 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
870 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
874 case SPECTRE_V2_CMD_NONE:
877 case SPECTRE_V2_CMD_FORCE:
878 case SPECTRE_V2_CMD_AUTO:
879 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
880 mode = SPECTRE_V2_IBRS_ENHANCED;
881 /* Force it so VMEXIT will restore correctly */
882 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
883 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
884 goto specv2_set_mode;
886 if (IS_ENABLED(CONFIG_RETPOLINE))
889 case SPECTRE_V2_CMD_RETPOLINE_AMD:
890 if (IS_ENABLED(CONFIG_RETPOLINE))
893 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
894 if (IS_ENABLED(CONFIG_RETPOLINE))
895 goto retpoline_generic;
897 case SPECTRE_V2_CMD_RETPOLINE:
898 if (IS_ENABLED(CONFIG_RETPOLINE))
902 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
906 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
907 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
909 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
910 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
911 goto retpoline_generic;
913 mode = SPECTRE_V2_RETPOLINE_AMD;
914 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
915 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
918 mode = SPECTRE_V2_RETPOLINE_GENERIC;
919 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
923 spectre_v2_enabled = mode;
924 pr_info("%s\n", spectre_v2_strings[mode]);
927 * If spectre v2 protection has been enabled, unconditionally fill
928 * RSB during a context switch; this protects against two independent
931 * - RSB underflow (and switch to BTB) on Skylake+
932 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
934 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
935 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
938 * Retpoline means the kernel is safe because it has no indirect
939 * branches. Enhanced IBRS protects firmware too, so, enable restricted
940 * speculation around firmware calls only when Enhanced IBRS isn't
943 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
944 * the user might select retpoline on the kernel command line and if
945 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
946 * enable IBRS around firmware calls.
948 if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
949 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
950 pr_info("Enabling Restricted Speculation for firmware calls\n");
953 /* Set up IBPB and STIBP depending on the general spectre V2 command */
954 spectre_v2_user_select_mitigation(cmd);
957 static void update_stibp_msr(void * __unused)
959 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
962 /* Update x86_spec_ctrl_base in case SMT state changed. */
963 static void update_stibp_strict(void)
965 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
967 if (sched_smt_active())
968 mask |= SPEC_CTRL_STIBP;
970 if (mask == x86_spec_ctrl_base)
973 pr_info("Update user space SMT mitigation: STIBP %s\n",
974 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
975 x86_spec_ctrl_base = mask;
976 on_each_cpu(update_stibp_msr, NULL, 1);
979 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
980 static void update_indir_branch_cond(void)
982 if (sched_smt_active())
983 static_branch_enable(&switch_to_cond_stibp);
985 static_branch_disable(&switch_to_cond_stibp);
989 #define pr_fmt(fmt) fmt
991 /* Update the static key controlling the MDS CPU buffer clear in idle */
992 static void update_mds_branch_idle(void)
995 * Enable the idle clearing if SMT is active on CPUs which are
996 * affected only by MSBDS and not any other MDS variant.
998 * The other variants cannot be mitigated when SMT is enabled, so
999 * clearing the buffers on idle just to prevent the Store Buffer
1000 * repartitioning leak would be a window dressing exercise.
1002 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1005 if (sched_smt_active())
1006 static_branch_enable(&mds_idle_clear);
1008 static_branch_disable(&mds_idle_clear);
1011 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1012 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1014 void cpu_bugs_smt_update(void)
1016 mutex_lock(&spec_ctrl_mutex);
1018 switch (spectre_v2_user_stibp) {
1019 case SPECTRE_V2_USER_NONE:
1021 case SPECTRE_V2_USER_STRICT:
1022 case SPECTRE_V2_USER_STRICT_PREFERRED:
1023 update_stibp_strict();
1025 case SPECTRE_V2_USER_PRCTL:
1026 case SPECTRE_V2_USER_SECCOMP:
1027 update_indir_branch_cond();
1031 switch (mds_mitigation) {
1032 case MDS_MITIGATION_FULL:
1033 case MDS_MITIGATION_VMWERV:
1034 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1035 pr_warn_once(MDS_MSG_SMT);
1036 update_mds_branch_idle();
1038 case MDS_MITIGATION_OFF:
1042 switch (taa_mitigation) {
1043 case TAA_MITIGATION_VERW:
1044 case TAA_MITIGATION_UCODE_NEEDED:
1045 if (sched_smt_active())
1046 pr_warn_once(TAA_MSG_SMT);
1048 case TAA_MITIGATION_TSX_DISABLED:
1049 case TAA_MITIGATION_OFF:
1053 mutex_unlock(&spec_ctrl_mutex);
1057 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
1059 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1061 /* The kernel command line selection */
1062 enum ssb_mitigation_cmd {
1063 SPEC_STORE_BYPASS_CMD_NONE,
1064 SPEC_STORE_BYPASS_CMD_AUTO,
1065 SPEC_STORE_BYPASS_CMD_ON,
1066 SPEC_STORE_BYPASS_CMD_PRCTL,
1067 SPEC_STORE_BYPASS_CMD_SECCOMP,
1070 static const char * const ssb_strings[] = {
1071 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
1072 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
1073 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
1074 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1077 static const struct {
1079 enum ssb_mitigation_cmd cmd;
1080 } ssb_mitigation_options[] __initconst = {
1081 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
1082 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
1083 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
1084 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
1085 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1088 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1090 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1094 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1095 cpu_mitigations_off()) {
1096 return SPEC_STORE_BYPASS_CMD_NONE;
1098 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1101 return SPEC_STORE_BYPASS_CMD_AUTO;
1103 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1104 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1107 cmd = ssb_mitigation_options[i].cmd;
1111 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1112 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1113 return SPEC_STORE_BYPASS_CMD_AUTO;
1120 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1122 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1123 enum ssb_mitigation_cmd cmd;
1125 if (!boot_cpu_has(X86_FEATURE_SSBD))
1128 cmd = ssb_parse_cmdline();
1129 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1130 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1131 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1135 case SPEC_STORE_BYPASS_CMD_AUTO:
1136 case SPEC_STORE_BYPASS_CMD_SECCOMP:
1138 * Choose prctl+seccomp as the default mode if seccomp is
1141 if (IS_ENABLED(CONFIG_SECCOMP))
1142 mode = SPEC_STORE_BYPASS_SECCOMP;
1144 mode = SPEC_STORE_BYPASS_PRCTL;
1146 case SPEC_STORE_BYPASS_CMD_ON:
1147 mode = SPEC_STORE_BYPASS_DISABLE;
1149 case SPEC_STORE_BYPASS_CMD_PRCTL:
1150 mode = SPEC_STORE_BYPASS_PRCTL;
1152 case SPEC_STORE_BYPASS_CMD_NONE:
1157 * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
1158 * bit in the mask to allow guests to use the mitigation even in the
1159 * case where the host does not enable it.
1161 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
1162 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1163 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
1167 * We have three CPU feature flags that are in play here:
1168 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1169 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1170 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1172 if (mode == SPEC_STORE_BYPASS_DISABLE) {
1173 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1175 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1176 * use a completely different MSR and bit dependent on family.
1178 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1179 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1180 x86_amd_ssb_disable();
1182 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1183 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1190 static void ssb_select_mitigation(void)
1192 ssb_mode = __ssb_select_mitigation();
1194 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1195 pr_info("%s\n", ssb_strings[ssb_mode]);
1199 #define pr_fmt(fmt) "Speculation prctl: " fmt
1201 static void task_update_spec_tif(struct task_struct *tsk)
1203 /* Force the update of the real TIF bits */
1204 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1207 * Immediately update the speculation control MSRs for the current
1208 * task, but for a non-current task delay setting the CPU
1209 * mitigation until it is scheduled next.
1211 * This can only happen for SECCOMP mitigation. For PRCTL it's
1212 * always the current task.
1215 speculation_ctrl_update_current();
1218 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1220 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1221 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1225 case PR_SPEC_ENABLE:
1226 /* If speculation is force disabled, enable is not allowed */
1227 if (task_spec_ssb_force_disable(task))
1229 task_clear_spec_ssb_disable(task);
1230 task_clear_spec_ssb_noexec(task);
1231 task_update_spec_tif(task);
1233 case PR_SPEC_DISABLE:
1234 task_set_spec_ssb_disable(task);
1235 task_clear_spec_ssb_noexec(task);
1236 task_update_spec_tif(task);
1238 case PR_SPEC_FORCE_DISABLE:
1239 task_set_spec_ssb_disable(task);
1240 task_set_spec_ssb_force_disable(task);
1241 task_clear_spec_ssb_noexec(task);
1242 task_update_spec_tif(task);
1244 case PR_SPEC_DISABLE_NOEXEC:
1245 if (task_spec_ssb_force_disable(task))
1247 task_set_spec_ssb_disable(task);
1248 task_set_spec_ssb_noexec(task);
1249 task_update_spec_tif(task);
1257 static bool is_spec_ib_user_controlled(void)
1259 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1260 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1261 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1262 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1265 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1268 case PR_SPEC_ENABLE:
1269 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1270 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1274 * With strict mode for both IBPB and STIBP, the instruction
1275 * code paths avoid checking this task flag and instead,
1276 * unconditionally run the instruction. However, STIBP and IBPB
1277 * are independent and either can be set to conditionally
1278 * enabled regardless of the mode of the other.
1280 * If either is set to conditional, allow the task flag to be
1281 * updated, unless it was force-disabled by a previous prctl
1282 * call. Currently, this is possible on an AMD CPU which has the
1283 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1284 * kernel is booted with 'spectre_v2_user=seccomp', then
1285 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1286 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1288 if (!is_spec_ib_user_controlled() ||
1289 task_spec_ib_force_disable(task))
1292 task_clear_spec_ib_disable(task);
1293 task_update_spec_tif(task);
1295 case PR_SPEC_DISABLE:
1296 case PR_SPEC_FORCE_DISABLE:
1298 * Indirect branch speculation is always allowed when
1299 * mitigation is force disabled.
1301 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1302 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1305 if (!is_spec_ib_user_controlled())
1308 task_set_spec_ib_disable(task);
1309 if (ctrl == PR_SPEC_FORCE_DISABLE)
1310 task_set_spec_ib_force_disable(task);
1311 task_update_spec_tif(task);
1319 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1323 case PR_SPEC_STORE_BYPASS:
1324 return ssb_prctl_set(task, ctrl);
1325 case PR_SPEC_INDIRECT_BRANCH:
1326 return ib_prctl_set(task, ctrl);
1332 #ifdef CONFIG_SECCOMP
1333 void arch_seccomp_spec_mitigate(struct task_struct *task)
1335 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1336 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1337 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1338 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1339 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1343 static int ssb_prctl_get(struct task_struct *task)
1346 case SPEC_STORE_BYPASS_DISABLE:
1347 return PR_SPEC_DISABLE;
1348 case SPEC_STORE_BYPASS_SECCOMP:
1349 case SPEC_STORE_BYPASS_PRCTL:
1350 if (task_spec_ssb_force_disable(task))
1351 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1352 if (task_spec_ssb_noexec(task))
1353 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
1354 if (task_spec_ssb_disable(task))
1355 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1356 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1358 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1359 return PR_SPEC_ENABLE;
1360 return PR_SPEC_NOT_AFFECTED;
1364 static int ib_prctl_get(struct task_struct *task)
1366 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1367 return PR_SPEC_NOT_AFFECTED;
1369 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1370 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1371 return PR_SPEC_ENABLE;
1372 else if (is_spec_ib_user_controlled()) {
1373 if (task_spec_ib_force_disable(task))
1374 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1375 if (task_spec_ib_disable(task))
1376 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1377 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1378 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1379 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1380 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1381 return PR_SPEC_DISABLE;
1383 return PR_SPEC_NOT_AFFECTED;
1386 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1389 case PR_SPEC_STORE_BYPASS:
1390 return ssb_prctl_get(task);
1391 case PR_SPEC_INDIRECT_BRANCH:
1392 return ib_prctl_get(task);
1398 void x86_spec_ctrl_setup_ap(void)
1400 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
1401 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
1403 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
1404 x86_amd_ssb_disable();
1407 bool itlb_multihit_kvm_mitigation;
1408 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
1411 #define pr_fmt(fmt) "L1TF: " fmt
1413 /* Default mitigation for L1TF-affected CPUs */
1414 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
1415 #if IS_ENABLED(CONFIG_KVM_INTEL)
1416 EXPORT_SYMBOL_GPL(l1tf_mitigation);
1418 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
1419 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
1422 * These CPUs all support 44bits physical address space internally in the
1423 * cache but CPUID can report a smaller number of physical address bits.
1425 * The L1TF mitigation uses the top most address bit for the inversion of
1426 * non present PTEs. When the installed memory reaches into the top most
1427 * address bit due to memory holes, which has been observed on machines
1428 * which report 36bits physical address bits and have 32G RAM installed,
1429 * then the mitigation range check in l1tf_select_mitigation() triggers.
1430 * This is a false positive because the mitigation is still possible due to
1431 * the fact that the cache uses 44bit internally. Use the cache bits
1432 * instead of the reported physical bits and adjust them on the affected
1433 * machines to 44bit if the reported bits are less than 44.
1435 static void override_cache_bits(struct cpuinfo_x86 *c)
1440 switch (c->x86_model) {
1441 case INTEL_FAM6_NEHALEM:
1442 case INTEL_FAM6_WESTMERE:
1443 case INTEL_FAM6_SANDYBRIDGE:
1444 case INTEL_FAM6_IVYBRIDGE:
1445 case INTEL_FAM6_HASWELL:
1446 case INTEL_FAM6_HASWELL_L:
1447 case INTEL_FAM6_HASWELL_G:
1448 case INTEL_FAM6_BROADWELL:
1449 case INTEL_FAM6_BROADWELL_G:
1450 case INTEL_FAM6_SKYLAKE_L:
1451 case INTEL_FAM6_SKYLAKE:
1452 case INTEL_FAM6_KABYLAKE_L:
1453 case INTEL_FAM6_KABYLAKE:
1454 if (c->x86_cache_bits < 44)
1455 c->x86_cache_bits = 44;
1460 static void __init l1tf_select_mitigation(void)
1464 if (!boot_cpu_has_bug(X86_BUG_L1TF))
1467 if (cpu_mitigations_off())
1468 l1tf_mitigation = L1TF_MITIGATION_OFF;
1469 else if (cpu_mitigations_auto_nosmt())
1470 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1472 override_cache_bits(&boot_cpu_data);
1474 switch (l1tf_mitigation) {
1475 case L1TF_MITIGATION_OFF:
1476 case L1TF_MITIGATION_FLUSH_NOWARN:
1477 case L1TF_MITIGATION_FLUSH:
1479 case L1TF_MITIGATION_FLUSH_NOSMT:
1480 case L1TF_MITIGATION_FULL:
1481 cpu_smt_disable(false);
1483 case L1TF_MITIGATION_FULL_FORCE:
1484 cpu_smt_disable(true);
1488 #if CONFIG_PGTABLE_LEVELS == 2
1489 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
1493 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
1494 if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
1495 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
1496 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1497 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
1499 pr_info("However, doing so will make a part of your RAM unusable.\n");
1500 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
1504 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
1507 static int __init l1tf_cmdline(char *str)
1509 if (!boot_cpu_has_bug(X86_BUG_L1TF))
1515 if (!strcmp(str, "off"))
1516 l1tf_mitigation = L1TF_MITIGATION_OFF;
1517 else if (!strcmp(str, "flush,nowarn"))
1518 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
1519 else if (!strcmp(str, "flush"))
1520 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
1521 else if (!strcmp(str, "flush,nosmt"))
1522 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
1523 else if (!strcmp(str, "full"))
1524 l1tf_mitigation = L1TF_MITIGATION_FULL;
1525 else if (!strcmp(str, "full,force"))
1526 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
1530 early_param("l1tf", l1tf_cmdline);
1533 #define pr_fmt(fmt) fmt
1537 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
1539 #if IS_ENABLED(CONFIG_KVM_INTEL)
1540 static const char * const l1tf_vmx_states[] = {
1541 [VMENTER_L1D_FLUSH_AUTO] = "auto",
1542 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
1543 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
1544 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
1545 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
1546 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
1549 static ssize_t l1tf_show_state(char *buf)
1551 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
1552 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1554 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
1555 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
1556 sched_smt_active())) {
1557 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
1558 l1tf_vmx_states[l1tf_vmx_mitigation]);
1561 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
1562 l1tf_vmx_states[l1tf_vmx_mitigation],
1563 sched_smt_active() ? "vulnerable" : "disabled");
1566 static ssize_t itlb_multihit_show_state(char *buf)
1568 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
1569 !boot_cpu_has(X86_FEATURE_VMX))
1570 return sprintf(buf, "KVM: Mitigation: VMX unsupported\n");
1571 else if (!(cr4_read_shadow() & X86_CR4_VMXE))
1572 return sprintf(buf, "KVM: Mitigation: VMX disabled\n");
1573 else if (itlb_multihit_kvm_mitigation)
1574 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
1576 return sprintf(buf, "KVM: Vulnerable\n");
1579 static ssize_t l1tf_show_state(char *buf)
1581 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
1584 static ssize_t itlb_multihit_show_state(char *buf)
1586 return sprintf(buf, "Processor vulnerable\n");
1590 static ssize_t mds_show_state(char *buf)
1592 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1593 return sprintf(buf, "%s; SMT Host state unknown\n",
1594 mds_strings[mds_mitigation]);
1597 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
1598 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1599 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
1600 sched_smt_active() ? "mitigated" : "disabled"));
1603 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
1604 sched_smt_active() ? "vulnerable" : "disabled");
1607 static ssize_t tsx_async_abort_show_state(char *buf)
1609 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
1610 (taa_mitigation == TAA_MITIGATION_OFF))
1611 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
1613 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
1614 return sprintf(buf, "%s; SMT Host state unknown\n",
1615 taa_strings[taa_mitigation]);
1618 return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
1619 sched_smt_active() ? "vulnerable" : "disabled");
1622 static char *stibp_state(void)
1624 if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
1627 switch (spectre_v2_user_stibp) {
1628 case SPECTRE_V2_USER_NONE:
1629 return ", STIBP: disabled";
1630 case SPECTRE_V2_USER_STRICT:
1631 return ", STIBP: forced";
1632 case SPECTRE_V2_USER_STRICT_PREFERRED:
1633 return ", STIBP: always-on";
1634 case SPECTRE_V2_USER_PRCTL:
1635 case SPECTRE_V2_USER_SECCOMP:
1636 if (static_key_enabled(&switch_to_cond_stibp))
1637 return ", STIBP: conditional";
1642 static char *ibpb_state(void)
1644 if (boot_cpu_has(X86_FEATURE_IBPB)) {
1645 if (static_key_enabled(&switch_mm_always_ibpb))
1646 return ", IBPB: always-on";
1647 if (static_key_enabled(&switch_mm_cond_ibpb))
1648 return ", IBPB: conditional";
1649 return ", IBPB: disabled";
1654 static ssize_t srbds_show_state(char *buf)
1656 return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
1659 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
1660 char *buf, unsigned int bug)
1662 if (!boot_cpu_has_bug(bug))
1663 return sprintf(buf, "Not affected\n");
1666 case X86_BUG_CPU_MELTDOWN:
1667 if (boot_cpu_has(X86_FEATURE_PTI))
1668 return sprintf(buf, "Mitigation: PTI\n");
1670 if (hypervisor_is_type(X86_HYPER_XEN_PV))
1671 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
1675 case X86_BUG_SPECTRE_V1:
1676 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
1678 case X86_BUG_SPECTRE_V2:
1679 return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
1681 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
1683 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
1684 spectre_v2_module_string());
1686 case X86_BUG_SPEC_STORE_BYPASS:
1687 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
1690 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
1691 return l1tf_show_state(buf);
1695 return mds_show_state(buf);
1698 return tsx_async_abort_show_state(buf);
1700 case X86_BUG_ITLB_MULTIHIT:
1701 return itlb_multihit_show_state(buf);
1704 return srbds_show_state(buf);
1710 return sprintf(buf, "Vulnerable\n");
1713 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
1715 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
1718 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
1720 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
1723 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
1725 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
1728 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
1730 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
1733 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
1735 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
1738 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
1740 return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
1743 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
1745 return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
1748 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
1750 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
1753 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
1755 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);