1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
18 #include <linux/pgtable.h>
19 #include <linux/bpf.h>
21 #include <asm/spec-ctrl.h>
22 #include <asm/cmdline.h>
24 #include <asm/processor.h>
25 #include <asm/processor-flags.h>
26 #include <asm/fpu/api.h>
29 #include <asm/paravirt.h>
30 #include <asm/alternative.h>
31 #include <asm/set_memory.h>
32 #include <asm/intel-family.h>
33 #include <asm/e820/api.h>
34 #include <asm/hypervisor.h>
35 #include <asm/tlbflush.h>
39 static void __init spectre_v1_select_mitigation(void);
40 static void __init spectre_v2_select_mitigation(void);
41 static void __init retbleed_select_mitigation(void);
42 static void __init spectre_v2_user_select_mitigation(void);
43 static void __init ssb_select_mitigation(void);
44 static void __init l1tf_select_mitigation(void);
45 static void __init mds_select_mitigation(void);
46 static void __init md_clear_update_mitigation(void);
47 static void __init md_clear_select_mitigation(void);
48 static void __init taa_select_mitigation(void);
49 static void __init mmio_select_mitigation(void);
50 static void __init srbds_select_mitigation(void);
51 static void __init l1d_flush_select_mitigation(void);
53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
54 u64 x86_spec_ctrl_base;
55 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
58 DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
59 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
61 static DEFINE_MUTEX(spec_ctrl_mutex);
64 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
65 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
67 void write_spec_ctrl_current(u64 val, bool force)
69 if (this_cpu_read(x86_spec_ctrl_current) == val)
72 this_cpu_write(x86_spec_ctrl_current, val);
75 * When KERNEL_IBRS this MSR is written on return-to-user, unless
76 * forced the update can be delayed until that time.
78 if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
79 wrmsrl(MSR_IA32_SPEC_CTRL, val);
82 u64 spec_ctrl_current(void)
84 return this_cpu_read(x86_spec_ctrl_current);
86 EXPORT_SYMBOL_GPL(spec_ctrl_current);
89 * The vendor and possibly platform specific bits which can be modified in
92 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
95 * AMD specific MSR info for Speculative Store Bypass control.
96 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
98 u64 __ro_after_init x86_amd_ls_cfg_base;
99 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
101 /* Control conditional STIBP in switch_to() */
102 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
103 /* Control conditional IBPB in switch_mm() */
104 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
105 /* Control unconditional IBPB in switch_mm() */
106 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
108 /* Control MDS CPU buffer clear before returning to user space */
109 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
110 EXPORT_SYMBOL_GPL(mds_user_clear);
111 /* Control MDS CPU buffer clear before idling (halt, mwait) */
112 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
113 EXPORT_SYMBOL_GPL(mds_idle_clear);
116 * Controls whether l1d flush based mitigations are enabled,
117 * based on hw features and admin setting via boot parameter
120 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
122 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
123 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
124 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
126 void __init check_bugs(void)
131 * identify_boot_cpu() initialized SMT support information, let the
134 cpu_smt_check_topology();
136 if (!IS_ENABLED(CONFIG_SMP)) {
138 print_cpu_info(&boot_cpu_data);
142 * Read the SPEC_CTRL MSR to account for reserved bits which may
143 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
144 * init code as it is not enumerated and depends on the family.
146 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
147 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
149 /* Allow STIBP in MSR_SPEC_CTRL if supported */
150 if (boot_cpu_has(X86_FEATURE_STIBP))
151 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
153 /* Select the proper CPU mitigations before patching alternatives: */
154 spectre_v1_select_mitigation();
155 spectre_v2_select_mitigation();
157 * retbleed_select_mitigation() relies on the state set by
158 * spectre_v2_select_mitigation(); specifically it wants to know about
161 retbleed_select_mitigation();
163 * spectre_v2_user_select_mitigation() relies on the state set by
164 * retbleed_select_mitigation(); specifically the STIBP selection is
167 spectre_v2_user_select_mitigation();
168 ssb_select_mitigation();
169 l1tf_select_mitigation();
170 md_clear_select_mitigation();
171 srbds_select_mitigation();
172 l1d_flush_select_mitigation();
178 * Check whether we are able to run this kernel safely on SMP.
180 * - i386 is no longer supported.
181 * - In order to run on anything without a TSC, we need to be
182 * compiled for a i486.
184 if (boot_cpu_data.x86 < 4)
185 panic("Kernel requires i486+ for 'invlpg' and other features");
187 init_utsname()->machine[1] =
188 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
189 alternative_instructions();
191 fpu__init_check_bugs();
192 #else /* CONFIG_X86_64 */
193 alternative_instructions();
196 * Make sure the first 2MB area is not mapped by huge pages
197 * There are typically fixed size MTRRs in there and overlapping
198 * MTRRs into large pages causes slow downs.
200 * Right now we don't do that with gbpages because there seems
201 * very little benefit for that case.
204 set_memory_4k((unsigned long)__va(0), 1);
209 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
211 u64 msrval, guestval, hostval = x86_spec_ctrl_base;
212 struct thread_info *ti = current_thread_info();
214 /* Is MSR_SPEC_CTRL implemented ? */
215 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
217 * Restrict guest_spec_ctrl to supported values. Clear the
218 * modifiable bits in the host base value and or the
219 * modifiable bits from the guest value.
221 guestval = hostval & ~x86_spec_ctrl_mask;
222 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
224 /* SSBD controlled in MSR_SPEC_CTRL */
225 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
226 static_cpu_has(X86_FEATURE_AMD_SSBD))
227 hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
229 /* Conditional STIBP enabled? */
230 if (static_branch_unlikely(&switch_to_cond_stibp))
231 hostval |= stibp_tif_to_spec_ctrl(ti->flags);
233 if (hostval != guestval) {
234 msrval = setguest ? guestval : hostval;
235 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
240 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
241 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
243 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
244 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
248 * If the host has SSBD mitigation enabled, force it in the host's
249 * virtual MSR value. If its not permanently enabled, evaluate
250 * current's TIF_SSBD thread flag.
252 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
253 hostval = SPEC_CTRL_SSBD;
255 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
257 /* Sanitize the guest value */
258 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
260 if (hostval != guestval) {
263 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
264 ssbd_spec_ctrl_to_tif(hostval);
266 speculation_ctrl_update(tif);
269 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
271 static void x86_amd_ssb_disable(void)
273 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
275 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
276 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
277 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
278 wrmsrl(MSR_AMD64_LS_CFG, msrval);
282 #define pr_fmt(fmt) "MDS: " fmt
284 /* Default mitigation for MDS-affected CPUs */
285 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
286 static bool mds_nosmt __ro_after_init = false;
288 static const char * const mds_strings[] = {
289 [MDS_MITIGATION_OFF] = "Vulnerable",
290 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers",
291 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
294 static void __init mds_select_mitigation(void)
296 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
297 mds_mitigation = MDS_MITIGATION_OFF;
301 if (mds_mitigation == MDS_MITIGATION_FULL) {
302 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
303 mds_mitigation = MDS_MITIGATION_VMWERV;
305 static_branch_enable(&mds_user_clear);
307 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
308 (mds_nosmt || cpu_mitigations_auto_nosmt()))
309 cpu_smt_disable(false);
313 static int __init mds_cmdline(char *str)
315 if (!boot_cpu_has_bug(X86_BUG_MDS))
321 if (!strcmp(str, "off"))
322 mds_mitigation = MDS_MITIGATION_OFF;
323 else if (!strcmp(str, "full"))
324 mds_mitigation = MDS_MITIGATION_FULL;
325 else if (!strcmp(str, "full,nosmt")) {
326 mds_mitigation = MDS_MITIGATION_FULL;
332 early_param("mds", mds_cmdline);
335 #define pr_fmt(fmt) "TAA: " fmt
337 enum taa_mitigations {
339 TAA_MITIGATION_UCODE_NEEDED,
341 TAA_MITIGATION_TSX_DISABLED,
344 /* Default mitigation for TAA-affected CPUs */
345 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
346 static bool taa_nosmt __ro_after_init;
348 static const char * const taa_strings[] = {
349 [TAA_MITIGATION_OFF] = "Vulnerable",
350 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
351 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
352 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled",
355 static void __init taa_select_mitigation(void)
359 if (!boot_cpu_has_bug(X86_BUG_TAA)) {
360 taa_mitigation = TAA_MITIGATION_OFF;
364 /* TSX previously disabled by tsx=off */
365 if (!boot_cpu_has(X86_FEATURE_RTM)) {
366 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
370 if (cpu_mitigations_off()) {
371 taa_mitigation = TAA_MITIGATION_OFF;
376 * TAA mitigation via VERW is turned off if both
377 * tsx_async_abort=off and mds=off are specified.
379 if (taa_mitigation == TAA_MITIGATION_OFF &&
380 mds_mitigation == MDS_MITIGATION_OFF)
383 if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
384 taa_mitigation = TAA_MITIGATION_VERW;
386 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
389 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
390 * A microcode update fixes this behavior to clear CPU buffers. It also
391 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
392 * ARCH_CAP_TSX_CTRL_MSR bit.
394 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
395 * update is required.
397 ia32_cap = x86_read_arch_cap_msr();
398 if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
399 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
400 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
403 * TSX is enabled, select alternate mitigation for TAA which is
404 * the same as MDS. Enable MDS static branch to clear CPU buffers.
406 * For guests that can't determine whether the correct microcode is
407 * present on host, enable the mitigation for UCODE_NEEDED as well.
409 static_branch_enable(&mds_user_clear);
411 if (taa_nosmt || cpu_mitigations_auto_nosmt())
412 cpu_smt_disable(false);
415 static int __init tsx_async_abort_parse_cmdline(char *str)
417 if (!boot_cpu_has_bug(X86_BUG_TAA))
423 if (!strcmp(str, "off")) {
424 taa_mitigation = TAA_MITIGATION_OFF;
425 } else if (!strcmp(str, "full")) {
426 taa_mitigation = TAA_MITIGATION_VERW;
427 } else if (!strcmp(str, "full,nosmt")) {
428 taa_mitigation = TAA_MITIGATION_VERW;
434 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
437 #define pr_fmt(fmt) "MMIO Stale Data: " fmt
439 enum mmio_mitigations {
441 MMIO_MITIGATION_UCODE_NEEDED,
442 MMIO_MITIGATION_VERW,
445 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
446 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
447 static bool mmio_nosmt __ro_after_init = false;
449 static const char * const mmio_strings[] = {
450 [MMIO_MITIGATION_OFF] = "Vulnerable",
451 [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
452 [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
455 static void __init mmio_select_mitigation(void)
459 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
460 cpu_mitigations_off()) {
461 mmio_mitigation = MMIO_MITIGATION_OFF;
465 if (mmio_mitigation == MMIO_MITIGATION_OFF)
468 ia32_cap = x86_read_arch_cap_msr();
471 * Enable CPU buffer clear mitigation for host and VMM, if also affected
472 * by MDS or TAA. Otherwise, enable mitigation for VMM only.
474 if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
475 boot_cpu_has(X86_FEATURE_RTM)))
476 static_branch_enable(&mds_user_clear);
478 static_branch_enable(&mmio_stale_data_clear);
481 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
482 * be propagated to uncore buffers, clearing the Fill buffers on idle
483 * is required irrespective of SMT state.
485 if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
486 static_branch_enable(&mds_idle_clear);
489 * Check if the system has the right microcode.
491 * CPU Fill buffer clear mitigation is enumerated by either an explicit
492 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
495 if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
496 (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
497 boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
498 !(ia32_cap & ARCH_CAP_MDS_NO)))
499 mmio_mitigation = MMIO_MITIGATION_VERW;
501 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
503 if (mmio_nosmt || cpu_mitigations_auto_nosmt())
504 cpu_smt_disable(false);
507 static int __init mmio_stale_data_parse_cmdline(char *str)
509 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
515 if (!strcmp(str, "off")) {
516 mmio_mitigation = MMIO_MITIGATION_OFF;
517 } else if (!strcmp(str, "full")) {
518 mmio_mitigation = MMIO_MITIGATION_VERW;
519 } else if (!strcmp(str, "full,nosmt")) {
520 mmio_mitigation = MMIO_MITIGATION_VERW;
526 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
529 #define pr_fmt(fmt) "" fmt
531 static void __init md_clear_update_mitigation(void)
533 if (cpu_mitigations_off())
536 if (!static_key_enabled(&mds_user_clear))
540 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
541 * mitigation, if necessary.
543 if (mds_mitigation == MDS_MITIGATION_OFF &&
544 boot_cpu_has_bug(X86_BUG_MDS)) {
545 mds_mitigation = MDS_MITIGATION_FULL;
546 mds_select_mitigation();
548 if (taa_mitigation == TAA_MITIGATION_OFF &&
549 boot_cpu_has_bug(X86_BUG_TAA)) {
550 taa_mitigation = TAA_MITIGATION_VERW;
551 taa_select_mitigation();
553 if (mmio_mitigation == MMIO_MITIGATION_OFF &&
554 boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
555 mmio_mitigation = MMIO_MITIGATION_VERW;
556 mmio_select_mitigation();
559 if (boot_cpu_has_bug(X86_BUG_MDS))
560 pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
561 if (boot_cpu_has_bug(X86_BUG_TAA))
562 pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
563 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
564 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
567 static void __init md_clear_select_mitigation(void)
569 mds_select_mitigation();
570 taa_select_mitigation();
571 mmio_select_mitigation();
574 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
575 * and print their mitigation after MDS, TAA and MMIO Stale Data
576 * mitigation selection is done.
578 md_clear_update_mitigation();
582 #define pr_fmt(fmt) "SRBDS: " fmt
584 enum srbds_mitigations {
585 SRBDS_MITIGATION_OFF,
586 SRBDS_MITIGATION_UCODE_NEEDED,
587 SRBDS_MITIGATION_FULL,
588 SRBDS_MITIGATION_TSX_OFF,
589 SRBDS_MITIGATION_HYPERVISOR,
592 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
594 static const char * const srbds_strings[] = {
595 [SRBDS_MITIGATION_OFF] = "Vulnerable",
596 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
597 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
598 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
599 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
602 static bool srbds_off;
604 void update_srbds_msr(void)
608 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
611 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
614 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
618 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX
619 * being disabled and it hasn't received the SRBDS MSR microcode.
621 if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
624 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
626 switch (srbds_mitigation) {
627 case SRBDS_MITIGATION_OFF:
628 case SRBDS_MITIGATION_TSX_OFF:
629 mcu_ctrl |= RNGDS_MITG_DIS;
631 case SRBDS_MITIGATION_FULL:
632 mcu_ctrl &= ~RNGDS_MITG_DIS;
638 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
641 static void __init srbds_select_mitigation(void)
645 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
649 * Check to see if this is one of the MDS_NO systems supporting TSX that
650 * are only exposed to SRBDS when TSX is enabled or when CPU is affected
651 * by Processor MMIO Stale Data vulnerability.
653 ia32_cap = x86_read_arch_cap_msr();
654 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
655 !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
656 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
657 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
658 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
659 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
660 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
661 else if (cpu_mitigations_off() || srbds_off)
662 srbds_mitigation = SRBDS_MITIGATION_OFF;
665 pr_info("%s\n", srbds_strings[srbds_mitigation]);
668 static int __init srbds_parse_cmdline(char *str)
673 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
676 srbds_off = !strcmp(str, "off");
679 early_param("srbds", srbds_parse_cmdline);
682 #define pr_fmt(fmt) "L1D Flush : " fmt
684 enum l1d_flush_mitigations {
689 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF;
691 static void __init l1d_flush_select_mitigation(void)
693 if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D))
696 static_branch_enable(&switch_mm_cond_l1d_flush);
697 pr_info("Conditional flush on switch_mm() enabled\n");
700 static int __init l1d_flush_parse_cmdline(char *str)
702 if (!strcmp(str, "on"))
703 l1d_flush_mitigation = L1D_FLUSH_ON;
707 early_param("l1d_flush", l1d_flush_parse_cmdline);
710 #define pr_fmt(fmt) "Spectre V1 : " fmt
712 enum spectre_v1_mitigation {
713 SPECTRE_V1_MITIGATION_NONE,
714 SPECTRE_V1_MITIGATION_AUTO,
717 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
718 SPECTRE_V1_MITIGATION_AUTO;
720 static const char * const spectre_v1_strings[] = {
721 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
722 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
726 * Does SMAP provide full mitigation against speculative kernel access to
729 static bool smap_works_speculatively(void)
731 if (!boot_cpu_has(X86_FEATURE_SMAP))
735 * On CPUs which are vulnerable to Meltdown, SMAP does not
736 * prevent speculative access to user data in the L1 cache.
737 * Consider SMAP to be non-functional as a mitigation on these
740 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
746 static void __init spectre_v1_select_mitigation(void)
748 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
749 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
753 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
755 * With Spectre v1, a user can speculatively control either
756 * path of a conditional swapgs with a user-controlled GS
757 * value. The mitigation is to add lfences to both code paths.
759 * If FSGSBASE is enabled, the user can put a kernel address in
760 * GS, in which case SMAP provides no protection.
762 * If FSGSBASE is disabled, the user can only put a user space
763 * address in GS. That makes an attack harder, but still
764 * possible if there's no SMAP protection.
766 if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
767 !smap_works_speculatively()) {
769 * Mitigation can be provided from SWAPGS itself or
770 * PTI as the CR3 write in the Meltdown mitigation
773 * If neither is there, mitigate with an LFENCE to
774 * stop speculation through swapgs.
776 if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
777 !boot_cpu_has(X86_FEATURE_PTI))
778 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
781 * Enable lfences in the kernel entry (non-swapgs)
782 * paths, to prevent user entry from speculatively
785 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
789 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
792 static int __init nospectre_v1_cmdline(char *str)
794 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
797 early_param("nospectre_v1", nospectre_v1_cmdline);
799 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
803 #define pr_fmt(fmt) "RETBleed: " fmt
805 enum retbleed_mitigation {
806 RETBLEED_MITIGATION_NONE,
807 RETBLEED_MITIGATION_UNRET,
808 RETBLEED_MITIGATION_IBPB,
809 RETBLEED_MITIGATION_IBRS,
810 RETBLEED_MITIGATION_EIBRS,
813 enum retbleed_mitigation_cmd {
820 const char * const retbleed_strings[] = {
821 [RETBLEED_MITIGATION_NONE] = "Vulnerable",
822 [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk",
823 [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB",
824 [RETBLEED_MITIGATION_IBRS] = "Mitigation: IBRS",
825 [RETBLEED_MITIGATION_EIBRS] = "Mitigation: Enhanced IBRS",
828 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
829 RETBLEED_MITIGATION_NONE;
830 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
833 static int __ro_after_init retbleed_nosmt = false;
835 static int __init retbleed_parse_cmdline(char *str)
841 char *next = strchr(str, ',');
847 if (!strcmp(str, "off")) {
848 retbleed_cmd = RETBLEED_CMD_OFF;
849 } else if (!strcmp(str, "auto")) {
850 retbleed_cmd = RETBLEED_CMD_AUTO;
851 } else if (!strcmp(str, "unret")) {
852 retbleed_cmd = RETBLEED_CMD_UNRET;
853 } else if (!strcmp(str, "ibpb")) {
854 retbleed_cmd = RETBLEED_CMD_IBPB;
855 } else if (!strcmp(str, "nosmt")) {
856 retbleed_nosmt = true;
858 pr_err("Ignoring unknown retbleed option (%s).", str);
866 early_param("retbleed", retbleed_parse_cmdline);
868 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n"
869 #define RETBLEED_COMPILER_MSG "WARNING: kernel not compiled with RETPOLINE or -mfunction-return capable compiler; falling back to IBPB!\n"
870 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
872 static void __init retbleed_select_mitigation(void)
874 bool mitigate_smt = false;
876 if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
879 switch (retbleed_cmd) {
880 case RETBLEED_CMD_OFF:
883 case RETBLEED_CMD_UNRET:
884 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
887 case RETBLEED_CMD_IBPB:
888 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
891 case RETBLEED_CMD_AUTO:
893 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
894 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
895 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
898 * The Intel mitigation (IBRS or eIBRS) was already selected in
899 * spectre_v2_select_mitigation(). 'retbleed_mitigation' will
900 * be set accordingly below.
906 switch (retbleed_mitigation) {
907 case RETBLEED_MITIGATION_UNRET:
909 if (!IS_ENABLED(CONFIG_RETPOLINE) ||
910 !IS_ENABLED(CONFIG_CC_HAS_RETURN_THUNK)) {
911 pr_err(RETBLEED_COMPILER_MSG);
912 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
913 goto retbleed_force_ibpb;
916 setup_force_cpu_cap(X86_FEATURE_RETHUNK);
917 setup_force_cpu_cap(X86_FEATURE_UNRET);
919 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
920 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
921 pr_err(RETBLEED_UNTRAIN_MSG);
926 case RETBLEED_MITIGATION_IBPB:
928 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
936 if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) &&
937 (retbleed_nosmt || cpu_mitigations_auto_nosmt()))
938 cpu_smt_disable(false);
941 * Let IBRS trump all on Intel without affecting the effects of the
942 * retbleed= cmdline option.
944 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
945 switch (spectre_v2_enabled) {
946 case SPECTRE_V2_IBRS:
947 retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
949 case SPECTRE_V2_EIBRS:
950 case SPECTRE_V2_EIBRS_RETPOLINE:
951 case SPECTRE_V2_EIBRS_LFENCE:
952 retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
955 pr_err(RETBLEED_INTEL_MSG);
959 pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
963 #define pr_fmt(fmt) "Spectre V2 : " fmt
965 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
966 SPECTRE_V2_USER_NONE;
967 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
968 SPECTRE_V2_USER_NONE;
970 #ifdef CONFIG_RETPOLINE
971 static bool spectre_v2_bad_module;
973 bool retpoline_module_ok(bool has_retpoline)
975 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
978 pr_err("System may be vulnerable to spectre v2\n");
979 spectre_v2_bad_module = true;
983 static inline const char *spectre_v2_module_string(void)
985 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
988 static inline const char *spectre_v2_module_string(void) { return ""; }
991 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
992 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
993 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
995 #ifdef CONFIG_BPF_SYSCALL
996 void unpriv_ebpf_notify(int new_state)
1001 /* Unprivileged eBPF is enabled */
1003 switch (spectre_v2_enabled) {
1004 case SPECTRE_V2_EIBRS:
1005 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1007 case SPECTRE_V2_EIBRS_LFENCE:
1008 if (sched_smt_active())
1009 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1017 static inline bool match_option(const char *arg, int arglen, const char *opt)
1019 int len = strlen(opt);
1021 return len == arglen && !strncmp(arg, opt, len);
1024 /* The kernel command line selection for spectre v2 */
1025 enum spectre_v2_mitigation_cmd {
1026 SPECTRE_V2_CMD_NONE,
1027 SPECTRE_V2_CMD_AUTO,
1028 SPECTRE_V2_CMD_FORCE,
1029 SPECTRE_V2_CMD_RETPOLINE,
1030 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
1031 SPECTRE_V2_CMD_RETPOLINE_LFENCE,
1032 SPECTRE_V2_CMD_EIBRS,
1033 SPECTRE_V2_CMD_EIBRS_RETPOLINE,
1034 SPECTRE_V2_CMD_EIBRS_LFENCE,
1035 SPECTRE_V2_CMD_IBRS,
1038 enum spectre_v2_user_cmd {
1039 SPECTRE_V2_USER_CMD_NONE,
1040 SPECTRE_V2_USER_CMD_AUTO,
1041 SPECTRE_V2_USER_CMD_FORCE,
1042 SPECTRE_V2_USER_CMD_PRCTL,
1043 SPECTRE_V2_USER_CMD_PRCTL_IBPB,
1044 SPECTRE_V2_USER_CMD_SECCOMP,
1045 SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
1048 static const char * const spectre_v2_user_strings[] = {
1049 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable",
1050 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection",
1051 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection",
1052 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl",
1053 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl",
1056 static const struct {
1058 enum spectre_v2_user_cmd cmd;
1060 } v2_user_options[] __initconst = {
1061 { "auto", SPECTRE_V2_USER_CMD_AUTO, false },
1062 { "off", SPECTRE_V2_USER_CMD_NONE, false },
1063 { "on", SPECTRE_V2_USER_CMD_FORCE, true },
1064 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false },
1065 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false },
1066 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false },
1067 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false },
1070 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
1072 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1073 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
1076 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
1078 static enum spectre_v2_user_cmd __init
1079 spectre_v2_parse_user_cmdline(void)
1084 switch (spectre_v2_cmd) {
1085 case SPECTRE_V2_CMD_NONE:
1086 return SPECTRE_V2_USER_CMD_NONE;
1087 case SPECTRE_V2_CMD_FORCE:
1088 return SPECTRE_V2_USER_CMD_FORCE;
1093 ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
1096 return SPECTRE_V2_USER_CMD_AUTO;
1098 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
1099 if (match_option(arg, ret, v2_user_options[i].option)) {
1100 spec_v2_user_print_cond(v2_user_options[i].option,
1101 v2_user_options[i].secure);
1102 return v2_user_options[i].cmd;
1106 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
1107 return SPECTRE_V2_USER_CMD_AUTO;
1110 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
1112 return mode == SPECTRE_V2_IBRS ||
1113 mode == SPECTRE_V2_EIBRS ||
1114 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1115 mode == SPECTRE_V2_EIBRS_LFENCE;
1119 spectre_v2_user_select_mitigation(void)
1121 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
1122 bool smt_possible = IS_ENABLED(CONFIG_SMP);
1123 enum spectre_v2_user_cmd cmd;
1125 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
1128 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
1129 cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
1130 smt_possible = false;
1132 cmd = spectre_v2_parse_user_cmdline();
1134 case SPECTRE_V2_USER_CMD_NONE:
1136 case SPECTRE_V2_USER_CMD_FORCE:
1137 mode = SPECTRE_V2_USER_STRICT;
1139 case SPECTRE_V2_USER_CMD_AUTO:
1140 case SPECTRE_V2_USER_CMD_PRCTL:
1141 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1142 mode = SPECTRE_V2_USER_PRCTL;
1144 case SPECTRE_V2_USER_CMD_SECCOMP:
1145 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1146 if (IS_ENABLED(CONFIG_SECCOMP))
1147 mode = SPECTRE_V2_USER_SECCOMP;
1149 mode = SPECTRE_V2_USER_PRCTL;
1153 /* Initialize Indirect Branch Prediction Barrier */
1154 if (boot_cpu_has(X86_FEATURE_IBPB)) {
1155 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
1157 spectre_v2_user_ibpb = mode;
1159 case SPECTRE_V2_USER_CMD_FORCE:
1160 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1161 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1162 static_branch_enable(&switch_mm_always_ibpb);
1163 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
1165 case SPECTRE_V2_USER_CMD_PRCTL:
1166 case SPECTRE_V2_USER_CMD_AUTO:
1167 case SPECTRE_V2_USER_CMD_SECCOMP:
1168 static_branch_enable(&switch_mm_cond_ibpb);
1174 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
1175 static_key_enabled(&switch_mm_always_ibpb) ?
1176 "always-on" : "conditional");
1180 * If no STIBP, IBRS or enhanced IBRS is enabled, or SMT impossible,
1181 * STIBP is not required.
1183 if (!boot_cpu_has(X86_FEATURE_STIBP) ||
1185 spectre_v2_in_ibrs_mode(spectre_v2_enabled))
1189 * At this point, an STIBP mode other than "off" has been set.
1190 * If STIBP support is not being forced, check if STIBP always-on
1193 if (mode != SPECTRE_V2_USER_STRICT &&
1194 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
1195 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1197 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) {
1198 if (mode != SPECTRE_V2_USER_STRICT &&
1199 mode != SPECTRE_V2_USER_STRICT_PREFERRED)
1200 pr_info("Selecting STIBP always-on mode to complement retbleed mitigation'\n");
1201 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1204 spectre_v2_user_stibp = mode;
1207 pr_info("%s\n", spectre_v2_user_strings[mode]);
1210 static const char * const spectre_v2_strings[] = {
1211 [SPECTRE_V2_NONE] = "Vulnerable",
1212 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines",
1213 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE",
1214 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS",
1215 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE",
1216 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines",
1217 [SPECTRE_V2_IBRS] = "Mitigation: IBRS",
1220 static const struct {
1222 enum spectre_v2_mitigation_cmd cmd;
1224 } mitigation_options[] __initconst = {
1225 { "off", SPECTRE_V2_CMD_NONE, false },
1226 { "on", SPECTRE_V2_CMD_FORCE, true },
1227 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
1228 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1229 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1230 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
1231 { "eibrs", SPECTRE_V2_CMD_EIBRS, false },
1232 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false },
1233 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false },
1234 { "auto", SPECTRE_V2_CMD_AUTO, false },
1235 { "ibrs", SPECTRE_V2_CMD_IBRS, false },
1238 static void __init spec_v2_print_cond(const char *reason, bool secure)
1240 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1241 pr_info("%s selected on command line.\n", reason);
1244 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
1246 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
1250 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
1251 cpu_mitigations_off())
1252 return SPECTRE_V2_CMD_NONE;
1254 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
1256 return SPECTRE_V2_CMD_AUTO;
1258 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
1259 if (!match_option(arg, ret, mitigation_options[i].option))
1261 cmd = mitigation_options[i].cmd;
1265 if (i >= ARRAY_SIZE(mitigation_options)) {
1266 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1267 return SPECTRE_V2_CMD_AUTO;
1270 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1271 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1272 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1273 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1274 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1275 !IS_ENABLED(CONFIG_RETPOLINE)) {
1276 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1277 mitigation_options[i].option);
1278 return SPECTRE_V2_CMD_AUTO;
1281 if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1282 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1283 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1284 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1285 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
1286 mitigation_options[i].option);
1287 return SPECTRE_V2_CMD_AUTO;
1290 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1291 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1292 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1293 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1294 mitigation_options[i].option);
1295 return SPECTRE_V2_CMD_AUTO;
1298 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1299 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
1300 mitigation_options[i].option);
1301 return SPECTRE_V2_CMD_AUTO;
1304 if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
1305 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
1306 mitigation_options[i].option);
1307 return SPECTRE_V2_CMD_AUTO;
1310 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) {
1311 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
1312 mitigation_options[i].option);
1313 return SPECTRE_V2_CMD_AUTO;
1316 spec_v2_print_cond(mitigation_options[i].option,
1317 mitigation_options[i].secure);
1321 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1323 if (!IS_ENABLED(CONFIG_RETPOLINE)) {
1324 pr_err("Kernel not compiled with retpoline; no mitigation available!");
1325 return SPECTRE_V2_NONE;
1328 return SPECTRE_V2_RETPOLINE;
1331 static void __init spectre_v2_select_mitigation(void)
1333 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1334 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1337 * If the CPU is not affected and the command line mode is NONE or AUTO
1338 * then nothing to do.
1340 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1341 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1345 case SPECTRE_V2_CMD_NONE:
1348 case SPECTRE_V2_CMD_FORCE:
1349 case SPECTRE_V2_CMD_AUTO:
1350 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1351 mode = SPECTRE_V2_EIBRS;
1355 if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1356 retbleed_cmd != RETBLEED_CMD_OFF &&
1357 boot_cpu_has(X86_FEATURE_IBRS) &&
1358 boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1359 mode = SPECTRE_V2_IBRS;
1363 mode = spectre_v2_select_retpoline();
1366 case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1367 pr_err(SPECTRE_V2_LFENCE_MSG);
1368 mode = SPECTRE_V2_LFENCE;
1371 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1372 mode = SPECTRE_V2_RETPOLINE;
1375 case SPECTRE_V2_CMD_RETPOLINE:
1376 mode = spectre_v2_select_retpoline();
1379 case SPECTRE_V2_CMD_IBRS:
1380 mode = SPECTRE_V2_IBRS;
1383 case SPECTRE_V2_CMD_EIBRS:
1384 mode = SPECTRE_V2_EIBRS;
1387 case SPECTRE_V2_CMD_EIBRS_LFENCE:
1388 mode = SPECTRE_V2_EIBRS_LFENCE;
1391 case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1392 mode = SPECTRE_V2_EIBRS_RETPOLINE;
1396 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1397 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1399 if (spectre_v2_in_ibrs_mode(mode)) {
1400 /* Force it so VMEXIT will restore correctly */
1401 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1402 write_spec_ctrl_current(x86_spec_ctrl_base, true);
1406 case SPECTRE_V2_NONE:
1407 case SPECTRE_V2_EIBRS:
1410 case SPECTRE_V2_IBRS:
1411 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
1414 case SPECTRE_V2_LFENCE:
1415 case SPECTRE_V2_EIBRS_LFENCE:
1416 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1419 case SPECTRE_V2_RETPOLINE:
1420 case SPECTRE_V2_EIBRS_RETPOLINE:
1421 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1425 spectre_v2_enabled = mode;
1426 pr_info("%s\n", spectre_v2_strings[mode]);
1429 * If spectre v2 protection has been enabled, unconditionally fill
1430 * RSB during a context switch; this protects against two independent
1433 * - RSB underflow (and switch to BTB) on Skylake+
1434 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
1436 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1437 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1440 * Retpoline protects the kernel, but doesn't protect firmware. IBRS
1441 * and Enhanced IBRS protect firmware too, so enable IBRS around
1442 * firmware calls only when IBRS / Enhanced IBRS aren't otherwise
1445 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1446 * the user might select retpoline on the kernel command line and if
1447 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1448 * enable IBRS around firmware calls.
1450 if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
1451 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1452 pr_info("Enabling Restricted Speculation for firmware calls\n");
1455 /* Set up IBPB and STIBP depending on the general spectre V2 command */
1456 spectre_v2_cmd = cmd;
1459 static void update_stibp_msr(void * __unused)
1461 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
1462 write_spec_ctrl_current(val, true);
1465 /* Update x86_spec_ctrl_base in case SMT state changed. */
1466 static void update_stibp_strict(void)
1468 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1470 if (sched_smt_active())
1471 mask |= SPEC_CTRL_STIBP;
1473 if (mask == x86_spec_ctrl_base)
1476 pr_info("Update user space SMT mitigation: STIBP %s\n",
1477 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1478 x86_spec_ctrl_base = mask;
1479 on_each_cpu(update_stibp_msr, NULL, 1);
1482 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
1483 static void update_indir_branch_cond(void)
1485 if (sched_smt_active())
1486 static_branch_enable(&switch_to_cond_stibp);
1488 static_branch_disable(&switch_to_cond_stibp);
1492 #define pr_fmt(fmt) fmt
1494 /* Update the static key controlling the MDS CPU buffer clear in idle */
1495 static void update_mds_branch_idle(void)
1497 u64 ia32_cap = x86_read_arch_cap_msr();
1500 * Enable the idle clearing if SMT is active on CPUs which are
1501 * affected only by MSBDS and not any other MDS variant.
1503 * The other variants cannot be mitigated when SMT is enabled, so
1504 * clearing the buffers on idle just to prevent the Store Buffer
1505 * repartitioning leak would be a window dressing exercise.
1507 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1510 if (sched_smt_active()) {
1511 static_branch_enable(&mds_idle_clear);
1512 } else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
1513 (ia32_cap & ARCH_CAP_FBSDP_NO)) {
1514 static_branch_disable(&mds_idle_clear);
1518 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1519 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1520 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
1522 void cpu_bugs_smt_update(void)
1524 mutex_lock(&spec_ctrl_mutex);
1526 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1527 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1528 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1530 switch (spectre_v2_user_stibp) {
1531 case SPECTRE_V2_USER_NONE:
1533 case SPECTRE_V2_USER_STRICT:
1534 case SPECTRE_V2_USER_STRICT_PREFERRED:
1535 update_stibp_strict();
1537 case SPECTRE_V2_USER_PRCTL:
1538 case SPECTRE_V2_USER_SECCOMP:
1539 update_indir_branch_cond();
1543 switch (mds_mitigation) {
1544 case MDS_MITIGATION_FULL:
1545 case MDS_MITIGATION_VMWERV:
1546 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1547 pr_warn_once(MDS_MSG_SMT);
1548 update_mds_branch_idle();
1550 case MDS_MITIGATION_OFF:
1554 switch (taa_mitigation) {
1555 case TAA_MITIGATION_VERW:
1556 case TAA_MITIGATION_UCODE_NEEDED:
1557 if (sched_smt_active())
1558 pr_warn_once(TAA_MSG_SMT);
1560 case TAA_MITIGATION_TSX_DISABLED:
1561 case TAA_MITIGATION_OFF:
1565 switch (mmio_mitigation) {
1566 case MMIO_MITIGATION_VERW:
1567 case MMIO_MITIGATION_UCODE_NEEDED:
1568 if (sched_smt_active())
1569 pr_warn_once(MMIO_MSG_SMT);
1571 case MMIO_MITIGATION_OFF:
1575 mutex_unlock(&spec_ctrl_mutex);
1579 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
1581 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1583 /* The kernel command line selection */
1584 enum ssb_mitigation_cmd {
1585 SPEC_STORE_BYPASS_CMD_NONE,
1586 SPEC_STORE_BYPASS_CMD_AUTO,
1587 SPEC_STORE_BYPASS_CMD_ON,
1588 SPEC_STORE_BYPASS_CMD_PRCTL,
1589 SPEC_STORE_BYPASS_CMD_SECCOMP,
1592 static const char * const ssb_strings[] = {
1593 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
1594 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
1595 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
1596 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1599 static const struct {
1601 enum ssb_mitigation_cmd cmd;
1602 } ssb_mitigation_options[] __initconst = {
1603 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
1604 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
1605 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
1606 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
1607 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1610 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1612 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1616 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1617 cpu_mitigations_off()) {
1618 return SPEC_STORE_BYPASS_CMD_NONE;
1620 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1623 return SPEC_STORE_BYPASS_CMD_AUTO;
1625 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1626 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1629 cmd = ssb_mitigation_options[i].cmd;
1633 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1634 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1635 return SPEC_STORE_BYPASS_CMD_AUTO;
1642 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1644 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1645 enum ssb_mitigation_cmd cmd;
1647 if (!boot_cpu_has(X86_FEATURE_SSBD))
1650 cmd = ssb_parse_cmdline();
1651 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1652 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1653 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1657 case SPEC_STORE_BYPASS_CMD_SECCOMP:
1659 * Choose prctl+seccomp as the default mode if seccomp is
1662 if (IS_ENABLED(CONFIG_SECCOMP))
1663 mode = SPEC_STORE_BYPASS_SECCOMP;
1665 mode = SPEC_STORE_BYPASS_PRCTL;
1667 case SPEC_STORE_BYPASS_CMD_ON:
1668 mode = SPEC_STORE_BYPASS_DISABLE;
1670 case SPEC_STORE_BYPASS_CMD_AUTO:
1671 case SPEC_STORE_BYPASS_CMD_PRCTL:
1672 mode = SPEC_STORE_BYPASS_PRCTL;
1674 case SPEC_STORE_BYPASS_CMD_NONE:
1679 * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
1680 * bit in the mask to allow guests to use the mitigation even in the
1681 * case where the host does not enable it.
1683 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
1684 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1685 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
1689 * We have three CPU feature flags that are in play here:
1690 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1691 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1692 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1694 if (mode == SPEC_STORE_BYPASS_DISABLE) {
1695 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1697 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1698 * use a completely different MSR and bit dependent on family.
1700 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1701 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1702 x86_amd_ssb_disable();
1704 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1705 write_spec_ctrl_current(x86_spec_ctrl_base, true);
1712 static void ssb_select_mitigation(void)
1714 ssb_mode = __ssb_select_mitigation();
1716 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1717 pr_info("%s\n", ssb_strings[ssb_mode]);
1721 #define pr_fmt(fmt) "Speculation prctl: " fmt
1723 static void task_update_spec_tif(struct task_struct *tsk)
1725 /* Force the update of the real TIF bits */
1726 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1729 * Immediately update the speculation control MSRs for the current
1730 * task, but for a non-current task delay setting the CPU
1731 * mitigation until it is scheduled next.
1733 * This can only happen for SECCOMP mitigation. For PRCTL it's
1734 * always the current task.
1737 speculation_ctrl_update_current();
1740 static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl)
1743 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
1747 case PR_SPEC_ENABLE:
1748 set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
1750 case PR_SPEC_DISABLE:
1751 clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
1758 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1760 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1761 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1765 case PR_SPEC_ENABLE:
1766 /* If speculation is force disabled, enable is not allowed */
1767 if (task_spec_ssb_force_disable(task))
1769 task_clear_spec_ssb_disable(task);
1770 task_clear_spec_ssb_noexec(task);
1771 task_update_spec_tif(task);
1773 case PR_SPEC_DISABLE:
1774 task_set_spec_ssb_disable(task);
1775 task_clear_spec_ssb_noexec(task);
1776 task_update_spec_tif(task);
1778 case PR_SPEC_FORCE_DISABLE:
1779 task_set_spec_ssb_disable(task);
1780 task_set_spec_ssb_force_disable(task);
1781 task_clear_spec_ssb_noexec(task);
1782 task_update_spec_tif(task);
1784 case PR_SPEC_DISABLE_NOEXEC:
1785 if (task_spec_ssb_force_disable(task))
1787 task_set_spec_ssb_disable(task);
1788 task_set_spec_ssb_noexec(task);
1789 task_update_spec_tif(task);
1797 static bool is_spec_ib_user_controlled(void)
1799 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1800 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1801 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1802 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1805 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1808 case PR_SPEC_ENABLE:
1809 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1810 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1814 * With strict mode for both IBPB and STIBP, the instruction
1815 * code paths avoid checking this task flag and instead,
1816 * unconditionally run the instruction. However, STIBP and IBPB
1817 * are independent and either can be set to conditionally
1818 * enabled regardless of the mode of the other.
1820 * If either is set to conditional, allow the task flag to be
1821 * updated, unless it was force-disabled by a previous prctl
1822 * call. Currently, this is possible on an AMD CPU which has the
1823 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1824 * kernel is booted with 'spectre_v2_user=seccomp', then
1825 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1826 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1828 if (!is_spec_ib_user_controlled() ||
1829 task_spec_ib_force_disable(task))
1832 task_clear_spec_ib_disable(task);
1833 task_update_spec_tif(task);
1835 case PR_SPEC_DISABLE:
1836 case PR_SPEC_FORCE_DISABLE:
1838 * Indirect branch speculation is always allowed when
1839 * mitigation is force disabled.
1841 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1842 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1845 if (!is_spec_ib_user_controlled())
1848 task_set_spec_ib_disable(task);
1849 if (ctrl == PR_SPEC_FORCE_DISABLE)
1850 task_set_spec_ib_force_disable(task);
1851 task_update_spec_tif(task);
1859 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1863 case PR_SPEC_STORE_BYPASS:
1864 return ssb_prctl_set(task, ctrl);
1865 case PR_SPEC_INDIRECT_BRANCH:
1866 return ib_prctl_set(task, ctrl);
1867 case PR_SPEC_L1D_FLUSH:
1868 return l1d_flush_prctl_set(task, ctrl);
1874 #ifdef CONFIG_SECCOMP
1875 void arch_seccomp_spec_mitigate(struct task_struct *task)
1877 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1878 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1879 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1880 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1881 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1885 static int l1d_flush_prctl_get(struct task_struct *task)
1887 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
1888 return PR_SPEC_FORCE_DISABLE;
1890 if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH))
1891 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1893 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1896 static int ssb_prctl_get(struct task_struct *task)
1899 case SPEC_STORE_BYPASS_DISABLE:
1900 return PR_SPEC_DISABLE;
1901 case SPEC_STORE_BYPASS_SECCOMP:
1902 case SPEC_STORE_BYPASS_PRCTL:
1903 if (task_spec_ssb_force_disable(task))
1904 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1905 if (task_spec_ssb_noexec(task))
1906 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
1907 if (task_spec_ssb_disable(task))
1908 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1909 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1911 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1912 return PR_SPEC_ENABLE;
1913 return PR_SPEC_NOT_AFFECTED;
1917 static int ib_prctl_get(struct task_struct *task)
1919 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1920 return PR_SPEC_NOT_AFFECTED;
1922 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1923 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1924 return PR_SPEC_ENABLE;
1925 else if (is_spec_ib_user_controlled()) {
1926 if (task_spec_ib_force_disable(task))
1927 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1928 if (task_spec_ib_disable(task))
1929 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1930 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1931 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1932 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1933 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1934 return PR_SPEC_DISABLE;
1936 return PR_SPEC_NOT_AFFECTED;
1939 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1942 case PR_SPEC_STORE_BYPASS:
1943 return ssb_prctl_get(task);
1944 case PR_SPEC_INDIRECT_BRANCH:
1945 return ib_prctl_get(task);
1946 case PR_SPEC_L1D_FLUSH:
1947 return l1d_flush_prctl_get(task);
1953 void x86_spec_ctrl_setup_ap(void)
1955 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
1956 write_spec_ctrl_current(x86_spec_ctrl_base, true);
1958 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
1959 x86_amd_ssb_disable();
1962 bool itlb_multihit_kvm_mitigation;
1963 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
1966 #define pr_fmt(fmt) "L1TF: " fmt
1968 /* Default mitigation for L1TF-affected CPUs */
1969 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
1970 #if IS_ENABLED(CONFIG_KVM_INTEL)
1971 EXPORT_SYMBOL_GPL(l1tf_mitigation);
1973 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
1974 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
1977 * These CPUs all support 44bits physical address space internally in the
1978 * cache but CPUID can report a smaller number of physical address bits.
1980 * The L1TF mitigation uses the top most address bit for the inversion of
1981 * non present PTEs. When the installed memory reaches into the top most
1982 * address bit due to memory holes, which has been observed on machines
1983 * which report 36bits physical address bits and have 32G RAM installed,
1984 * then the mitigation range check in l1tf_select_mitigation() triggers.
1985 * This is a false positive because the mitigation is still possible due to
1986 * the fact that the cache uses 44bit internally. Use the cache bits
1987 * instead of the reported physical bits and adjust them on the affected
1988 * machines to 44bit if the reported bits are less than 44.
1990 static void override_cache_bits(struct cpuinfo_x86 *c)
1995 switch (c->x86_model) {
1996 case INTEL_FAM6_NEHALEM:
1997 case INTEL_FAM6_WESTMERE:
1998 case INTEL_FAM6_SANDYBRIDGE:
1999 case INTEL_FAM6_IVYBRIDGE:
2000 case INTEL_FAM6_HASWELL:
2001 case INTEL_FAM6_HASWELL_L:
2002 case INTEL_FAM6_HASWELL_G:
2003 case INTEL_FAM6_BROADWELL:
2004 case INTEL_FAM6_BROADWELL_G:
2005 case INTEL_FAM6_SKYLAKE_L:
2006 case INTEL_FAM6_SKYLAKE:
2007 case INTEL_FAM6_KABYLAKE_L:
2008 case INTEL_FAM6_KABYLAKE:
2009 if (c->x86_cache_bits < 44)
2010 c->x86_cache_bits = 44;
2015 static void __init l1tf_select_mitigation(void)
2019 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2022 if (cpu_mitigations_off())
2023 l1tf_mitigation = L1TF_MITIGATION_OFF;
2024 else if (cpu_mitigations_auto_nosmt())
2025 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2027 override_cache_bits(&boot_cpu_data);
2029 switch (l1tf_mitigation) {
2030 case L1TF_MITIGATION_OFF:
2031 case L1TF_MITIGATION_FLUSH_NOWARN:
2032 case L1TF_MITIGATION_FLUSH:
2034 case L1TF_MITIGATION_FLUSH_NOSMT:
2035 case L1TF_MITIGATION_FULL:
2036 cpu_smt_disable(false);
2038 case L1TF_MITIGATION_FULL_FORCE:
2039 cpu_smt_disable(true);
2043 #if CONFIG_PGTABLE_LEVELS == 2
2044 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
2048 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
2049 if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
2050 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
2051 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
2052 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
2054 pr_info("However, doing so will make a part of your RAM unusable.\n");
2055 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
2059 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
2062 static int __init l1tf_cmdline(char *str)
2064 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2070 if (!strcmp(str, "off"))
2071 l1tf_mitigation = L1TF_MITIGATION_OFF;
2072 else if (!strcmp(str, "flush,nowarn"))
2073 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
2074 else if (!strcmp(str, "flush"))
2075 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
2076 else if (!strcmp(str, "flush,nosmt"))
2077 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2078 else if (!strcmp(str, "full"))
2079 l1tf_mitigation = L1TF_MITIGATION_FULL;
2080 else if (!strcmp(str, "full,force"))
2081 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
2085 early_param("l1tf", l1tf_cmdline);
2088 #define pr_fmt(fmt) fmt
2092 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
2094 #if IS_ENABLED(CONFIG_KVM_INTEL)
2095 static const char * const l1tf_vmx_states[] = {
2096 [VMENTER_L1D_FLUSH_AUTO] = "auto",
2097 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
2098 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
2099 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
2100 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
2101 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
2104 static ssize_t l1tf_show_state(char *buf)
2106 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
2107 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2109 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
2110 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
2111 sched_smt_active())) {
2112 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
2113 l1tf_vmx_states[l1tf_vmx_mitigation]);
2116 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
2117 l1tf_vmx_states[l1tf_vmx_mitigation],
2118 sched_smt_active() ? "vulnerable" : "disabled");
2121 static ssize_t itlb_multihit_show_state(char *buf)
2123 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2124 !boot_cpu_has(X86_FEATURE_VMX))
2125 return sprintf(buf, "KVM: Mitigation: VMX unsupported\n");
2126 else if (!(cr4_read_shadow() & X86_CR4_VMXE))
2127 return sprintf(buf, "KVM: Mitigation: VMX disabled\n");
2128 else if (itlb_multihit_kvm_mitigation)
2129 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
2131 return sprintf(buf, "KVM: Vulnerable\n");
2134 static ssize_t l1tf_show_state(char *buf)
2136 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2139 static ssize_t itlb_multihit_show_state(char *buf)
2141 return sprintf(buf, "Processor vulnerable\n");
2145 static ssize_t mds_show_state(char *buf)
2147 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2148 return sprintf(buf, "%s; SMT Host state unknown\n",
2149 mds_strings[mds_mitigation]);
2152 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
2153 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2154 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
2155 sched_smt_active() ? "mitigated" : "disabled"));
2158 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2159 sched_smt_active() ? "vulnerable" : "disabled");
2162 static ssize_t tsx_async_abort_show_state(char *buf)
2164 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
2165 (taa_mitigation == TAA_MITIGATION_OFF))
2166 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
2168 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2169 return sprintf(buf, "%s; SMT Host state unknown\n",
2170 taa_strings[taa_mitigation]);
2173 return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
2174 sched_smt_active() ? "vulnerable" : "disabled");
2177 static ssize_t mmio_stale_data_show_state(char *buf)
2179 if (mmio_mitigation == MMIO_MITIGATION_OFF)
2180 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
2182 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2183 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2184 mmio_strings[mmio_mitigation]);
2187 return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
2188 sched_smt_active() ? "vulnerable" : "disabled");
2191 static char *stibp_state(void)
2193 if (spectre_v2_in_ibrs_mode(spectre_v2_enabled))
2196 switch (spectre_v2_user_stibp) {
2197 case SPECTRE_V2_USER_NONE:
2198 return ", STIBP: disabled";
2199 case SPECTRE_V2_USER_STRICT:
2200 return ", STIBP: forced";
2201 case SPECTRE_V2_USER_STRICT_PREFERRED:
2202 return ", STIBP: always-on";
2203 case SPECTRE_V2_USER_PRCTL:
2204 case SPECTRE_V2_USER_SECCOMP:
2205 if (static_key_enabled(&switch_to_cond_stibp))
2206 return ", STIBP: conditional";
2211 static char *ibpb_state(void)
2213 if (boot_cpu_has(X86_FEATURE_IBPB)) {
2214 if (static_key_enabled(&switch_mm_always_ibpb))
2215 return ", IBPB: always-on";
2216 if (static_key_enabled(&switch_mm_cond_ibpb))
2217 return ", IBPB: conditional";
2218 return ", IBPB: disabled";
2223 static ssize_t spectre_v2_show_state(char *buf)
2225 if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
2226 return sprintf(buf, "Vulnerable: LFENCE\n");
2228 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
2229 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
2231 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
2232 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
2233 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
2235 return sprintf(buf, "%s%s%s%s%s%s\n",
2236 spectre_v2_strings[spectre_v2_enabled],
2238 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
2240 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
2241 spectre_v2_module_string());
2244 static ssize_t srbds_show_state(char *buf)
2246 return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
2249 static ssize_t retbleed_show_state(char *buf)
2251 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) {
2252 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
2253 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
2254 return sprintf(buf, "Vulnerable: untrained return thunk on non-Zen uarch\n");
2256 return sprintf(buf, "%s; SMT %s\n",
2257 retbleed_strings[retbleed_mitigation],
2258 !sched_smt_active() ? "disabled" :
2259 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2260 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ?
2261 "enabled with STIBP protection" : "vulnerable");
2264 return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
2267 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
2268 char *buf, unsigned int bug)
2270 if (!boot_cpu_has_bug(bug))
2271 return sprintf(buf, "Not affected\n");
2274 case X86_BUG_CPU_MELTDOWN:
2275 if (boot_cpu_has(X86_FEATURE_PTI))
2276 return sprintf(buf, "Mitigation: PTI\n");
2278 if (hypervisor_is_type(X86_HYPER_XEN_PV))
2279 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
2283 case X86_BUG_SPECTRE_V1:
2284 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
2286 case X86_BUG_SPECTRE_V2:
2287 return spectre_v2_show_state(buf);
2289 case X86_BUG_SPEC_STORE_BYPASS:
2290 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
2293 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
2294 return l1tf_show_state(buf);
2298 return mds_show_state(buf);
2301 return tsx_async_abort_show_state(buf);
2303 case X86_BUG_ITLB_MULTIHIT:
2304 return itlb_multihit_show_state(buf);
2307 return srbds_show_state(buf);
2309 case X86_BUG_MMIO_STALE_DATA:
2310 return mmio_stale_data_show_state(buf);
2312 case X86_BUG_RETBLEED:
2313 return retbleed_show_state(buf);
2319 return sprintf(buf, "Vulnerable\n");
2322 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
2324 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
2327 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
2329 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
2332 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
2334 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
2337 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
2339 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
2342 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
2344 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
2347 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
2349 return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
2352 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
2354 return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
2357 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
2359 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
2362 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
2364 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
2367 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
2369 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2372 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
2374 return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);