arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17
  18 #include <asm/spec-ctrl.h>
  19 #include <asm/cmdline.h>
  20 #include <asm/bugs.h>
  21 #include <asm/processor.h>
  22 #include <asm/processor-flags.h>
  23 #include <asm/fpu/internal.h>
  24 #include <asm/msr.h>
  25 #include <asm/paravirt.h>
  26 #include <asm/alternative.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/set_memory.h>
  29 #include <asm/intel-family.h>
  30
  31 static void __init spectre_v2_select_mitigation(void);
  32 static void __init ssb_select_mitigation(void);
  33
  34 /*
  35  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  36  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  37  */
  38 u64 __ro_after_init x86_spec_ctrl_base;
  39
  40 /*
  41  * The vendor and possibly platform specific bits which can be modified in
  42  * x86_spec_ctrl_base.
  43  */
  44 static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;
  45
  46 /*
  47  * AMD specific MSR info for Speculative Store Bypass control.
  48  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  49  */
  50 u64 __ro_after_init x86_amd_ls_cfg_base;
  51 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  52
  53 void __init check_bugs(void)
  54 {
  55         identify_boot_cpu();
  56
  57         if (!IS_ENABLED(CONFIG_SMP)) {
  58                 pr_info("CPU: ");
  59                 print_cpu_info(&boot_cpu_data);
  60         }
  61
  62         /*
  63          * Read the SPEC_CTRL MSR to account for reserved bits which may
  64          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  65          * init code as it is not enumerated and depends on the family.
  66          */
  67         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  68                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  69
  70         /* Select the proper spectre mitigation before patching alternatives */
  71         spectre_v2_select_mitigation();
  72
  73         /*
  74          * Select proper mitigation for any exposure to the Speculative Store
  75          * Bypass vulnerability.
  76          */
  77         ssb_select_mitigation();
  78
  79 #ifdef CONFIG_X86_32
  80         /*
  81          * Check whether we are able to run this kernel safely on SMP.
  82          *
  83          * - i386 is no longer supported.
  84          * - In order to run on anything without a TSC, we need to be
  85          *   compiled for a i486.
  86          */
  87         if (boot_cpu_data.x86 < 4)
  88                 panic("Kernel requires i486+ for 'invlpg' and other features");
  89
  90         init_utsname()->machine[1] =
  91                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
  92         alternative_instructions();
  93
  94         fpu__init_check_bugs();
  95 #else /* CONFIG_X86_64 */
  96         alternative_instructions();
  97
  98         /*
  99          * Make sure the first 2MB area is not mapped by huge pages
 100          * There are typically fixed size MTRRs in there and overlapping
 101          * MTRRs into large pages causes slow downs.
 102          *
 103          * Right now we don't do that with gbpages because there seems
 104          * very little benefit for that case.
 105          */
 106         if (!direct_gbpages)
 107                 set_memory_4k((unsigned long)__va(0), 1);
 108 #endif
 109 }
 110
 111 /* The kernel command line selection */
 112 enum spectre_v2_mitigation_cmd {
 113         SPECTRE_V2_CMD_NONE,
 114         SPECTRE_V2_CMD_AUTO,
 115         SPECTRE_V2_CMD_FORCE,
 116         SPECTRE_V2_CMD_RETPOLINE,
 117         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 118         SPECTRE_V2_CMD_RETPOLINE_AMD,
 119 };
 120
 121 static const char *spectre_v2_strings[] = {
 122         [SPECTRE_V2_NONE]                       = "Vulnerable",
 123         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 124         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 125         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 126         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 127 };
 128
 129 #undef pr_fmt
 130 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 131
 132 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 133         SPECTRE_V2_NONE;
 134
 135 void x86_spec_ctrl_set(u64 val)
 136 {
 137         if (val & x86_spec_ctrl_mask)
 138                 WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
 139         else
 140                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
 141 }
 142 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);
 143
 144 u64 x86_spec_ctrl_get_default(void)
 145 {
 146         u64 msrval = x86_spec_ctrl_base;
 147
 148         if (static_cpu_has(X86_FEATURE_SPEC_CTRL))
 149                 msrval |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
 150         return msrval;
 151 }
 152 EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);
 153
 154 /**
 155  * x86_spec_ctrl_set_guest - Set speculation control registers for the guest
 156  * @guest_spec_ctrl:            The guest content of MSR_SPEC_CTRL
 157  * @guest_virt_spec_ctrl:       The guest controlled bits of MSR_VIRT_SPEC_CTRL
 158  *                              (may get translated to MSR_AMD64_LS_CFG bits)
 159  *
 160  * Avoids writing to the MSR if the content/bits are the same
 161  */
 162 void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)
 163 {
 164         u64 host = x86_spec_ctrl_base;
 165
 166         /* Is MSR_SPEC_CTRL implemented ? */
 167         if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 168                 return;
 169
 170         /* SSBD controlled in MSR_SPEC_CTRL */
 171         if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
 172                 host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
 173
 174         if (host != guest_spec_ctrl)
 175                 wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl);
 176 }
 177 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest);
 178
 179 /**
 180  * x86_spec_ctrl_restore_host - Restore host speculation control registers
 181  * @guest_spec_ctrl:            The guest content of MSR_SPEC_CTRL
 182  * @guest_virt_spec_ctrl:       The guest controlled bits of MSR_VIRT_SPEC_CTRL
 183  *                              (may get translated to MSR_AMD64_LS_CFG bits)
 184  *
 185  * Avoids writing to the MSR if the content/bits are the same
 186  */
 187 void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)
 188 {
 189         u64 host = x86_spec_ctrl_base;
 190
 191         /* Is MSR_SPEC_CTRL implemented ? */
 192         if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 193                 return;
 194
 195         /* SSBD controlled in MSR_SPEC_CTRL */
 196         if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
 197                 host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
 198
 199         if (host != guest_spec_ctrl)
 200                 wrmsrl(MSR_IA32_SPEC_CTRL, host);
 201 }
 202 EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host);
 203
 204 static void x86_amd_ssb_disable(void)
 205 {
 206         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 207
 208         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 209                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 210         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 211                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 212 }
 213
 214 #ifdef RETPOLINE
 215 static bool spectre_v2_bad_module;
 216
 217 bool retpoline_module_ok(bool has_retpoline)
 218 {
 219         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 220                 return true;
 221
 222         pr_err("System may be vulnerable to spectre v2\n");
 223         spectre_v2_bad_module = true;
 224         return false;
 225 }
 226
 227 static inline const char *spectre_v2_module_string(void)
 228 {
 229         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 230 }
 231 #else
 232 static inline const char *spectre_v2_module_string(void) { return ""; }
 233 #endif
 234
 235 static void __init spec2_print_if_insecure(const char *reason)
 236 {
 237         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 238                 pr_info("%s selected on command line.\n", reason);
 239 }
 240
 241 static void __init spec2_print_if_secure(const char *reason)
 242 {
 243         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 244                 pr_info("%s selected on command line.\n", reason);
 245 }
 246
 247 static inline bool retp_compiler(void)
 248 {
 249         return __is_defined(RETPOLINE);
 250 }
 251
 252 static inline bool match_option(const char *arg, int arglen, const char *opt)
 253 {
 254         int len = strlen(opt);
 255
 256         return len == arglen && !strncmp(arg, opt, len);
 257 }
 258
 259 static const struct {
 260         const char *option;
 261         enum spectre_v2_mitigation_cmd cmd;
 262         bool secure;
 263 } mitigation_options[] = {
 264         { "off",               SPECTRE_V2_CMD_NONE,              false },
 265         { "on",                SPECTRE_V2_CMD_FORCE,             true },
 266         { "retpoline",         SPECTRE_V2_CMD_RETPOLINE,         false },
 267         { "retpoline,amd",     SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
 268         { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
 269         { "auto",              SPECTRE_V2_CMD_AUTO,              false },
 270 };
 271
 272 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 273 {
 274         char arg[20];
 275         int ret, i;
 276         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
 277
 278         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 279                 return SPECTRE_V2_CMD_NONE;
 280         else {
 281                 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
 282                 if (ret < 0)
 283                         return SPECTRE_V2_CMD_AUTO;
 284
 285                 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
 286                         if (!match_option(arg, ret, mitigation_options[i].option))
 287                                 continue;
 288                         cmd = mitigation_options[i].cmd;
 289                         break;
 290                 }
 291
 292                 if (i >= ARRAY_SIZE(mitigation_options)) {
 293                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 294                         return SPECTRE_V2_CMD_AUTO;
 295                 }
 296         }
 297
 298         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
 299              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
 300              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
 301             !IS_ENABLED(CONFIG_RETPOLINE)) {
 302                 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
 303                 return SPECTRE_V2_CMD_AUTO;
 304         }
 305
 306         if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
 307             boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 308                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 309                 return SPECTRE_V2_CMD_AUTO;
 310         }
 311
 312         if (mitigation_options[i].secure)
 313                 spec2_print_if_secure(mitigation_options[i].option);
 314         else
 315                 spec2_print_if_insecure(mitigation_options[i].option);
 316
 317         return cmd;
 318 }
 319
 320 /* Check for Skylake-like CPUs (for RSB handling) */
 321 static bool __init is_skylake_era(void)
 322 {
 323         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 324             boot_cpu_data.x86 == 6) {
 325                 switch (boot_cpu_data.x86_model) {
 326                 case INTEL_FAM6_SKYLAKE_MOBILE:
 327                 case INTEL_FAM6_SKYLAKE_DESKTOP:
 328                 case INTEL_FAM6_SKYLAKE_X:
 329                 case INTEL_FAM6_KABYLAKE_MOBILE:
 330                 case INTEL_FAM6_KABYLAKE_DESKTOP:
 331                         return true;
 332                 }
 333         }
 334         return false;
 335 }
 336
 337 static void __init spectre_v2_select_mitigation(void)
 338 {
 339         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 340         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 341
 342         /*
 343          * If the CPU is not affected and the command line mode is NONE or AUTO
 344          * then nothing to do.
 345          */
 346         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 347             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 348                 return;
 349
 350         switch (cmd) {
 351         case SPECTRE_V2_CMD_NONE:
 352                 return;
 353
 354         case SPECTRE_V2_CMD_FORCE:
 355         case SPECTRE_V2_CMD_AUTO:
 356                 if (IS_ENABLED(CONFIG_RETPOLINE))
 357                         goto retpoline_auto;
 358                 break;
 359         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 360                 if (IS_ENABLED(CONFIG_RETPOLINE))
 361                         goto retpoline_amd;
 362                 break;
 363         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 364                 if (IS_ENABLED(CONFIG_RETPOLINE))
 365                         goto retpoline_generic;
 366                 break;
 367         case SPECTRE_V2_CMD_RETPOLINE:
 368                 if (IS_ENABLED(CONFIG_RETPOLINE))
 369                         goto retpoline_auto;
 370                 break;
 371         }
 372         pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
 373         return;
 374
 375 retpoline_auto:
 376         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 377         retpoline_amd:
 378                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 379                         pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
 380                         goto retpoline_generic;
 381                 }
 382                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 383                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 384                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 385                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 386         } else {
 387         retpoline_generic:
 388                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 389                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 390                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 391         }
 392
 393         spectre_v2_enabled = mode;
 394         pr_info("%s\n", spectre_v2_strings[mode]);
 395
 396         /*
 397          * If neither SMEP nor PTI are available, there is a risk of
 398          * hitting userspace addresses in the RSB after a context switch
 399          * from a shallow call stack to a deeper one. To prevent this fill
 400          * the entire RSB, even when using IBRS.
 401          *
 402          * Skylake era CPUs have a separate issue with *underflow* of the
 403          * RSB, when they will predict 'ret' targets from the generic BTB.
 404          * The proper mitigation for this is IBRS. If IBRS is not supported
 405          * or deactivated in favour of retpolines the RSB fill on context
 406          * switch is required.
 407          */
 408         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
 409              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
 410                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 411                 pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
 412         }
 413
 414         /* Initialize Indirect Branch Prediction Barrier if supported */
 415         if (boot_cpu_has(X86_FEATURE_IBPB)) {
 416                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
 417                 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
 418         }
 419
 420         /*
 421          * Retpoline means the kernel is safe because it has no indirect
 422          * branches. But firmware isn't, so use IBRS to protect that.
 423          */
 424         if (boot_cpu_has(X86_FEATURE_IBRS)) {
 425                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
 426                 pr_info("Enabling Restricted Speculation for firmware calls\n");
 427         }
 428 }
 429
 430 #undef pr_fmt
 431 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 432
 433 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 434
 435 /* The kernel command line selection */
 436 enum ssb_mitigation_cmd {
 437         SPEC_STORE_BYPASS_CMD_NONE,
 438         SPEC_STORE_BYPASS_CMD_AUTO,
 439         SPEC_STORE_BYPASS_CMD_ON,
 440         SPEC_STORE_BYPASS_CMD_PRCTL,
 441         SPEC_STORE_BYPASS_CMD_SECCOMP,
 442 };
 443
 444 static const char *ssb_strings[] = {
 445         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 446         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 447         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 448         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 449 };
 450
 451 static const struct {
 452         const char *option;
 453         enum ssb_mitigation_cmd cmd;
 454 } ssb_mitigation_options[] = {
 455         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 456         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 457         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 458         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 459         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 460 };
 461
 462 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 463 {
 464         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 465         char arg[20];
 466         int ret, i;
 467
 468         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 469                 return SPEC_STORE_BYPASS_CMD_NONE;
 470         } else {
 471                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 472                                           arg, sizeof(arg));
 473                 if (ret < 0)
 474                         return SPEC_STORE_BYPASS_CMD_AUTO;
 475
 476                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 477                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 478                                 continue;
 479
 480                         cmd = ssb_mitigation_options[i].cmd;
 481                         break;
 482                 }
 483
 484                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 485                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 486                         return SPEC_STORE_BYPASS_CMD_AUTO;
 487                 }
 488         }
 489
 490         return cmd;
 491 }
 492
 493 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 494 {
 495         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 496         enum ssb_mitigation_cmd cmd;
 497
 498         if (!boot_cpu_has(X86_FEATURE_SSBD))
 499                 return mode;
 500
 501         cmd = ssb_parse_cmdline();
 502         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 503             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 504              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 505                 return mode;
 506
 507         switch (cmd) {
 508         case SPEC_STORE_BYPASS_CMD_AUTO:
 509         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 510                 /*
 511                  * Choose prctl+seccomp as the default mode if seccomp is
 512                  * enabled.
 513                  */
 514                 if (IS_ENABLED(CONFIG_SECCOMP))
 515                         mode = SPEC_STORE_BYPASS_SECCOMP;
 516                 else
 517                         mode = SPEC_STORE_BYPASS_PRCTL;
 518                 break;
 519         case SPEC_STORE_BYPASS_CMD_ON:
 520                 mode = SPEC_STORE_BYPASS_DISABLE;
 521                 break;
 522         case SPEC_STORE_BYPASS_CMD_PRCTL:
 523                 mode = SPEC_STORE_BYPASS_PRCTL;
 524                 break;
 525         case SPEC_STORE_BYPASS_CMD_NONE:
 526                 break;
 527         }
 528
 529         /*
 530          * We have three CPU feature flags that are in play here:
 531          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 532          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 533          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 534          */
 535         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 536                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 537                 /*
 538                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
 539                  * a completely different MSR and bit dependent on family.
 540                  */
 541                 switch (boot_cpu_data.x86_vendor) {
 542                 case X86_VENDOR_INTEL:
 543                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 544                         x86_spec_ctrl_mask &= ~SPEC_CTRL_SSBD;
 545                         x86_spec_ctrl_set(SPEC_CTRL_SSBD);
 546                         break;
 547                 case X86_VENDOR_AMD:
 548                         x86_amd_ssb_disable();
 549                         break;
 550                 }
 551         }
 552
 553         return mode;
 554 }
 555
 556 static void ssb_select_mitigation(void)
 557 {
 558         ssb_mode = __ssb_select_mitigation();
 559
 560         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 561                 pr_info("%s\n", ssb_strings[ssb_mode]);
 562 }
 563
 564 #undef pr_fmt
 565 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 566
 567 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 568 {
 569         bool update;
 570
 571         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 572             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 573                 return -ENXIO;
 574
 575         switch (ctrl) {
 576         case PR_SPEC_ENABLE:
 577                 /* If speculation is force disabled, enable is not allowed */
 578                 if (task_spec_ssb_force_disable(task))
 579                         return -EPERM;
 580                 task_clear_spec_ssb_disable(task);
 581                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 582                 break;
 583         case PR_SPEC_DISABLE:
 584                 task_set_spec_ssb_disable(task);
 585                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 586                 break;
 587         case PR_SPEC_FORCE_DISABLE:
 588                 task_set_spec_ssb_disable(task);
 589                 task_set_spec_ssb_force_disable(task);
 590                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 591                 break;
 592         default:
 593                 return -ERANGE;
 594         }
 595
 596         /*
 597          * If being set on non-current task, delay setting the CPU
 598          * mitigation until it is next scheduled.
 599          */
 600         if (task == current && update)
 601                 speculative_store_bypass_update();
 602
 603         return 0;
 604 }
 605
 606 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 607                              unsigned long ctrl)
 608 {
 609         switch (which) {
 610         case PR_SPEC_STORE_BYPASS:
 611                 return ssb_prctl_set(task, ctrl);
 612         default:
 613                 return -ENODEV;
 614         }
 615 }
 616
 617 #ifdef CONFIG_SECCOMP
 618 void arch_seccomp_spec_mitigate(struct task_struct *task)
 619 {
 620         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 621                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 622 }
 623 #endif
 624
 625 static int ssb_prctl_get(struct task_struct *task)
 626 {
 627         switch (ssb_mode) {
 628         case SPEC_STORE_BYPASS_DISABLE:
 629                 return PR_SPEC_DISABLE;
 630         case SPEC_STORE_BYPASS_SECCOMP:
 631         case SPEC_STORE_BYPASS_PRCTL:
 632                 if (task_spec_ssb_force_disable(task))
 633                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 634                 if (task_spec_ssb_disable(task))
 635                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 636                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 637         default:
 638                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 639                         return PR_SPEC_ENABLE;
 640                 return PR_SPEC_NOT_AFFECTED;
 641         }
 642 }
 643
 644 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 645 {
 646         switch (which) {
 647         case PR_SPEC_STORE_BYPASS:
 648                 return ssb_prctl_get(task);
 649         default:
 650                 return -ENODEV;
 651         }
 652 }
 653
 654 void x86_spec_ctrl_setup_ap(void)
 655 {
 656         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 657                 x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
 658
 659         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 660                 x86_amd_ssb_disable();
 661 }
 662
 663 #ifdef CONFIG_SYSFS
 664
 665 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 666                                char *buf, unsigned int bug)
 667 {
 668         if (!boot_cpu_has_bug(bug))
 669                 return sprintf(buf, "Not affected\n");
 670
 671         switch (bug) {
 672         case X86_BUG_CPU_MELTDOWN:
 673                 if (boot_cpu_has(X86_FEATURE_PTI))
 674                         return sprintf(buf, "Mitigation: PTI\n");
 675
 676                 break;
 677
 678         case X86_BUG_SPECTRE_V1:
 679                 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
 680
 681         case X86_BUG_SPECTRE_V2:
 682                 return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
 683                                boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
 684                                boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
 685                                spectre_v2_module_string());
 686
 687         case X86_BUG_SPEC_STORE_BYPASS:
 688                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 689
 690         default:
 691                 break;
 692         }
 693
 694         return sprintf(buf, "Vulnerable\n");
 695 }
 696
 697 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
 698 {
 699         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 700 }
 701
 702 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
 703 {
 704         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 705 }
 706
 707 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
 708 {
 709         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 710 }
 711
 712 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 713 {
 714         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 715 }
 716 #endif